Abstract
Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.
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Schedule a callMore From: IEEE Transactions on Device and Materials Reliability
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