Stress Current Slew Rate Sensitivity of an Ultra-High-Speed Interface IC

Abstract

This study analyzes the Electrostatic Discharge (ESD) susceptibility of a 28nm high-speed CMOS Integrated Circuit (IC) for network applications (25Gbps), showing a non-negligible failure rate in manufacturing after having passed Charged Device Model (CDM) qualification testing. A detailed inspection of each process step identified the press-fit assembly of charged through-hole connectors to be the root cause for ultra-fast discharges through the Printed Circuit Board (PCB) traces into the high-speed RF interface. Extended CDM tests of the high-speed ICs displayed a wide overlap of pass and fail not allowing for a clear conclusion regarding the CDM robustness. Only the single digit ps-resolution and precision of the highly reproducible test method Capacitively Coupled Transmission Line Pulsing (CC-TLP) allowed a conclusive sharp pass/fail transition at a certain peak current level. In combination with a 33/63GHz single shot oscilloscope, it eventually identified the stress current slew rate to have a direct influence on the failure threshold, explaining the non-conclusive failure distribution of CDM. For this result, we had to increase the bandwidth of the CC-TLP setup, challenge the limits of today’s metrology and test setups, and implement post measurement embedding/de-embedding techniques. By pushing the frontiers of today’s ESD testing in the CDM domain, the outcome of this study should contribute to future standardization of CDM and CC-TLP.