Conductance Of Field-effect Transistors Research Articles

Surface-modified polydimethylsiloxane with soft-plasma as dielectric layer for flexible artificial synaptic transistors

The conductance of field-effect transistors (FETs) can be effectively stimulated by electrical or optical pulses, which could be potentially applied as artificial synapses. The combination of solution processable elastomers with polymer semiconductors has attracted extensive interest in all-polymer flexible synaptic electronics, due to the flexible and light weight property. In this work, a glow-discharge soft-plasma is utilized to treat the widely-used elastomer polydimethylsiloxane (PDMS) layer. Subsequently, the surface energy of PDMS is increased, from the contact angle of 100° to fully spread state and induce high charge trapping density (Δn, about 1.9 × 1012 cm−2 under 525 nm green light irradiation and positive gate-bias stress) on the surface. The PDMS surface are homogenously etched by soft plasma without damaging underneath materials, which can be used as dielectric layer in organic FETs. Thus, prepared organic FETs warrant quick charge transfer dynamics between PDMS surface and semiconductor layer. Upon which, flexible synaptic FETs are demonstrated, corresponding synaptic functions like excitatory postsynaptic current (EPSC), paired pulse facilitation (PPF), short-term plasticity (STP) are all realized. Furthermore, the handwritten digits with an accuracy of 86.2% are realized utilizing prepared synaptic devices.

Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

Current electronics technology increasingly demands higher integration, flexibility, higher efficiency, and performance aspects such as compatibility with higher temperature operation of the semiconductor devices, which may find limitations when silicon is used. The superior intrinsic properties of SiC, eventually combined with the ability of growing monolithically epitaxial, high quality graphene on a SiC wafer (1), makes it a reliable alternative for some electronic applications, such as field effect transistors (FET), radio frequency (RF) power amplifiers, integrated circuits (IC), or sensors. In this work, we describe the fabrication and preliminary electrical characterizations of epitaxial graphene (EG) on a SiC substrate FET devices based on an alternative back gate architecture. We propose a new approach in which the FET device is built on a 4◦ off-axis cut, N+ doped 4H-SiC substrate (the back gate) with, on top of, it a 1μm semi-insulating homoepitaxial layer of SiC compensated with vanadium (the dielectric layer). EG will be used as FET conduction channel. Using this V-compensated dielectric layer is aimed to minimize effects on the FET characteristics such as from defects in the SiC crystal, especially below the FET active areas, which would have occurred when using ion implantation to create a buried gate. The EG film was grown by the high temperature Si sublimation method under an Ar ambient. Raman spectroscopy, Atomic Force Microscopy (AFM) and Scanning Electron Microscopy (SEM) were applied in the structural characterization of epigraphene. The lack of D-peak in Raman spectra, together with SEM and AFM images, indicate that high quality monolayer to few layer epitaxial graphene fully covering the SiC surface is deposited. The electrical characteristics of the EG channel-devices and the functionality of the bottom gate were examined with 2-probe and 4-probe method. The electrical properties of the FET devices were also investigated with 3 terminal configuration.

Leakage mechanism in Al x Ga1−x N/GaN heterostructures with AlN interlayer

Leakage of Al x Ga1−x N/GaN heterostructures was investigated by admittance–voltage profiling. Nominally undoped structures were grown by low-pressure metal-organic vapor-phase epitaxy. The investigated structures had an Al-content of 30%. They are compared to structures with an additional 1 nm thick AlN interlayer placed before the Al0.3Ga0.7N layer growth, originally to improve device performance. Conductance of field effect transistor devices with AlN interlayer, measured from depletion of the two-dimensional electron gas (2DEG) to zero volt bias at frequencies ranging from 50 Hz to 10 kHz, could be described by free charge carriers using a Drude model. The voltage dependent conductance shows a behavior described by either Poole-Frenkel emission or Schottky emission (SE). From the size of the conductance, as well as simulation of the tunneling current injected from the gate under off-state conditions by universal Schottky tunneling, SE is obvious. Evaluating the data by SE, we can locate the leakage path, of tens of nm in the range between gate and drain/source with contact to the 2DEG, originating from the AlN interlayer. The static dielectric constant in growth direction, necessary for the evaluation, is determined from various Al x Ga1−x N/GaN heterostructures to ϵ ||(0) = 10.7 ± 0.1.

Formation of quantum dots in GaN/AlGaN FETs

GaN and the heterostructures are attractive in condensed matter science and applications for electronic devices. We measure the electron transport in GaN/AlGaN field-effect transistors (FETs) at cryogenic temperature. We observe formation of quantum dots in the conduction channel near the depletion of the 2-dimensional electron gas (2DEG). Multiple quantum dots are formed in the disordered potential induced by impurities in the FET conduction channel. We also measure the gate insulator dependence of the transport properties. These results can be utilized for the development of quantum dot devices utilizing GaN/AlGaN heterostructures and evaluation of the impurities in GaN/AlGaN FET channels.

Bulk transport and contact limitation of MoS2 multilayer flake transistors untangled via temperature-dependent transport measurements

Rational use of novel high-performance semiconductors in field-effect transistors (FETs) requires exact knowledge of the dominating charge transport mechanisms. In particular, the distinction between contact- and semiconductor-limited transport is important in FETs with small channel lengths. Here, we analyze the relative contributions of contact limitation and intrinsic conductivity of FETs based on mechanically exfoliated multilayers of the high performance n-type semiconductor molybdenum disulfide (MoS2). Based on a lithography-free fabrication process, we realize FETs with room temperature mobility (μ) of up to 46.8 cm2/Vs and ION/IOFF ratio of up to 105. Using temperature- and bias-dependent charge transport measurements, we are able to show that the intrinsic bulk transport in the flake can be best described by a phonon-limited band transport model with a conductive bulk at room temperature that freezes out upon cooling of the sample. In addition, we notice an increase of μ by a factor of 2–5 when using a self-assembled monolayer (SAM)-modified SiO2/MoS2 interface. More importantly, we show that the choice of drain–source bias (VDS) is crucial when interpreting MoS2 transport measurements, while for large VDS the intrinsic semiconductor transport properties can be observed, a strong contact limitation appears at low VDS. Our combined measurements allow us to distinguish between the effect of bulk and semiconductor/dielectric interface transport and the effect of contact resistance on the electrical transport properties.

Electric control of spin in monolayer WSe2 field effect transistors

We report first-principles theoretical investigations of quantum transport in a monolayer WSe2 field effect transistor (FET). Due to strong spin–orbit interaction (SOI) and the atomic structure of the two-dimensional lattice, monolayer WSe2 has an electronic structure that exhibits Zeeman-like up–down spin texture near the K and points of the Brillouin zone. In a FET, the gate electric field induces an extra, externally tunable SOI that re-orients the spins into a Rashba-like texture thereby realizing electric control of the spin. The conductance of FET is modulated by the spin texture, namely by if the spin orientation of the carrier after the gated channel region, matches or miss-matches that of the FET drain electrode. The carrier current in the FET is labelled by both the valley index and spin index, realizing valleytronics and spintronics in the same device.

Poly(p-phenylenevinylene)-based field-effect transistors with platinum source-drain electrodes

Organic field-effect transistors (FETs) have been fabricated by using poly(p-phenylenevinylene) (PPV) films prepared from a water soluble precursor polymer and p-channel FET conduction was obtained by using platinum source-drain electrodes. When the conversion temperatures for preparing PPV films changed between 180 and 280 °C, the field-effect hole mobilities changed between 4.3 × 10−4 and 8.4 × 10−6 cm2 V−1 s−1. The highest field-effect hole mobility was seen on the PPV thermally converted at 180 °C. The decreases in field-effect mobilities in the PPV films with further extended average π-conjugation length converted at higher temperatures were ascribed to morphological defects owing to crystallization.

Room-temperature single charge sensitivity in carbon nanotube field-effect transistors

Electrical current fluctuation studies are reported for coaxial p-type and n-type single-wall carbon nanotube field-effect transistors (FETs). Abrupt discrete switching of the source-drain current is observed at room temperature. The authors attribute these random telegraph signals to charge fluctuating electron traps near the FET conduction channels. Evolution of the current-switching behavior associated with the occupancy of individual electron traps is demonstrated and analyzed statistically. The result strongly indicates room temperature single charge sensitivity in carbon nanotube FETs, which may offer potential applications for single molecule sensors based on suitably prepared FET devices.

P- and n-Type Charge Transport in Field-Effect Transistors of Pristine Poly(p-Phenylenevinylene)

ABSTRACTPoly(p-phenylenevinylene) (PPV) thin films were prepared by using drop casting under high gravity condition and p- and n-type PPV based field effect transistors (FET) have been fabricated. PPV FETs with gold source-drain electrodes showed the p-channel FET conduction. The FET characteristics of PPV were improved by annealing and the field-effect hole mobility was 8.8×10−4cm2V−1s−1. On the other hand, PPV FET with calcium source-drain electrodes showed the n-channel FET conduction and the field-effect electron mobility was 1.0×10−6cm2V−1s−1.

General observation of n-type field-effect behaviour in organic semiconductors

Organic semiconductors have been the subject of active research for over a decade now, with applications emerging in light-emitting displays and printable electronic circuits. One characteristic feature of these materials is the strong trapping of electrons but not holes: organic field-effect transistors (FETs) typically show p-type, but not n-type, conduction even with the appropriate low-work-function electrodes, except for a few special high-electron-affinity or low-bandgap organic semiconductors. Here we demonstrate that the use of an appropriate hydroxyl-free gate dielectric--such as a divinyltetramethylsiloxane-bis(benzocyclobutene) derivative (BCB; ref. 6)--can yield n-channel FET conduction in most conjugated polymers. The FET electron mobilities thus obtained reveal that electrons are considerably more mobile in these materials than previously thought. Electron mobilities of the order of 10(-3) to 10(-2) cm(2) V(-1) s(-1) have been measured in a number of polyfluorene copolymers and in a dialkyl-substituted poly(p-phenylenevinylene), all in the unaligned state. We further show that the reason why n-type behaviour has previously been so elusive is the trapping of electrons at the semiconductor-dielectric interface by hydroxyl groups, present in the form of silanols in the case of the commonly used SiO2 dielectric. These findings should therefore open up new opportunities for organic complementary metal-oxide semiconductor (CMOS) circuits, in which both p-type and n-type behaviours are harnessed.

Nanomatertials as Low Density Lipoprotein (LDL) Sensors

ABSTRACTIn2O3nanowire and carbon nanotube transistors were used to study the chemical gating effects in response to LDL particles. Low density lipoprotein (LDL) cholesterol in blood constitutes a risk factor for coronary artery disease (heart attack). The interactions of LDL particles with these two different surfaces were investigated. The degree of LDL particles binding to carbon nanotubes was ten-fold higher than to In2O3nanowires possibly owing to the hydrophobic/hydrophilic interactions. The conductance of field effect transistors (FET) based on nanowires and nanotubes showed complementary responses after exposure to LDL particles. While In2O3nanowire transistors exhibited higher conductance accompanied by a negative shift of the threshold voltage, nanotube transistors displayed a lower conductance. This phenomenon was attributed to the complementary doping between the n-type In2O3nanowires and p-type carbon nanotubes.

Ballistic transport in nanoscale field effect transistors revealed by four-terminal DC characterization

We show that four-terminal measurements of the differential conductance of field effect transistors (FETs) can provide important insights into the transport mechanism, and in particular can reveal the presence of ballistic transport. Measurements and simulations of purposely fabricated AlGaAs–GaAs heterostructure FETs show that ballistic transport results in a pronounced peak in the derivative of the differential conductance versus the gate voltage, which splits into two peaks with increasing drain-to-source voltage. Analyzing the four-probe conductance, ballistic electron transport through the channel is revealed as the origin of the observed peak splitting.