Field-effect Transistor Devices Research Articles

Low-Cost Shadow Mask Fabrication for Nanoelectronics

We present two approaches for fabricating shadow masks for the evaporation of electrodes onto nanomaterials. In the first one, we combine the use of a commercial fiber laser engraving system with readily available aluminum foil. This method is suitable for fabricating shadow masks with line widths of 50 µm and minimum feature separation of 20 µm, and using it to create masks with complex patterns is very straightforward. In the second approach, we use a commercially available vinyl cutting machine to pattern a vinyl stencil mask, and we use a glass fiber to define the separation between the electrodes. With this approach, we achieve well-defined electrodes separated by 15 µm, but this technique is less versatile in creating complex masks as compared with the laser-based one. We demonstrate the potential of these techniques by fabricating field-effect transistor devices based on MoS2. Our approach is a cost-effective and easily accessible method for fabricating shadow masks with high resolution and accuracy, making it accessible to a wider range of laboratories.

Edge Contacts to Atomically Precise Graphene Nanoribbons.

Bottom-up-synthesized graphene nanoribbons (GNRs) are an emerging class of designer quantum materials that possess superior properties, including atomically controlled uniformity and chemically tunable electronic properties. GNR-based devices are promising candidates for next-generation electronic, spintronic, and thermoelectric applications. However, due to their extremely small size, making electrical contact with GNRs remains a major challenge. Currently, the most commonly used methods are top metallic electrodes and bottom graphene electrodes, but for both, the contact resistance is expected to scale with overlap area. Here, we develop metallic edge contacts to contact nine-atom-wide armchair GNRs (9-AGNRs) after encapsulation in hexagonal boron-nitride (h-BN), resulting in ultrashort contact lengths. We find that charge transport in our devices occurs via two different mechanisms: at low temperatures (9 K), charges flow through single GNRs, resulting in quantum dot (QD) behavior with well-defined Coulomb diamonds (CDs), with addition energies in the range of 16 to 400 meV. For temperatures above 100 K, a combination of temperature-activated hopping and polaron-assisted tunneling takes over, with charges being able to flow through a network of 9-AGNRs across distances significantly exceeding the length of individual GNRs. At room temperature, our short-channel field-effect transistor devices exhibit on/off ratios as high as 3 × 105 with on-state current up to 50 nA at 0.2 V. Moreover, we find that the contact performance of our edge-contact devices is comparable to that of top/bottom contact geometries but with a significantly reduced footprint. Overall, our work demonstrates that 9-AGNRs can be contacted at their ends in ultra-short-channel FET devices while being encapsulated in h-BN.

Identifying Pauli spin blockade using deep learning

Pauli spin blockade (PSB) can be employed as a great resource for spin qubit initialisation and readout even at elevated temperatures but it can be difficult to identify. We present a machine learning algorithm capable of automatically identifying PSB using charge transport measurements. The scarcity of PSB data is circumvented by training the algorithm with simulated data and by using cross-device validation. We demonstrate our approach on a silicon field-effect transistor device and report an accuracy of 96% on different test devices, giving evidence that the approach is robust to device variability. Our algorithm, an essential step for realising fully automatic qubit tuning, is expected to be employable across all types of quantum dot devices.

Engineering Interface Defects and Interdiffusion at the Degenerate Conductive In2O3/Al2O3 Interface for Stable Electrodes in a Saline Solution.

A low-temperature Al2O3 deposition process provides a simplified method to form a conductive two-dimensional electron gas (2DEG) at the metal oxide/Al2O3 heterointerface. However, the impact of key factors of the interface defects and cation interdiffusion on the interface is still not well understood. Furthermore, there is still a blank space in terms of applications that go beyond the understanding of the interface's electrical conductivity. In this work, we carried out a systematic experimental study by oxygen plasma pretreatment and thermal annealing post-treatment to study the impact of interface defects and cation interdiffusion at the In2O3/Al2O3 interface on the electrical conductance, respectively. Combining the trends in electrical conductance with the structural characteristics, we found that building a sharp interface with a high concentration of interface defects provides a reliable approach to producing such a conductive interface. After applying this conductive interface as electrodes for fabricating a field-effect transistor (FET) device, we found that this interface electrode exhibited ultrastability in phosphate-buffered saline (PBS), a commonly used biological saline solution. This study provides new insights into the formation of conductive 2DEGs at metal oxide/Al2O3 interfaces and lays the foundation for further applications as electrodes in bioelectronic devices.

Implementation of Gate-All-Around Gate-Engineered Charge Plasma Nanowire FET-Based Common Source Amplifier.

This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual-material gate (DMG) and gate stack (GS) as gate engineering techniques and its analog/RF performance parameters are compared to those of the Gate-All-Around Single-Material Gate Charge Plasma Nanowire Field Effect Transistor (GAA-SMG-CP NW-FET) device. Both Gate-All-Around (GAA) devices are designed using the Silvaco TCAD tool. GAA structures have demonstrated good gate control because the gate holds the channel, which is an inherent advantage for both devices discussed herein. The charge plasma dopingless technique is used, in which the source and drain regions are formed using metal contacts and necessary work functions rather than doping. This dopingless technique eliminates the need for doping, reducing fluctuations caused by random dopants and lowering the device's thermal budget. Gate engineering techniques such as DMG and GS significantly improved the current characteristics which played a crucial role in obtaining maximum gain for circuit designs. The lookup table (LUT) approach is used in the implementation of the CS amplifier circuit with the proposed device. The transient response of the circuit is analyzed with both the device structures where the gain achieved for the CS amplifier circuit using the proposed GAA-DMG-GS-CP NW-FET is 15.06 dB. The superior performance showcased by the proposed GAA-DMG-GS-CP NW-FET device with analog, RF and circuit analysis proves its strong candidature for future nanoscale and low-power applications.

Pure edge-contact devices on single-layer-CVD-graphene integrated into a single chip

We present a simple and cost-effective fabrication technique for on-chip integration of pure edge contact two-terminal (2T) and Graphene field effect transistor (GFET) devices with low contact resistance and nonlinear characteristics based on single-layer chemical-vapor-deposited (CVD) graphene. We use a smart print-based mask projection technique with a 10X magnification objective lens for maskless lithography followed by thermal evaporation of the contact material Cr-Pd-Au through three different angles (90° and ± 45°) using a customized inclined-angle sample-holder to control the angle during normal incidence evaporation for edge-contact to graphene. Our fabrication technique, graphene quality, and contact geometry enable pure metal contact to 2D single-layer graphene allowing electron transport through the 1D atomic edge of graphene. Our devices show some signatures of edge contact to graphene in terms of very low contact resistance of 23.5 Ω, the sheet resistance of 11.5 Ω, and sharp nonlinear voltage-current characteristics (VCC) which are highly sensitive to the bias voltage. This study may find application in future graphene-integrated chip-scale passive or active low-power electronic devices.

Ultrahigh breakdown current density of van der Waals one dimensional PdBr2

One-dimensional (1D) van der Waals (vdW) materials offer nearly defect-free strands as channel materials in the field-effect transistor devices and probably, a better interconnect than conventional copper with higher current density and resistance to electro-migration with sustainable down-scaling. We report a theoretically predicted halide based 1D few-chain atomic thread, PdBr2, isolable from its bulk which crystallizes in a monoclinic space group C2/c. Liquid phase exfoliated nanowires with mean length (20 ± 1)μm transferred onto a SiO2/Si wafer with a maximum aspect ratio (length:width) of ≈5000 confirm the lower cleavage energy perpendicular to the chain direction. Moreover, an isolated nanowire can also sustain a current density of 200 MA/cm2, which is atleast one-order higher than typical copper interconnects. However, local transport measurement via the conducting atomic force microscopy (CAFM) tip along the cross direction of the single chain records a much lower current density due to the anisotropic electronic band structure. While 1D nature of the nanoobject can be linked with a non-trivial collective quantum behavior, vdW nature could be beneficial for possible pathways in an interconnect fabrication strategy with better control of placement in an integrated circuit.

Phosphorus deactivation by hydrogen on hot carrier stressed high-voltage N-channel field effect transistor CMOS device demonstrated by scanning capacitance microscopy imaging

Junction profiles of hot electron stressed high-voltage N-channel field effect transistor (NFET) devices were measured by scanning capacitance microscopy. Deactivation of phosphorous was observed on the drain side. To directly establish a link between phosphorus deactivation and hydrogen, junction profiles were measured on an unstressed NFET (N-type metal-oxide-semiconductor) device with and without H2 plasma treatment and with subsequent 400 °C annealing in helium. Phosphorus deactivation was observed in the device after H2 plasma treatment, while subsequent 400 °C annealing led to dissociation of the P–H (or H–Si–P) bond and recovery of the device junctions.

Correlation of Extended Defects with Electrical Yield of SiC MOSFET Devices

The quality of the silicon carbide (SiC) epitaxial layer, i.e., layer homogeneities and extended defect densities, is of highest importance for high power 4H-SiC trench metal-oxide-semiconductor field effect transistors (Trench-MOSFET) devices. Especially, yield for devices with a large chip area is severely impacted by extended defects. Previously, devices had to be fully manufactured to effectively gauge the impact of a reduction in extended defect densities in the epitaxial layers on device yield. The production of devices such as Trench-MOSFETs is an extensive procedure. Therefore, a correlation between extended defects in the epitaxial layer and electrical device failure would allow to reliably estimate the impact of process changes during epitaxial layer deposition on electrical device yield.For this reason, n-type epitaxial layers were grown on around 1,000 commercially available 150 mm 4H-SiC Si-face substrates, which received a chemical wet cleaning prior to the epitaxy deposition. Substrates with lowest micro-pipe density from two different suppliers were used. The wafers were characterized with the corresponding device layout for defects utilizing surface microscopy as well as ultraviolet photoluminescence techniques. Subsequently, these wafers were used to produce more than 500,000 Trench-MOSFET devices. All devices have been tested on wafer level for their initial electrical integrity.With these methods a precise correlation between extended defects in the epitaxial layer and electrical failures on wafer level could be found. The influence of different substrates on the defect-based yield prediction regarding the electrical yield on wafer level is discussed. Additionally, a calculated kill-ratio is presented and the severity of defect classes on initial device failure, e.g., stacking faults, and their key failures modes are discussed.

Progress on Memristor-Based Analog Logic Operation

There is always a need for low-power, area-efficient VLSI (Very Large-Scale Integration) design and this need is increasing day by day. However, conventional design methods based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) technology cannot meet the performance requirements. The memristor, as a promising computing and memory integration device, offers a new research idea for conventional logic circuit structure and architecture innovation, given its non-volatility, scalability, low power consumption, fast switching speed, etc. This paper proposes a brief overview of the characteristics and current status of memristor-based logic circuits and analyzes their applications in numerical expression and memory. The benefits and drawbacks of various analog logic circuit structures are summarized and compared. In addition, some solution strategies for these issues are presented. Finally, this paper offers prospects for the applications of memristors in the logic implementation of large-scale memristor arrays, the novel structure of in-memory computing, and neural network computing.

Metal Contact Induced Unconventional Field Effect in Metallic Carbon Nanotubes.

One-dimensional carbon nanotubes (CNTs) are promising for future nanoelectronics and optoelectronics, and an understanding of electrical contacts is essential for developing these technologies. Although significant efforts have been made in this direction, the quantitative behavior of electrical contacts remains poorly understood. Here, we investigate the effect of metal deformations on the gate voltage dependence of the conductance of metallic armchair and zigzag CNT field effect transistors (FETs). We employ density functional theory calculations of deformed CNTs under metal contacts to demonstrate that the current-voltage characteristics of the FET devices are qualitatively different from those expected for metallic CNT. We predict that, in the case of armchair CNT, the gate-voltage dependence of the conductance shows an ON/OFF ratio of about a factor of two, nearly independent of temperature. We attribute the simulated behavior to modification of the band structure under the metals caused by deformation. Our comprehensive model predicts a distinct feature of conductance modulation in armchair CNTFETs induced by the deformation of the CNT band structure. At the same time, the deformation in zigzag metallic CNTs leads to a band crossing but not to a bandgap opening.

Amplification of ammonia sensing performance through gate induced carrier modulation in Cur-rGO Silk-FET

Uncontrolled human and industrial activities lead to the increase in demand for selective gas sensors for detection of poisonous gases in our environment. Conventional resistive gas sensors suffer from predetermined sensitivity and poor selectivity among gases. This paper demonstrates curcumin reduced graphene oxide-silk field effect transistor for selective and sensitive detection of ammonia in air. The sensing layer was characterized by X-ray diffraction, FESEM and HRTEM to confirm its structural and morphological features. Raman spectroscopy, Fourier transform infrared spectroscopy and X-ray photoelectron spectroscopy was carried out to analyze the functional moieties present in the sensing layer. Curcumin reduced graphene oxide introduces sufficient hydroxyl groups in the sensing layer to provide high degree of selectivity towards ammonia vapors. The performance of the sensor device was evaluated at positive, negative and zero gate voltage. Carrier modulation in the channel through gate electrostatics revealed that the minority carriers (electrons) in p-type reduced graphene oxide plays a pivotal role in enhancement of sensitivity of the sensor device. The sensor response was enhanced to 634% for 50 ppm ammonia at 0.6 V gate voltage compared to 23.2% and 39.3% at 0 V and − 3 V respectively. The sensor exhibited faster response and recovery at 0.6 V owing to higher mobility of electrons and quick charge transfer mechanism. The sensor exhibited satisfactory humidity resistant characteristics and high stability. Hence, curcumin reduced graphene oxide-silk field effect transistor device with proper gate bias elucidates excellent ammonia detection and may be a potential candidate for future room temperature, low power, portable gas detection system.

Bending Stability of Ferroelectric Gated Graphene Field Effect Transistor for Flexible Electronics.

In this work, we explored the potential of the ferroelectric gate of (Pb0.92La0.08)(Zr0.30Ti0.70)O3 (PLZT(8/30/70)) for flexible graphene field effect transistor (GFET) devices. Based on the deep understanding of the VDirac of PLZT(8/30/70) gate GFET, which determines the application of the flexible GFET devices, the polarization mechanisms of PLZT(8/30/70) under bending deformation were analyzed. It was found that both flexoelectric polarization and piezoelectric polarization exist under bending deformation, and their polarization direction is opposite under the same bending deformation. Thus, a relatively stable of VDirac is obtained due to the combination of these two effects. In contrast to the relatively good linear movement of VDirac under bending deformation of relaxor ferroelectric (Pb0.92La0.08)(Zr0.52Ti0.48)O3 (PLZT(8/52/48)) gated GFET, these stable properties of the PLZT(8/30/70) gate GFETs make them have great potential for applications in flexible devices.

Theoretical design of Au–DPPh–Au molecular junction for use in organic field-effect transistors

The electron transport properties of a newly designed model based on the molecular junction of 2,2′,6,6′-tetraphenyl-dipyranylidene (DPPh) between two Au electrodes were investigated. Density functional theory was applied in combination with the non-equilibrium Green's function method. In addition, scanning tunneling microscopy images and rectification ratio were analyzed to show the charge density intensity within the asymmetric and nonlinear behaviors of current (I) at applied voltages (V). The electronic properties, transmission coefficient, and I–V characteristics of the Au–DPPh–Au model along the z-axis are more favorable than that of the model along the y-axis. The different analyses showed that the Au–DPPh–Au model along the z-axis is a suitable molecular junction for use in organic field-effect transistor devices.

Aza-anthradithiophene-based conjugated polymers: Synthesis and field-effect transistor application

Acenedithiophenes are classical fused-ring units for constructing conjugated polymers. In this work, a new aza-anthradithiophene unit has been designed and was for the first time employed as building unit to constructing conjugated polymers for organic field-effect transistors. Two conjugated polymers based on thiophthene (P1) and benzothiadiazole (P2) as co-units were synthesized by Stille and Suzuki coupling reactions, respectively. The thermal stability, optical and electrochemical properties, and microstructure were investigated. Organic field-effect transistor devices based on conjugated polymers as semiconductor layer were also fabricated and two polymers exhibited typical hole transport characteristics with the average field-effect mobility up to 7.9 × 10−4 cm2V−1s−1 and Ion/Ioff ratios over 104.

Tex Se1- x Photodiode Shortwave Infrared Detection and Imaging.

Short-wave infrared detectors are playing an increasingly important role in the fields of autonomous driving, food safety, disease diagnosis and scientific research. However, the mature short-wave infrared camera such as InGaAs has the disadvantage of complexly heterogeneous integration with complementary metal-oxide-semiconductor (CMOS) readout circuits, leading to high cost and low imaging resolution. Herein, we report a low-cost, high-performance, and high-stability Tex Se1- x short-wave infrared photodiode detector. The Tex Se1- x thin film is fabricated through CMOS-compatible low-temperature evaporation and post-annealing process, showcasing the potential of direct integration on the readout circuit. The device demonstrates a broad-spectrum response of 300-1600nm, a room-temperature specific detectivity of 1.0 × 1010 Jones, a -3dB bandwidth up to 116kHz, and a linear dynamic range of over 55dB, achieving the fastest response among Te-based photodiode devices and a dark current density 7 orders of magnitude smaller than Te-based photoconductive and field-effect transistor devices. With a simple Si3 N4 packaging, the detector shows high electric stability and thermal stability, meeting the requirements for vehicular applications. Based on the optimized Tex Se1- x photodiode detector, we demonstrate the applications in material identification and masking imaging. Our work paves a new way for CMOS-compatible infrared imaging chips. This article is protected by copyright. All rights reserved.

High-Contrast Bidirectional Optoelectronic Synapses based on 2D Molecular Crystal Heterojunctions for Motion Detection.

Light-stimulated optoelectronic synaptic devices are fundamental compositions of the neuromorphic vision system. However, there are still huge challenges to achieving both bidirectional synaptic behaviors under light stimuli and high performance. Herein, a bilayer 2D molecular crystal (2DMC) p-n heterojunction is developed to achieve high-performance bidirectional synaptic behaviors. The 2DMC heterojunction-based field effect transistor (FET) devices exhibit typical ambipolar properties and remarkable responsivity (R) of 3.58×104 A W-1 under weak light as low as 0.008mW cm-2 . Excitatory and inhibitory synaptic behaviors are successfully realized by the same light stimuli under different gate voltages. Moreover, a superior contrast ratio (CR) of 1.53×103 is demonstrated by the ultrathin and high-quality 2DMC heterojunction, which transcends previous optoelectronic synapses and enables application for the motion detection of the pendulum. Furthermore, a motion detection network based on the device is developed to detect and recognize classic motion vehicles in road traffic with an accuracy exceeding 90%. This work provides an effective strategy for developing high-contrast bidirectional optoelectronic synapses and shows great potential in the intelligent bionic device and future artificial vision.

Repairing and Preventing Photooxidation of Few-Layer Black Phosphorus with β-Carotene

Few-layer black phosphorus (FLBP), a technologically important 2D material, faces a major hurdle to consumer applications: spontaneous degradation under ambient conditions. Blocking the direct exposure of FLBP to the environment has remained the key strategy to enhance its stability, but this can also limit its utility. In this paper, a more ambitious approach to handling FLBP is reported where not only is FLBP oxidation blocked, but it is also repaired postoxidation. Our approach, inspired by nature, employs the antioxidant molecule β-carotene that protects plants against photooxidative damages to act as a protecting and repairing agent for FLBP. The mechanistic role of β-carotene is established by a suite of spectro-microscopy techniques, in combination with computational studies and biochemical assays. Transconductance studies on FLBP-based field effect transistor (FET) devices further affirm the protective and reparative effects of β-carotene. The outcomes indicate the potential for deploying a plethora of natural antioxidant molecules to enhance the stability of other environmentally sensitive inorganic nanomaterials and expedite their translation for technological and consumer applications.

Platinum contacts for 9-atom-wide armchair graphene nanoribbons

Creating a good contact between electrodes and graphene nanoribbons (GNRs) has been a long-standing challenge in searching for the next GNR-based nanoelectronics. This quest requires the controlled fabrication of sub-20 nm metallic gaps, a clean GNR transfer minimizing damage and organic contamination during the device fabrication, as well as work function matching to minimize the contact resistance. Here, we transfer 9-atom-wide armchair-edged GNRs (9-AGNRs) grown on Au(111)/mica substrates to pre-patterned platinum electrodes, yielding polymer-free 9-AGNR field-effect transistor devices. Our devices have a resistance in the range of 106–108 Ω in the low-bias regime, which is 2–4 orders of magnitude lower than previous reports. Density functional theory calculations combined with the non-equilibrium Green's function method explain the observed p-type electrical characteristics and further demonstrate that platinum gives strong coupling and higher transmission in comparison to other materials, such as graphene.

High-Performance and Robust Spintronic/CNTFET-Based Binarized Neural Network Hardware Accelerator

The convolutional neural network (CNN) is a significant part of the artificial intelligence (AI) systems widely used in different tasks. The binarized neural networks (BNNs) reduce power consumption and hardware overhead to answer the demands for using AI in power-limited applications. In this paper, a BNN hardware accelerator is proposed. The proposed approach is based on a novel nonvolatile XNOR/XOR circuit designed using the magnetic tunnel junction (MTJ) and gate-all-around carbon nanotube field-effect transistor (GAA-CNTFET) devices. The nonvolatility of the proposed design leads to the elimination of external memory access that significantly decreases the data transmission delay and power dissipation. Moreover, it consumes low energy, which is very critical in battery-operated devices. Furthermore, the combinational read circuitry of the proposed design leads to high robustness to process variations. According to the simulation results, our proposed design has a logical error rate of 0.0164%, which is negligible and offers a significantly high network accuracy even in the presence of significant process variations. Our proposed hardware accelerator provides at least 13%, 29%, and 41% improvements regarding power, power delay product (PDP), and area compared to its state-of-the-art counterparts.