Field-effect Transistor Devices Research Articles

Van der Waals Epitaxial Growth of Ultrathin Indium Antimonide on Arbitrary Substrates Through Low-thermal Budget.

III-V semiconductors possess high mobility, high frequency response, and detection sensitivity, making them potentially attractive for beyond-silicon electronics applications. However, the traditional heteroepitaxy of III-V semiconductors is impeded by a significant lattice mismatch and the necessity for extreme vacuum and high temperature conditions due to the low saturated vapor pressures of their constituent metals, thereby impeding their in situ compatibility with flexible substrates and silicon-based circuits. In this study, we present a novel approach to fabricate ultrathin InSb single-crystal nanosheets on arbitrary substrates with a thickness as thin as 2.4nm using low-thermal-budget Van der Waals (vdW) epitaxy through chemical vapor deposition (CVD). In particular, we have successfully achieved in-situ growth on both silicon-based substrates and flexible polyimide substrates. Notably, the growth temperature required for InSb nanosheets (240°C) is significantly lower than that employed in back-end-of-line processes (400°C). The field effect transistor (FET) devices based on fabricated ultrathin InSb nanosheets exhibit ultra-high On-off ratio exceeding 108 and demonstrate minimal gate leakage currents. Furthermore, these ultrathin InSb nanosheet display p-type characteristics with hole mobilities reaching up to 203 cm2v-1s-1 at room temperatures. This study paves the way for achieving heterogeneous integration of III-V semiconductors, ensuring compatibility with existing integrated circuit architecture and facilitating their application in flexible electronics, thereby realizing the potential of III-V nanometer-scale logic transistors. This article is protected by copyright. All rights reserved.

SiX2 (X = S, Se) Nanowire Gate-All-Around MOSFETs for Sub-5 nm Applications.

The gate-all-around (GAA) field-effect transistor (FET) holds great potential to support next-generation integrated circuits. Nanowires such as carbon nanotubes (CNTs) are one important category of channel materials in GAA FETs. Based on first-principles investigations, we propose that SiX2 (X = S, Se) nanowires are promising channel materials that can significantly elevate the performance of GAA FETs. The sub-5 nm SiX2 (X = S, Se) nanowire GAA FETs exhibit excellent ballistic transport properties that meet the requirements of the 2013 International Technology Roadmap for Semiconductors (ITRS). Compared to CNTs, they are also advantageous or at least comparable in terms of gate controllability, device dimensions, etc. Importantly, SiSe2 GAA FETs show superb gate controllability due to the ultralow minimum subthreshold swing (SSmin) that breaks "Boltzmann's tyranny". Moreover, the energy-delay product (EDP) of SiX2 GAA FETs is significantly lower than that of the CNT FETs. These features make SiX2 nanowires ideal channel material in the sub-5 nm GAA FET devices.

Extended-Gate FET Biosensor Based on GaN Micropillar Array and Polycrystalline Layer: Application to Hg2+ Detection in Human Urine.

Owing to the separation of field-effect transistor (FET) devices from sensing environments, extended-gate FET (EGFET) biosensor features high stability and low cost. Herein, a highly sensitive EGFET biosensor based on a GaN micropillar array and polycrystalline layer (GMP) was fabricated, which was prepared by using simple one-step low-temperature MOCVD growth. In order to improve the sensitivity and detection limit of EGFET biosensor, the surface area and the electrical conductivity of extended-gate electrode can be increased by the micropillar array and the polycrystalline layer, respectively. The designed GMP-EGFET biosensor was modified with l-cysteine and applied for Hg2+ detection with a low limit of detection (LOD) of 1 ng/L, a high sensitivity of -16.3 mV/lg(μg/L) and a wide linear range (1 ng/L-24.5 μg/L). In addition, the detection of Hg2+ in human urine was realized with an LOD of 10 ng/L, which was more than 30 times lower than that of reported sensors. To our knowledge, it is the first time that GMP was used as extended-gate of EGFET biosensor.

Ion detection in a DNA nanopore FET device.

An ion detection device that combines a DNA-origami nanopore and a field-effect transistor (FET) was designed and modeled to determine sensitivity of the nanodevice to the local cellular environment. Such devices could be integrated into a live cell, creating an abiotic-biotic interface integrated with semiconductor electronics. A continuum model is used to describe the behavior of ions in an electrolyte solution. The drift-diffusion equations are employed to model the ion distribution, taking into account the electric fields and concentration gradients. This was matched to the results from electric double layer theory to verify applicability of the model to a bio-sensing environment. The FET device combined with the nanopore is shown to have high sensitivity to ion concentration and nanopore geometry, with the electrical double layer behavior governing the device characteristics. A logarithmic relationship was found between ion concentration and a single FET current, generating up to 200nA of current difference with a small applied bias.&#xD.

Benzodipyrrolidone-based Donor-Acceptor Semiconducting Polymers with High Hole Mobility and Noncovalent Conformational Locks

Constructing highly coplanar polymer backbone plays an important role in boosting the carrier mobility of organic field effect transistors (OFETs) devices. In this study, based on noncovalent conformational locks strategy, we synthesized the electron-acceptor (A) monomer via introducing 3-dodecylthiophene on strong electron-deficient planar benzodipyrrolidone and the electron-donor (D) monomers containing different numbers (0-2) of fluorine atoms at different positon. A series of novel D-A copolymers, namely PBDP-F0, PBDP-F1 and PBDP-F2 with different backbone conformational locks through F···S and F···H-C noncovalent interactions, were obtained via Stille polycondensation. For the application in an organic field-effect transistor, all the polymers exhibited p-type charge transport characteristics and good performance with the highest hole mobilities as 0.24 cm2 V-1 s-1 for PBDP-F0, 0.87 cm2 V-1 s-1 for PBDP-F1 and 1.93 cm2 V-1 s-1 for PBDP-F2, respectively. AFM and GIXRD investigations indicated that all polymers take predominantly edge-on orientation packing mode because of the rigid and coplanar backbone conformation and the annealing films exhibited small π-π stacking distances of 3.73, 3.71 and 3.69 Å for PBDP-F0, PBDP-F1 and PBDP-F2 respectively. This work demonstrates that modified BDP-based D-A copolymers with conformational locks has a potential application in the high-performance semiconductor materials.

Process-in-Memory realized by nonvolatile Task-Scheduling and Resource-Sharing XNOR-Net hardware Accelerator architectures

Due to the success of artificial intelligence systems in solving complex problems, these systems have been investigated in many applications. There is an increasing demand for these systems in many new applications. The XNOR-Net, a binary neural network, is a promising candidate for implementing these systems in devices with limited power and hardware resources. Efficient hardware implementation of XNOR-Nets is critical and has been widely investigated in recent research. In this paper, a resource-sharing gate and architecture and a task-scheduling gate and architecture have been proposed. To reduce power consumption, the proposed nonvolatile logic-in-memory gates are designed based on the magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistor (CNTFET) devices. Using the proposed resource-sharing gate for hardware implementation of XNOR-Net minimizes the number of flip-flops, power consumption, PDP, and area by at least 75%, 75%, 60%, and 42%, respectively, as compared to its state-of-the-art counterparts. Also, using the proposed task-scheduling design to implement the XNOR-Net on 2, 4, and 8 datasets, the power consumption is reduced by at least 24%, 54%, and 65%, respectively, compared to its state-of-the-art counterparts .

Three-dimensional Modeling of Core-structured Field Effect Transistor

Objective: In our previous publication, a core-structured field effect transistor (CoreFET) device shows field effect transistor (FET) behavior. In this work, we investigated factors such as the thickness of the film and the channel on the conductivity of the device in order to optimize the geometry to provide guidance on the fabrication of the device with the best performance. Methods: This study uses Silvaco ATLAS numerical simulation software to investigate the performance of CoreFET. The effects of the thickness of the dielectric layer, SiO2, and the distance between the drain and source (channel length) on the conductivity of the semi-conductor indium gallium zinc oxide (IGZO) have been studied. The flat FET models with the same parameters were used for comparison. Results: Our simulation results demonstrate a directed correlation between the optimized conductivity of the device and the thickness of the dielectric material, as well as the length of the channel. Enhanced sensitivity is achievable by employing a thinner dielectric layer and a narrower channel. Conclusion: According to the results, the device can achieve better performance by optimizing the thickness of the insulator and the gap distance between drain and source electrodes. The remarkable similarity between them indicates that the FET effect remained largely unaffected by variations in FET shape. This observation suggests a consistent outcome across FETs, reinforcing the notion that CoreFET exhibits comparable results as those of film FETs. This finding significantly broadens the scope of CoreFET applications.

N‐Type GaSe Thin Flake for Field Effect Transistor, Photodetector, and Optoelectronic Memory

AbstractThe family of 2D chalcogenide semiconductors has been growing rapidly. Metal monochalcogenides, for instance, can enable new possibilities in functional electronics and optoelectronics. A Gallium Selenide (GaSe) thin flake is used to fabricate a back gated field effect transistor (FET) with n‐type conduction behavior and wide hysteresis at the ambient conditions. The device shows high mobility up to 28 cm2 V−1 s−1 with Ion/Ioff ratio over 103. Under the laser exposure, the device shows a decrease in the threshold voltage and a left‐shift of the transfer characteristic with a slight increase in the current. The transfer characteristic exhibits a hysteretic behavior with hysteresis width linearly dependent on the applied gate voltage. Moreover, the GaSe‐based FET shows a photo response with a photoresponsivity of 475 mAW−1 and detectivity of 4.6 × 1012 Jones. The photocurrent rise and decay times are 0.1 and 1.3 s, respectively. Furthermore, the GaSe FET device can be used as a performant memory device with well separated states and memory window enhanced by the laser exposure, confirming an optoelectronic memory class.

Improvement of C-shaped pocket TFET with sandwiched drain for ambipolar performance and analog/RF performance

A novel structure of tunneling field effect transistor device (CSP-SD-TFET) is proposed, which adds a sandwiched drain to the C-shaped pocket TFET (CSP-TFET). This structure can increase the resistance of the drain, share the lateral electric field at the tunneling junction between the channel and the drain, reduce the lateral electric field at the tunneling junction, and suppress the generation of ambipolar current. The DC and analog/RF characteristics of CSP-SD-TFET are simulated and analyzed by Sentaurus TCAD, and the sandwiched structure parameters of the drain are optimized. The results show that the sandwiched drain structure suppresses the ambipolar current and on-state current, so the parameters of the sandwiched drain structure need to be a compromise between low ambipolar current and high on-state current. The optimized CSP-SD-TFET device has good DC characteristics, such as low average subthreshold swing SSavg (12.2mV/dec), high on/off current ratio Ion/Ioff (2.5 × 1011), high on-state current Ion (9.02 × 10−4 A/μm) and low ambipolar current Iamb (5.41 × 10−17A/μm). The RF performance of the CSP-SD-TFET, such as the cut-off frequency fT (1 × 1011 Hz) and gain-bandwidth product GBP (5.66 × 1010 Hz), are improved. It can be seen that the CSP-SD-TFET device not only has good DC characteristics but also improves analog/RF characteristics.

Steep slope threshold switching field‐effect transistors based on 2D heterostructure

AbstractIn dealing with the increasing power dissipation of electronic systems with increasing integration density, a field‐effect transistor (FET) with steep switching slope that overcomes the thermionic limit is vital to achieve low‐power operations. Here, we report two types of threshold switching (TS) FETs based on 2D Van der Waals heterostructures by virtue of the abrupt resistive switching of the hexagonal boron nitride (hBN) TS device. The common hBN dielectric layer functions as the switching medium for the TS device and the gate dielectric for the 2D FET enabling seamless integration of the hBN TS device and baseline 2D FET. TS FET in source configuration by connecting the TS device to the source terminal of the 2D FET offers an ultralow average subthreshold swing (SS) of 1.6 mV/dec over six decades of drain current at room temperature and suppressed leakage current. TS FET in gate configuration by connecting the TS device to the gate terminal of the 2D FET also exhibits steep switching slope with ultralow SS of 10.6 mV/dec. The proposed compact device structures integrating 2D FET and TS device provide a potential approach of monolithic integration toward next‐generation low‐power electronics.

An investigation into the short-circuit characteristics of Sic MOSFET power devices

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) devices exhibit substantial prospects for application under extreme operational conditions, including elevated temperatures, high voltages, and high frequencies. Nevertheless, owing to their distinctive material and structural attributes, SiC MOSFET devices are not devoid of challenges, with the short-circuit phenomenon constituting a pivotal avenue of inquiry. The short-circuit effect pertains to the abrupt escalation of leakage current that these devices might undergo under elevated voltage conditions, thereby exerting a perturbing influence on their stability and reliability. Investigations into the short-circuit effect predominantly revolve around two dimensions: one involves comprehending its underlying physical mechanisms, while the other centers on identifying commensurate remedial approaches.With respect to the underlying physical mechanisms, researchers have discerned that the elevated breakdown field strength and augmented carrier mobility intrinsic to SiC materials engender an augmentation in leakage current, consequently giving rise to the short-circuit effect. Furthermore, factors such as oxide layer anomalies and surface states are also conceivable catalysts for the surge in leakage current. To rectify this predicament, scholars have proffered a panoply of stratagems, encompassing the optimization of material synthesis processes, enhancement of oxide layer quality, refinement of device structural designs, and incorporation of protective circuitry, among others. In summation, the investigation of the short-circuit effect in silicon carbide MOSFET devices is fundamentally aimed at attaining an in-depth comprehension of its causative mechanisms. Moreover, it endeavors to proffer efficacious resolutions conducive to augmenting the reliability and steadfastness of these devices within high-temperature and high-voltage environments, thereby facilitating their widespread integration within the ambit of high-performance power electronics.

Design and Performance Assessment of a Label- free Biosensor utilizing a Novel TFET Configuration

The present study presents an innovative idea: an original design for a label-free biosensor utilizing H-shape channel configuration within a dielectrically modulated (DM) double-gate TFET (DGTFET) framework, which includes the incorporation of a drain pocket (DP). This design concept is introduced In this study, an analytical model for the DM DPDG-TFET has been created for the first time was formulated and subsequently verified through comparison with industry-standard simulation software (Silvaco TCAD). In this paper we have examine both the biosensor's sensitivity and its effectiveness when employed as a tunnel field-effect transistor (TFET) device. A comprehensive analysis of the device's performance has been conducted. The innovative configuration of the suggested TFET results in heightened sensitivity. Incorporating a drain pocket (DP) at the junction between the drain and channel effectively eliminates ambipolarity, showcasing a successful approach. The H-shape DM DPDGTFET design demonstrates its superiority over various devices documented in the literature. The presence or lack of electric charge in various biomolecules is examined in order to evaluate the device's sensitivity as a label-free biosensor.

Diagnostics of Tuberculosis with Single-Walled Carbon Nanotube-Based Field-Effect Transistors.

Tuberculosis (TB) is still threatening millions of people's lives, especially in developing countries. One of the major factors contributing to the ongoing epidemic of TB is the lack of a fast, efficient, and inexpensive diagnostic strategy. In this work, we developed a semiconducting single-walled carbon nanotube (SWCNT)-based field-effect transistor (FET) device functionalized with anti-Mycobacterium tuberculosis antigen 85B antibody (Ab85B) to detect the major M. tuberculosis-secreted antigen 85B (Ag85B). Through optimizing the device fabrication process by evaluating the mass of the antibody and the concentration of the gating electrolyte, our Ab85B-SWCNT FET devices achieved the detection of the Ag85B spiked in phosphate-buffered saline (calibration samples) with a limit of detection (LOD) of 0.05 fg/mL. This SWCNT FET biosensor also showed good sensing performance in biological matrices including artificial sputum and can identify Ag85B in serum after introducing bovine serum albumin (BSA) into the blocking layer. Furthermore, our BSA-blocked Ab85B-SWCNT FET devices can distinguish between TB-positive and -negative clinical samples, promising the application of SWCNT FET devices in point-of-care TB diagnostics. Moreover, the robustness of this SWCNT-based biosensor to the TB diagnosis in blood serum was enhanced by blocking SWCNT devices directly with a glutaraldehyde cross-linked BSA layer, enabling future applications of these SWCNT-based biosensors in clinical testing.

Ultrasensitive detection of miRNA based on single-walled carbon nanotube@MoS2 field-effect transistor regulated by atomic layer deposition

MicroRNAs (miRNAs) act as diagnostic markers for various diseases, and achieving ultra-sensitive detection of miRNAs has an important effect on early disease diagnosis. Field-effect transistor (FET) biosensor exhibits superior sensitivity compared to conventional clinical detection instruments in detecting biomolecules. However, developing high-sensitive FET biosensors for detecting microRNAs remains challenging. In this study, we developed a FET biosensor using MoS2 and a network film of semiconductor single-walled carbon nanotube (SWCNT) as channel materials. The MoS2 cycles were precisely controlled and optimized by atom layer deposition (ALD), and the optimized 3-cycle device exhibited the best performance. This adjustment is beneficial for enhancing the charge transfer between SWCNT and MoS2, as well as improving the on/off ratio and mobility of FET devices. Additionally, the SWCNT@MoS2 structure offers a larger specific surface area, providing more active binding sites on the sensing interface. These two favorable factors contribute to the realization of linear detection miRNA-21 from 1 × 10−17 to 1 × 10−10 mol L−1 in biosensors. The theoretical detection limit of the biosensor is 1.9 × 10−18 mol L−1. This work develops a novel approach to achieve highly sensitive detection of miRNA for high-performance FET biosensors.

The Robust Ferroelectric and Electrical Response in 2D Bi2O2Se Semiconductor

AbstractThe amelioration of atomically thin ferroelectric materials is imperative for next‐generation outperformed two‐dimensional (2D) electronics, which is elusive by their bulk counterparts. These remarkable materials’ ferroelectric and piezoelectric features are the fundamental urges in optoelectronics, electronics, and energy harvesting. In this work, 2D ferroelectric Bi2O2Se flakes have been synthesized using a modified chemical vapor deposition technique. The 6 nm thick Bi2O2Se flake provides a robust ferroelectric switching under an applied voltage of ±10 V by piezoresponse force microscopy, further confirmed by first principles. Leveraging the successful growth, the high‐quality Bi2O2Se flakes permit the fabrication of a field‐effect transistor (FET) with state‐of‐the‐art performance. The FET device rewards a high current on–off ratio of 108 and field effect mobility of almost 131 cm2 V−1 s−1, owing to the small carrier effective mass of 0.2 m0. Combined, the electric field‐induced local polarization of ferroelectric switching and unprecedented device performance of Bi2O2Se semiconductors are certified for their utilization in advanced nanoelectronics and miniaturization of multifunctional devices with multifunctionalities.

Enhanced N-type Semiconducting Performance of Asymmetric Monochlorinated Isoindigo-based Semiregioregular Polymers under Dynamic Forces.

The asymmetric monochlorination strategy not only effectively addresses the steric issues in conventional dichlorination but also enables the development of promising acceptor units and semiregioregular polymers. Herein, monochlorinated isoindigo (1CIID) is successfully designed and synthesized by selectively introducing single chlorine (Cl) atoms. Furthermore, the 1CIID copolymerizes with two donor counterparts, centrosymmetric 2,2'-bithiophene (2T) and axisymmetric 4,7-di(thiophen-2-yl)benzo[1,2,5]thiadiazole (DTBT), forming two polymers, P1CIID-2T and P1CIID-DTBT. These polymers exhibit notable differences in backbone linearity and dipole moments, influenced by the symmetry of their donor counterparts. In particular, P1CIID-2T, which contains a centrosymmetric 2T unit, demonstrates a linear backbone and a significant dipole moment of 10.20 D. These properties contribute to the favorable film morphology of P1CIID-2T, characterized by highly ordered crystallinity in the presence of fifth-order (500) X-ray diffraction peaks. Notably, P1CIID-2T exhibits a significant improvement in molecular alignment under dynamic force, resulting in over 8-fold improvement in the performance of organic field-effect transistor (OFET) devices, with superior electron mobility up to 1.22 cm2 V-1 s-1. This study represents the first synthesis of asymmetric monochlorinated isoindigo-based conjugated polymers, highlighting the potential of asymmetric monochlorination for developing n-type semiconducting polymers. Moreover, our findings provide valuable insights into the relationship between the molecular structure and properties.

Temperature Dependence of Charge Transport Properties of Quasi-2D Chiral Perovskite Thin-Film Field-Effect Transistors.

Chiral halide perovskite materials promise both superior light response and the capability to distinguish circularly polarized emissions, which are especially common in the fluorescence spectra of organic chiral materials. Herein, thin-film field-effect transistors (FETs) based on chiral quasi-two-dimensional perovskites are explored, and the temperature dependence of the charge carrier transport mechanism over the broad temperature range (80-300 K) is revealed. A typical p-type charge transport behavior is observed for both left-handed (S-C6H5(CN2)2NH3)2(CH3NH3)n-1PbnI3n+1 and right-handed (R-C6H5(CN2)2NH3)2(CH3NH3)n-1PbnI3n+1 chiral perovskites, with maximum carrier mobilities of 1.7 × 10-5 cm2 V-1 s-1 and 2.5 × 10-5 cm2 V-1 s-1 at around 280 K, respectively. The shallow traps with smaller activation energy (0.03 eV) hinder the carrier transport over the lower temperature regime (80-180 K), while deep traps with 1 order of magnitude larger activation energy than the shallow traps moderate the charge carrier transport in the temperature range of 180-300 K. From the charge carrier mechanism point of view, impurity scattering is established as the dominant factor from 80 K until around 280 K, while phonon scattering becomes predominant up to room temperature. Responsivities of 0.15 A W-1 and 0.14 A W-1 for left-handed and right-handed chiral perovskite FET devices are obtained.

Ferroelectric 2D SnS2 Analog Synaptic FET.

In this study, the development and characterization of 2D ferroelectric field-effect transistor (2D FeFET) devices are presented, utilizing nanoscale ferroelectric HfZrO2 (HZO) and 2D semiconductors. The fabricated device demonstrated multi-level data storage capabilities. It successfully emulated essential biological characteristics, including excitatory/inhibitory postsynaptic currents (EPSC/IPSC), Pair-Pulse Facilitation (PPF), and Spike-Timing Dependent Plasticity (STDP). Extensive endurance tests ensured robust stability (107 switching cycles, 105 s (extrapolated to 10 years)), excellent linearity, and high Gmax /Gmin ratio (>105 ), all of which are essential for realizing multi-level data states (>7-bit operation). Beyond mimicking synaptic functionalities, the device achieved a pattern recognition accuracy of ≈94% on the Modified National Institute of Standards and Technology (MNIST) handwritten dataset when incorporated into a neural network, demonstrating its potential as an effective component in neuromorphic systems. The successful implementation of the 2D FeFET device paves the way for the development of high-efficiency, ultralow-power neuromorphic hardware which is in sub-femtojoule (48 aJ/spike) and fast response (1 µs), which is 104 folds faster than human synapse (≈10ms). The results of the research underline the potential of nanoscale ferroelectric and 2D materials in building the next generation of artificial intelligence technologies.

Ti3C2O2 MXene single-layer as a nanoscale transport device

We considered Ti3C2O2 MXene single-layers with stepped edges as a nanoscale field effect transistor (FET) device. Our model device contains stepped edges at the interface of Ti3C2O2 and Ti2CO2 segments, and a top gate. We suggest that Ti2CO2 semiconducting device region can be obtained by etching the central part of a Ti3C2O2 single-layer. We determined the device characteristic of the proposed device in non-equilibrium Green’s function (NEGF) calculations and observed the transistor behavior. The current through the device is controllable by the total amount of accumulated charge on the gate electrode. Our findings should be applicable to a large number of MXenes: Starting from M3C2O2 MXene single-layers, nanoscale FETs could be produced using conventional mask and etching lithography techniques.

Modeling of non-intrinsic noise in nanometer metal oxide semiconductor field effect transistors

With the proportional reduction of metal–oxide–semiconductor field effect transistor (MOSFET) devices, the short channel effect, the parasitic effect, and the field strength effect are significantly enhanced, the proportion of parasitic resistance increases, and the non-intrinsic noise also increases, which seriously affects the working efficiency of the device. However, existing research mainly focuses on the intrinsic noise of MOSFET, and there is little research on the non-intrinsic noise; furthermore, the models describing the relationship between non-intrinsic noise, device structure, and bias have not yet been addressed. Therefore, in this paper, 90, 65, 32, 10, and 5 nm MOSFETs are studied. The rate of the intrinsic ballistic parameter is introduced to set up the source–drain current model and the non-intrinsic noise model. The source–drain current model is consistent with the theoretical model, numerical simulation, and experimental results in the literature. Finally, the relationship between the non-intrinsic noise and the bias and the device parameters are analyzed, and the conclusion is helpful to improve the working efficiency, lifetime, and response speed of nanoscale MOSFET devices.