Field-effect Mobility Research Articles

Numerical Modelling of Carrier Transport in Organic Field Effect Transistors

Background: Organic field effect transistors (OFETs), used in the fabrication of nanosensors, are one of the most promising devices in organic electronics because of their lightweight, flexibility, and low fabrication cost. However, the optimization of such OFETs is still in an early stage due to the minimal analytical and numerical models presented in the literature. Objective: This research presses to demonstrate a numerical carrier transport model based on the finite element method (FEM) to investigate the I-V characteristic of OFETs. Methods: Two various organic semiconductor materials have been included in the study, polyaniline and pentacene, where micro-scale, as well as nano-scale models have been presented. OFETs regarding channel length, dielectric thickness, and doping level impact have been studied. We nominated the threshold voltage, the on/off current ratio, the sub-threshold swing, and the field effect mobilities as the primary output evaluating parameters. Results: The numerical model has shown the criticality of the doping effect on tuning the device flowing drain current to exceed 300 μA saturation current, along with a threshold voltage of -0.1 V under a channel length of 30 nm. Conclusion: The study highlights the effectiveness of polyaniline over pentacene as nano-channel length OFET due to the boosted conductivity of polyaniline concerning pentacene.

Comparative Study of Indium Oxide Films for High‐Mobility TFTs: ALD, PLD and Solution Process

AbstractDeposition of indium oxide base films for high‐mobility thin film transistors (TFTs) has been an important part in the implementation of high‐resolution and high‐frequency display back panels. In this study, three types of In2O3 (InO) films have been fabricated for TFTs using atomic layer deposition (ALD), pulsed laser deposition (PLD), and solution process, respectively. ALD‐derived InO films show controllable grain formation and optimized TFTs show the field effect mobility of ≈100 cm2 V−1s−1 in both the conventional transistor measurements and critical four‐probe measurements, reaching the level of low‐temperature polycrystalline silicon (LTPS). Combined spectroscopy investigations show that the ALD‐derived InO film features advantages as compared to those of the PLD‐deposited and solution‐processed InO film in providing a smoother surface morphology, good crystallinity, and more orderly atomic growth mode. Moreover, the bias‐stress stability of ALD‐derived TFTs can be improved with further passivation.

Impact of bias stress and endurance switching on electrical characteristics of polycrystalline ZnO-TFTs with Al2O3 gate dielectric

Abstract This study experimentally investigates electrical characteristics and degradation phenomena in polycrystalline zinc oxide thin-film transistors (ZnO-TFTs). ZnO-TFTs with Al2O3 gate dielectric, Al-doped ZnO (AZO) source–drain contacts, and AZO gate electrode are fabricated using remote plasma-enhanced atomic layer deposition at a maximum process temperature of 190 °C. We employ positive bias stress (PBS), negative bias stress (NBS), and endurance cycling measurements to evaluate the ZnO-TFT performance and examine carrier dynamics at the channel-dielectric interface and at grain boundaries in the polycrystalline channel. DC transfer measurements yield a threshold voltage of −5.95 V, a field-effect mobility of 53.5 cm2/(V∙s), a subthreshold swing of 136 mV dec−1, and an on-/off-current ratio above 109. PBS and NBS measurements, analysed using stretched-exponential fitting, reveal the dynamics of carrier trapping and de-trapping between the channel layer and the gate insulator. Carrier de-trapping time is 88 s under NBS at −15 V, compared to 1856 s trapping time under PBS at +15 V. Endurance tests across 109 cycles assess switching characteristics and temporal changes in ZnO-TFTs, focusing on threshold voltage and field-effect mobility. The threshold voltage shift observed during endurance cycling is similar to that of NBS due to the contrast in carrier trapping/de-trapping time. A measured mobility hysteresis of 19% between the forward and reverse measurement directions suggests grain boundary effects mediated by the applied gate bias. These findings underscore the electrical resilience of polycrystalline ZnO-TFTs and the aptitude for 3D heterogeneous integration applications.

Effect of Deposition Temperature on Zn Interstitials and Oxygen Vacancies in RF-Sputtered ZnO Thin Films and Thin Film-Transistors

ZnO thin films were deposited using RF sputtering by varying the argon:oxygen gas flow rates and substrate temperatures. Structural, optical and electrical characterization of ZnO thin films were systematically carried out using X-Ray diffraction (XRD), scanning electron microscopy (SEM), UV–visible spectroscopy, X-Ray photoelectron spectroscopy (XPS) and Hall measurements. Film deposited at room temperature and annealed at 300 °C exhibited low O2 incorporation with localized defects and a high percentage of Zn interstitials. A large crystalline size and fewer grain boundaries resulted in a high Hall mobility of 46.09 cm2/V-s Deposition at higher substrate temperatures resulted in improvement in O2 incorporation through the annihilation of localized defects and decrease in oxygen vacancies and Zn interstitials. Urbach tails within the bandgap were identified using the absorption spectrum and compared with the % defects from XPS. Bottom-gate thin-film transistors were subsequently fabricated on a SiO2/p-Si substrate using the combination of RF sputtering, wet etching and photolithography. Variation in the substrate temperature showed performance enhancement in terms of the leakage current, threshold voltage, sub-threshold swing and ION/IOFF ratio. Thin-film transistor (TFT) devices deposited at 300 °C resulted in an O2-rich surface through chemisorption, which led to a reduction in the leakage current of up to 10−12 A and a 10-fold reduction in the sub-threshold swing (SS) from 30 V to 2.8 V. Further TFT optimization was carried out by reducing the ZnO thickness to 50 nm, which resulted in a field-effect mobility of 1.1 cm2/V-s and ION/IOFF ratio of 105.

Novel electrical characteristic measurement system of semiconductor films for estimating device characteristics

We proposed a novel measurement method and system to measure the electrical characteristics of non-patterned semiconductor films to estimate the final device’s properties. The proposed method is based on measuring bottom-gate structure thin-film transistor (TFT) using the probe pins as source and drain electrodes. We carefully designed the array structure and material of the probe pin to effectively detect extremely low-level currents without patterned electrodes on the semiconductor film. The contact pressure was also carefully controlled through continuous monitoring using an implemented pressure sensor to ensure the reliability and reproducibility of the measured data. In addition, we developed a method of extracting device parameters, such as the threshold voltage and field-effect mobility, from the measured data, considering the geometric factor of the proposed method. Comparative analysis between the measurement results of the film sample using the proposed system and that of the final TFT sample exhibited similar results with slight deviations. Furthermore, the proposed system provided similar results under repetitive measurements. Consequently, the proposed method and system successfully demonstrated the estimation of the final TFT’s properties by measuring the electrical characteristics of the non-patterned semiconductor film with excellent reliability, highlighting the possibility of effectively reducing costs for development and fabrication.

Understanding thickness-dependent stability of tungsten-doped indium oxide transistors

In this study, the influence of the thickness of the channel layer on the electrical properties and stability of tungsten-doped indium oxide (IWO) thin-film transistors (TFTs) was investigated. Although oxide-semiconductor TFTs, particularly indium gallium zinc oxide, are promising, problems related to oxygen vacancies have led to their instability. In contrast, IWO has proven to be a compelling alternative because of its robust resistance to oxygen vacancies. IWO TFTs with varying channel thicknesses (10, 20, and 30 nm) were fabricated, and the device parameters, such as threshold voltage (Vth), subthreshold swing (SS), field-effect mobility (μFE), and on/off current ratio (Ion/Ioff), were analyzed. It was found that as the channel thickness increased, Vth exhibited a negative shift and SS increased, indicating an increase in carrier concentration. This phenomenon is attributed to the bulk trap density, in particular to oxygen vacancies. Negative bias stress tests confirmed the influence of the oxygen vacancies, with thicker channels showing more pronounced shifts. Low-frequency noise measurements were consistent with the carrier number fluctuation model, indicating that defects within the channel region contribute to the observed noise. The study concludes that identifying an optimal channel thickness during device manufacturing is crucial for improved TFT performance, with 20 nm devices characterized by high μFE and comparable trap density to 10 nm. This study provides valuable insight into the nuanced relationship between the channel thickness, trap density, and electrical performance of IWO TFTs.

The Extraction of the Density of States of Atomic-Layer-Deposited ZnO Transistors by Analyzing Gate-Dependent Field-Effect Mobility

In this study, we investigated the density of states extraction method for atomic-deposited ZnO thin-film transistors (TFTs) by analyzing gate-dependent field-effect mobility. The atomic layer deposition (ALD) method offers ultra-thin and smooth ZnO films, but these films suffer from interface and semiconductor defects, which lead to disordered localized electronic structures. Hence, to investigate the unstable localized structure of ZnO TFTs, we tried to derive the electronic state relationship by assuming field-effect mobility can be expressed as a gate-dependent Arrhenius relation, and the activation energy in the relation is the required energy for hopping. Following this derived relationship, the DOS of the atomic-deposited ZnO transistor was extracted and found to be consistent with those using temperature-dependent measurements. Moreover, to ensure the proposed method is reliable, we applied methods for the extraction of DOSs of doped ZnO transistors, which show enhanced mobilities with shifted threshold voltages, and the results show that the extraction method is reliable. Thus, we can state that the mobility-based DOS extraction method offers practical benefits for estimating the density of states of disordered transistors using a single transfer characteristic of these devices.

Electrical and UV-sensing performance of N-doped-Ba(Ti,Zr,Mo,Hf,Ta)O3-dielectric and ZnSnO-channel-based flexible thin-film transistors

Flexible thin-film transistors (TFTs) based on N-doped Ba(Ti,Zr,Mo,Hf,Ta)O3 dielectric and ZnSnO channel show high electrical and UV-sensing performance. The optimal N-doped Ba(Ti,Zr,Mo,Hf,Ta)O3 compositions with low equivalent oxide thicknesses (≈2 nm) and high-entropy (configurational entropy ≈ 1.59 R) are efficiently determined from a wide composition space (library). The film library is patterned to 450 metal–insulator-metal stacks, revealing dielectric constants ≈ 262–322 and loss (tan δ) ≈ 0.01–0.30 for the N-doped Ba(Ti,Zr,Mo,Hf,Ta)O3 at 1 kHz. The library is further integrated to 63 TFTs, and the promising ones exhibit the remarkable parameters: current on/off ratio of 108, threshold voltage (VT) of 0.02 V, saturation field-effect mobility of ≈76 cm2⋅V−1⋅s−1, and subthreshold swing of 0.062 V dec−1. The devices also exhibit desirable long-term stability for up to five months and perform reliably with small or negligible changes in VT and drain-source current under various gate-bias stress and temperature conditions. Furthermore, the TFT-based ultraviolet (253 nm) detector demonstrates impressive sensitivity (≈ 2 × 106) and responsibility (≈ 1171.9 A W−1). There is no substantial degradation in electrical or sensing characteristics under various levels of deformation. Charge transport in constructed energy band diagrams is used to elucidate the observed remarkable performance.

Molecular Reconfiguration of Disordered Tellurium Oxide Transistors with Biomimetic Spectral Selectivity.

Reconfigurable devices with field-effect transistor features and neuromorphic behaviors are promising for enhancing data processing capability and reducing power consumption in next-generation semiconductor platforms. However, commonly used 2D materials for reconfigurable devices require additional modulation terminals and suffer from complex and stringent operating rules to obtain specific functionalities. Here, a p-type disordered tellurium oxide is introduced that realizes dual-mode reconfigurability as a logic transistor and a neuromorphic device. Due to the disordered film surface, the enhanced adsorption of oxygen molecules and laser-induced desorption concurrently regulate the carrier concentration in the channel. The device exhibits high-performance p-type characteristics with a field-effect hole mobility of 10.02 cm2 V-1 s-1 and an Ion/Ioff ratio exceeding 106 in the transistor mode. As a neuromorphic device, the vision system exhibits biomimetic bee vision, explicitly responding to the blue-to-ultraviolet light. Finally, in-sensor denoising and invisible image recognition in static and dynamic scenarios are achieved.

Thermal atomic layer deposition-processed InHfZnO thin film transistors with excellent stability

In recent years, the downscaling of transistors has sparked considerable interest in the advancement of amorphous oxide semiconductors, particularly indium-hafnium-zinc oxide (IHZO) has remarkable potential in applications such as high-resolution displays and 3D NAND. For the first time, we propose the fabrication of IHZO thin film transistors (TFTs) via thermal atomic layer deposition (TH-ALD). The preparation, electrical properties, and stability of IHZO TFTs are investigated. The performance of TFT deposited at 250 °C and annealed in N2 atmosphere at 300 °C exhibits a high field-effect mobility (μ) of 22.53 cm2/Vs, a high Ion/Ioff of ∼107, a low threshold voltage (Vth) of 0.15 V, and a minimum subthreshold swing (SS) of 0.24 V/decade. Furthermore, the threshold voltage shifts (ΔVth) in TFTs annealed in N2 and O2 are 0.31 and 0.16 V, respectively. These enhancements are attributed to the defects suppression and remaining ionized oxygen vacancies result in increased electron concentration in N2-annealed films. In comparison, O2 annealing causes a reduction in field effect mobility but concurrently enhances stability due to the direct passivation of defects, which leads to fewer oxygen vacancies. Additionally, Hf content can also impact the performance of TFT devices, even a small addition of Hf also results in the effective reduction of the carrier concentration. These findings provide valuable insights into the device mechanism of IHZO TFTs, presenting a novel avenue for comprehending and augmenting their overall performance.

Solution-processable ordered defect compound semiconductors for high-performance electronics.

Solution-processable semiconductors hold promise in enabling applications requiring cost-effective electronics at scale but suffer from low performance limited by defects. We show that ordered defect compound semiconductor CuIn5Se8, which forms regular defect complexes with defect-pair compensation, can simultaneously achieve high performance and solution processability. CuIn5Se8 transistors exhibit defect-tolerant, band-like transport supplying an output current above 35 microamperes per micrometer, with a large on/off ratio greater than 106, a small subthreshold swing of 189 ± 21 millivolts per decade, and a high field-effect mobility of 58 ± 10 square centimeters per volt per second, with excellent uniformity and stability, superior to devices built on its less defective parent compound CuInSe2, analogous binary compound In2Se3, and other solution-deposited semiconductors. They can be monolithically integrated with carbon nanotube transistors to form high-speed and low-voltage three-dimensional complementary logic circuits and with micro-light-emitting diodes to realize high-resolution displays.

Sputter-Deposited copper iodide thin film transistors with low Operating voltage

This paper reports on a back-gated p-type thin film transistor (TFT) with copper iodide (CuI) as the channel material, a HfO2 gate dielectric layer, and Al2O3 passivation. The γ-CuI channel was deposited from a CuI target using DC magnetron sputtering at room temperature. Our TFT can be fully shut off by VG = 4 V, with a field-effect channel hole mobility μh ∼ 1.5–2 cm2 V−1 s−1. An anneal in forming gas was performed twice, once at 200 °C, then at 250 °C to improve gate control, yielding a final Ion/Ioff current ratio of ∼ 250. The anneal served two purposes: to reduce the oxygen acceptor density in the CuI channel and reduce the concentration of interface states between the CuI, Al2O3 passivation, and HfO2. A model of the device was built in an industrial TCAD simulator, which reproduces the measured characteristics and allows an estimation of interface state densities and channel doping.

Compositional changes between metastable SnO and stable SnO2 in a sputtered film for p-type thin-film transistors

p-Type tin(II) oxide (SnO (Sn2+)) formation using radiofrequency (RF) reactive magnetron sputtering and post-deposition annealing (PDA) processes was investigated. The as-grown SnOx film deposited from an SnOx (SnO:Sn = 60:40) target by RF sputtering at an oxygen partial pressure (PO2) of 0 Pa consisted of 2 % Sn (Sn0), 42 % Sn2+, and 56 % SnO2 (Sn4+). However, compared with the Sn2+ fraction observed after PDA under N2 and low-vacuum (∼1 Pa) conditions, that after PDA at 300 °C under high vacuum (< 5 × 10−4 Pa) (HVPDA) increased substantially to greater than 62 %. This result was attributed to the transformation from SnO2 to SnO during HVPDA. A staggered bottom-gate thin-film transistor with an SnO channel (10 nm), which was fabricated by HVPDA at 300 °C, exhibited p-type properties, including a relatively high on-current/off-current (Ion/Ioff) ratio of 5.1 × 104 and a hole field-effect mobility (µFE) of 1.8 cm2/(V·s).

Molecular-Scale Geometric Design: Zigzag-Structured Intrinsically Stretchable Polymer Semiconductors.

Orienting intelligence and multifunction, stretchable semiconductors are of great significance in constructing next-generation human-friendly wearable electronic devices. Nevertheless, rendering semiconducting polymers mechanical stretchability without compromising intrinsic electrical performance remains a major challenge. Combining geometry-innovated inorganic systems and structure-tailored organic semiconductors, a molecular-scale geometric design strategy is proposed to obtain high-performance intrinsically stretchable polymer semiconductors. Originating from the linear regioregular conjugated polymer and corresponding para-modified near-linear counterpart, a series of zigzag-structured semiconducting polymers are developed with diverse ortho-type and meta-type kinking units quantitatively incorporated. They showcase huge edges in realizing stretchability enhancement for conformational transition, likewise with long-range π-aggregation and short-range torsion disorder taking effect. Assisted by additional heteroatom embedment and flexible alkyl-chain attachment, mechanical stretchability and carrier mobility could afford a two-way promotion. Among zigzag-structured species, o-OC8-5% with the initial field-effect mobility up to 1.92 cm2 V-1 s-1 still delivers 1.43 and 1.37 cm2 V-1 s-1 under 100% strain with charge transport parallel and perpendicular to the stretching direction, respectively, accompanied by outstanding performance retention and cyclic stability. This molecular design strategy contributes to an in-depth exploration of prospective intrinsically stretchable semiconductors for cutting-edge electronic devices.

Crystal Engineering Under Residual Solvent Evaporation: A Journey Into Crystallization Chronicles of Soluble Acenes.

In the pursuit of achieving high-performance and high-throughput organic transistors, this study highlights two critical aspects: designing new soluble acenes and optimizing their solution processing. A fundamental understanding of the crystallization mechanism inherent to these customized soluble acenes, as they undergo a transformation during the evaporation of residual solvent, is deemed essential. Here, the pathway to crafting ideal solution processing conditions is elucidated, meticulously tailored to the molecular structure of soluble acenes when blended with polymers. Employing a comprehensive array of analytical and computational methodologies, this investigation delves directly into the intricate interplay between processing parameters and crystallization mechanisms, firmly rooted in the domains of thermodynamics and kinetics. Notably, a delicate equilibrium where the optimal weight of residual solvent harmoniously aligns is uncovered with the specific attributes of soluble acene molecules, exerting influence over vertical phase separation with the blended polymer and the crystallization process of soluble acenes at the surface. Consequently, transistors showcasing remarkable field-effect mobility exceeding 8 cm2V-1s-1 are successfully developed. These findings provide invaluable guidance for navigating the path toward determining optimal solution processing conditions across a diverse array of soluble acene/polymer blend systems, all achieved through the strategic application of crystal and residual solvent engineering.

Improved Electrical Performance of CVD Monolayer-MoS2 TFT Via Wet Transfer of Van Der Waals Source/Drain Electrodes

In this study, we introduce a novel wet transfer method utilizing PMMA as a supporting tool for electrode transfer, with HF employed to facilitate the separation of the electrode from a sacrificial layer. This method is applied to fabricate source/drain electrodes for MoS2 FETs. The implementation of the transferred Ag source/drain electrodes significantly enhances the carrier mobility of the CVD monolayer-MoS2 FET by forming a Van der Waals contact between the monolayer MoS2 and the Ag electrode, which ensures minimal contact resistance between them. As a result, compared with its counterpart with Ag source/drain electrodes prepared by thermal evaporation, the field-effect mobility of the proposed MoS2 FET is increased from 25.3 cm²V⁻¹s⁻¹ to 69.1 cm²V⁻¹s⁻¹, while the contact resistance is reduced from 13.7 kΩ·μm to 1.49 kΩ·μm.

Enhancement of organic field-effect transistor performance via precision molecular alignment of a P4T2F-HD-based conjugated polymer

This study conducts a detailed exploration of how the orientation of molecules affects the efficiency of organic field-effect transistors (OFETs), with a particular focus on a new conjugated polymer, P4T2F-HD. The study examines the fabrication of both large-scale, anisotropically oriented thin films and non-oriented, isotropic thin films of P4T2F-HD through two separate approaches: the Unidirectional Film Transfer Method (UFTM) for oriented films and spin-coating for isotropic films. Results indicate that UFTM notably excels in directing the molecular alignment of P4T2F-HD across extensive areas, thereby creating anisotropic thin films, whereas spin-coating yields isotropic thin films lacking specific orientation. Further investigation into the properties of these films through various analytical techniques sheds light on the role of molecular orientation in influencing their electronic characteristics. OFETs fabricated with anisotropically oriented P4T2F-HD films exhibit markedly improved performance, characterized by higher charge carrier mobility and enhanced electrical stability, in comparison to their isotropic counterparts. The study evidences that the directional arrangement of macromolecules plays a pivotal role in OFETs functionality, with UFTM-derived films demonstrating a significant leap in field-effect mobility—showing an over 100-fold improvement over spin-coated films. This boost is linked to the effective charge transmission along the polymer chains, enabled by precise molecular alignment.

Tri‐Layer Heterostructure Channel of a‐IGZO/a‐ITZO/a‐IGZO Toward Enhancement of Transport and Reliability in Amorphous Oxide Semiconductor Thin Film Transistors

AbstractThin film transistors (TFTs) based on amorphous oxide semiconductors (AOS) are promising candidates for panel displays. However, the trade‐off between mobility and reliability in AOS‐TFTs hinders their further applications in next‐generation display techniques and newly developed logic and memory circuits. Here, a structural strategy is proposed for the mobility‐reliability trade‐off, via a triple‐layer channel containing a Ga‐free high‐mobility layer (amorphous InSnZnO, a‐ITZO) sandwiched by two Ga‐rich layers (amorphous InGaZnO, a‐IGZO) with higher reliability. Gate‐induced carrier accumulation is verified mainly being energetically confined within the high mobility a‐ITZO layer, at the newly defined a‐ITZO/a‐IGZO interface. Compared to single layer a‐ITZO‐TFTs, triple‐channel a‐IGZO/a‐ITZO/a‐IGZO TFTs (GTG‐TFTs) exhibit outstanding stability and electrical transport performances, with suppressed positive/negative‐bias‐stress voltage shifts from 1/0.3 to 0.1/0.004 V, enhanced field effect mobility from ≈40 to 56 cm2V−1s−1, and optimized sub‐threshold swing down to 80 mV dec−1. Further numerical simulations and charge transport characterizations, including magnetotransport and gate‐induced Hall effect, indicate that charge transport in tri‐layer structure is less affected by energetic disorders present at gate insulator interfaces.

Heterogeneous monolithic 3D integration for hybrid vertical CMOS inverter using n-type IGTO TFT on p-type Si FET

In this work, a complementary metal oxide semiconductor (CMOS) vertical inverter using heterogeneous monolithic 3D (M3D) integration with p-type Si field-effect transistor (FET) and n-type indium-gallium-tin-oxide (IGTO) thin film transistor (TFT) was implemented and characterized. This CMOS inverter was attained by vertical stacking n-type IGTO TFT on p-type Si FET. Oxide semiconductor materials such as indium-gallium-zinc-oxide (IGZO), indium-tungsten-oxide (IWO), indium oxide (In2O3) and IGTO are being considered as potential options for channel materials in M3D integration technology due to high electrical characteristics and low temperature process. Among them, IGTO was employed as a channel material to achieve high mobility. We fabricated a n-type IGTO TFT using HfO2 and tungsten as a gate dielectric and electrode, respectively. The post-annealing process was conducted at 200–500 °C with 50 °C intervals. The IGTO TFT exhibits a high field-effect mobility (32.9 cm2/Vs), low sub-threshold swing (0.070 V/dec) and stable reliability behaviour (ΔVth < 0.4 V) against various external gate bias temperature stress tests in a low temperature (<500 °C). The stable heterogeneous vertical inverter performance such as voltage-transfer curve (VM = 1.66 V), voltage gain (30.1 V at VDD = 3 V), and noise margin (NMH = 1.22 V, NML = 1.34 V) were well behaved. This M3D integration-based hybrid CMOS inverter can be an alternative knob toward various device applications.

Precisely Tailoring WSe2 Polarity via van der Waals Bismuth-Gold Modulated Contact.

Creating high-quality contacts between high-melting-point metals and delicate two-dimensional (2D) semiconductors poses a critical challenge to polarity control due to inevitable chemical disorder and Fermi-level pinning observed in the contact regions. Here, we report a van der Waals (vdW) integration strategy to precisely tailor the WSe2 polarity by meticulously modulating metal contact compositions. Controlling the low-melting-point bismuth (Bi) thickness effectively modulates the Bi/Au dominant contact with WSe2. This facilitates the precise polarity transformation between n-type, ambipolar, and p-type, with exceptional field-effect mobilities of 200 cm2 V-1 s-1 for electrons and 136 cm2 V-1 s-1 for holes. Within this vdW geometry, we further demonstrate the fundamental electrical components such as diodes and complementary inverters with enhanced rectification ratios and voltage gains. Our results showcase an effective and compatible with mass manufacturing method for precise polarity modulation of 2D semiconductors, providing a promising pathway toward large-scale high-performance 2D electronics and integrated circuits.