Fibonacci Charge Pump Research Articles

General Analysis of Fibonacci Charge Pump SSL Output Characteristics With Parasitic Capacitances

A closed-form analytic formula for the output characteristics of a Fibonacci charge pump model in the slow-switching limit generalized to any number of switching capacitor stages is derived for the first time. The model incorporates bottom-plate and closed-switch parasitic capacitances. Thus, the derived formula gives insight into the effects of parasitics on the output characteristics and their deviation from the ideal, including the limit of the output resistance and gain as the number of stages grows to infinity. The limits of this generalized formula reduce to previously published results of special cases, and simulations confirm the results. The calculation complexity of the output characteristics using the model is completely independent of the size of the converter, whereas the computational complexity of previous works grows linearly with converter size.

High-Current Drivability Fibonacci Charge Pump With Connect–Point–Shift Enhancement

A switched-capacitor dc-dc voltage regulator that converts an input of 2.4-3.6 V to an output of 30 V has been designed to power display driver integrated circuits. A novel Fibonacci structure, named connect-point-shift, is proposed to improve the current drivability, which increases the minimum current drivability from 0.16 to 0.274 mA. This scheme saves the chip size by approximately 40% while providing equal current drivability as the traditional one. The power efficiency has been improved by 1%-7%, and a peak efficiency of 83.4% has been achieved. The adaptive-conversion-ratio has been adopted for ripple and efficiency improvement. A pulse skip regulator and a linear regulator are utilized to keep the output terminal of the charge pump stable at around 30 V. Their ripple, efficiency, load regulation, and line regulation are compared for further optimization. Theories of Degenerate State and state-space averaging are applied to validate the performance enhancement. This scheme has been fabricated and validated by a 0.11-μm 1.5 V/6 V/30 V process.

New Discrete Fibonacci Charge Pump Design, Evaluation and Measurement

Abstract This paper focuses on the practical aspects of the realisation of Dickson and Fibonacci charge pumps. Standard Dickson charge pump circuit solution and new Fibonacci charge pump implementation are compared. Both charge pumps were designed and then evaluated by LTspice XVII simulations and realised in a discrete form on printed circuit board (PCB). Finally, the key parameters as the output voltage, efficiency, rise time, variable power supply and clock frequency effects were measured.

P‐52: A Fibonacci‐Like Charge Pump and its Current Drive Capacity Enhancement for Display Driver ICs

In this work, a mixed‐Fibonacci charge pump scheme with gate drive enhancement is proposed to provide as high as 30 V output voltage for display driver integrated circuits (ICs). By generating a high supply voltage (<6.6 V) with a first voltage doubler charge pump, the subsequent Fibonacci charge pump engages more middle‐voltage (MV) power transistors and more MV control signals. This improves the current drive capacity by approximately 50%‐120%, and the power efficiency is optimized by approximately 10%. Alternatively, it saves about 50% of chip size compared with the traditional scheme. Based on a 0.11 μm 1.5 V/6 V/32 V process, the design is fabricated and the performance improvement is validated. The novel one can achieve a peak current drive capacity of 1.74 mA and its peak power efficiency is 74%.

A High Conversion Ratio Component-Efficient Charge Pump for Display Drivers

In this paper, a scheme combining the advantages of both Dickson charge pump and Fibonacci charge pump has been proposed to output 30 V voltage for display driver integrated circuit applications. With only two external capacitors, it fits for small-sized package like smart card applications. The flying capacitors of Dickson charge pump were optimized and 2.3% of the chip size was saved. Meanwhile a highly precise and simple model for one-stage Fibonacci charge pump was utilized. By using RC charging theory, its voltage error can be limited within 0.02% and it is feasible for further efficiency optimization. Based on a 0.11 μm 1.5 V/6 V/32 V process, three different types of layouts for the built-in capacitors were fabricated to further optimize the chip size and their performance was compared. They enhance the flying capacitance by 6%, 26%, and 64%, respectively, compared with the traditional design. This design improves the maximum current drivability and the power efficiency is higher than 53%.

Dickson Charge Pump with Gate Drive Enhancement and Area Saving

This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system's current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.

Dynamic Analysis of Two-Phase Switched-Capacitor DC–DC Converters

A method that aims at analyzing the dynamic behavior of some two-phase switched-capacitor charge pump circuits is proposed. A recurrence relation on the voltages across the charging capacitors of a given two-phase charge pump circuit is developed. The output voltage and the accumulated charge of a charge pump circuit after any clock cycle were found by solving some basic matrix equations, with a specific loading current and some required initial conditions. The validation of the proposed method was done by SPICE simulations based on a 8 × linear, Fibonacci, and an exponential charge pump. The analysis results were also verified with the simulation results obtained from some charge pump circuits designed with the 0.18 μm CMOS process. Results show that the proposed method can yield a close estimation on the dynamic behavior of a charge pump circuit in most of the designs. We further found that the rising times for the exponential and Fibonacci charge pumps are shorter, especially when the conversion ratio is high, than that of the linear one.