FET Threshold Voltage Research Articles

Effect of Dislocations on GaAs FET Threshold Voltage

Effect of Dislocations on GaAs FET Threshold Voltage

Extraordinary Points in the GaAs FET Threshold Voltage Distribution

Extraordinary Points in the GaAs FET Threshold Voltage Distribution

What Affects Most GaAs FET Threshold Voltage

What Affects Most GaAs FET Threshold Voltage

Influence of Structural and Electrical Characteristics of Extended Defects on GaAs Field Effect Transistors

ABSTRACTThe paper presents a systematic study of grown-in and process-induced defects on LEC GaAs substrates. Defects have been revealed by photoetching the wafers with diluted Sirti-like solutions after various processing steps. MESFET arrays have been processed on the wafers and a systematic mapping of the I-V characteristics has been performed. A correlation between various defect configurations and the FET threshold voltage shifts has been established.

Proximity effect of dislocations on GaAs MESFET threshold voltage

Spatial inhomogeneity of semi-insulating LEC-grown GaAs is currently a subject of considerable attention, and there have been contradictory reports that dislocations affect FET threshold voltage either directly or indirectly. Careful measurements of the threshold voltage are carried out in the vicinity of cellular dislocation networks, lineages, and the densely dislocated wafer periphery, which are dislocation distributions peculiar to LEC-grown GaAs crystals. The measurements were made in an attempt to verify the proximity effect of dislocations on the threshold voltage. It is concluded that, even though there is still ambiguity at very close gate-to-pit distances, the proximity effect is apparently observed only when the gate-to-pit distance is less than about 50µm. A threshold voltage difference between dislocation-free and dislocated areas is also demonstrated.

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Liquid-encapsulated Czochralski (LEC) grown, undoped GaAs exhibits high resistive, semiinsulating property and is very suitable for high performance GaAs IC's substrate with a direct ionimplantation technology. An FET threshold voltage, however, is strongly influenced by material properties. A close relationship between dislocations, native antisite defects AsGa and FET threshold voltage is briefly discussed, and it is demonstrated that dislocation-free GaAs exhibits a very uniform electrical properties desirable for GaAs ICs substrate.

Improvement of Vthcontrol for GaAs FET's by shallow-channel ion implantation

Fluctation of a net electrical activity of implanted impurities is thought to be the main origin of fluctuation of the threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> ) of GaAs FET's which have a channel layer formed by ion implantation directly into semi-insulating substrates. Net electrical activity is affected by several factors such as implantation damage and the nature of the substrate. Calculation of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> predicts that a shallow channel is advantageous to reduce the fluctuation of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> when the fluctuation of the net activity of implantated impurities predominates in that of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> . The advantage of the shallow channel was verified experimentally by a through-film implantation technique, which was one of the ways to realize the shallow-channel FET.

Factors Contributing to Cmos Static Ram Upset

Phenomena contributing to transient radiation induced static RAM (SRAM) cell upset in CMOS integrated circuits (ICs) include rail span collapse, dynamic FET threshold voltage shifts, photocurrents internal to the RAM cell, secondary photocurrents, and lateral variations in silicon surface potential. Of these phenomena, it is found that the major contributors are rail span collapse and internal cell photocurrents. A model is presented which combines global rail span collapse calculations with detailed analyses of local effects in the ram cell.

Model for the temperature dependence of the threshold voltage of modulation-doped field-effect transistors

A model for the temperature dependence Of the threshold voltage of modulation-doped FET's caused by traps in doped AlGaAs is presented. The model takes into account the charge distribution in the depletion region determined by the temperature and time-dependent occupation of traps. The theory shows excellent agreement with experiment in the temperature range 77 to 400 K.

Summary Abstract: Electron traps in MBE AlxGa1−xAs and the temperature dependence of the threshold voltage of modulation-doped FET’s

Summary Abstract: Electron traps in MBE AlxGa1−xAs and the temperature dependence of the threshold voltage of modulation-doped FET’s

Non-destructive characterization of electrical uniformity in semi-insulating GaAs substrates by microwave photoconductance technique

A novel non-destructive way of characterizing electrical uniformity of semi-insulating GaAs substrates is presented, and applied to Cr-doped HB and undoped LEC wafers. The method utilizes photoconductance at microwave frequencies. Photoconduction is shown to be n-type in both type of substrates, and its magnitude is related to effective lifetime of photo-generated electrons on the basis of a simple theory developed here. Photoconductance variation in Cr-doped substrates is less pronounced, and is related to Cr acceptor concentration. On the other hand, photoconductance variation is more pronounced in undoped LEC substrates with U,M or W-shaped distribution. The photoconductance variation in LEC substrates reflects concentration fluctuation of residual acceptor such as carbon. The photoconductance technique collects information concerning the acceptor distribution near the surface which has a direct effect on the threshold voltage of FETs.

A 1 GHz 50 mW GaAs dual modulus divider IC

A 1-GHz 50-mW GaAs dual modulus divider IC has been realized by using source-coupled FET logic. Dividing values are 128/129 and 64/65. The chip size is 0.94/spl times/1.07 mm, in which 223 FETs, 101 diodes, and 80 resistors are integrated. The platinum buried gate planar FET process is used in the IC fabrication. The maximum toggle frequency is 1.12 GHz and IC current is 9.55 mA at 5 V supply voltage. About 10-30% chip yield was achieved in the wide (0.1-0.4 V) enhancement FET threshold voltage range.

A GaAs 4 kbit SRAM with direct coupled FET logic

A GaAs 4-kb static RAM with enhancement/depletion direct coupled FET logic was designed and successfully fabricated by self-aligned implantation for n/SUP +/-layer technology (SAINT). The aim of the RAM circuit was to attain an access time of 2 ns with a power dissipation of less than 1 W. Statistical circuit simulation clarified the allowable scattering tolerance for FET threshold voltage of 45 mW. In-process monitoring was made wafer-to-wafer and chip-to-chip. A minimum address access time of 2.8 ns was measured with a power consumption of 1.2 W. Write and read operations were completely confirmed with a minimum write pulse width of 2 ns.

Dislocations as the origin of threshold voltage scatterings for GaAs MESFET on LEC-grown semi-insulating GaAs substrate

This paper describes the extended results on the influence of dislocations in liquid-encapsulated Czochralski (LEC) grown semi-insulating GaAs substrates on threshold voltage of GaAs MESFET's. MESFET's located less than about 50 µm from a dislocation exhibit threshold voltage lower than those far from a dislocation and threshold voltage scatters at less than about 30 µm from a dislocation. The scattering is considered briefly from anisotropy of stress field around dislocations. Particular interest is devoted to the electrical properties around dislocations because of their detrimental influence on the FET threshold voltage.

Uniformity evaluation of MESFET's for GaAs LSI fabrication

Studies were made on GaAs MESFET I-V characteristic scattering using self-aligned FET's on semi-insulating substrates. Surface treatment before gate-metal evaporation was found to have a satisfactory affect on FET drain current. The two main factors of threshold-voltage scattering in self-aligned FET's were clarified. One is the lack of uniformity in gate lengths, and the other is substrate nonuniformity. An analytical method was proposed to distinguish between threshold-voltage dispersions attributed to the factors without direct measurement of the gate lengths. Threshold-voltage scattering due to crystal inhomogeneity was estimated for both LEC and HB substrates, and for both the entire area of a 2-in wafer and an area as small as 400 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It was confirmed that the dislocations making up the firm network structure in LEC crystal affect the threshold voltage of self-aligned FET's and give rise to large dispersion even in the small area. High uniformity was recognized in the small area on HB substrates.

Characterization of thin active layer on semi-insulating GaAs by mapping of FET array performance

A computer-aided FET performance measurement system was established to characterize a thin active layer formed on a semi-insulating GaAs substrate. By mapping FET array performances on a thin active layer, this system was applicable to substrate material quality evaluation and to a check of FET fabrication processes. It also gave the key information on FET threshold voltage scattering to the GaAs IC circuit designer. Most importantly, it was powerful in the characterization of thin active layers for which conventional methods, such as resistivity, Hall, or C-V measurements, were not effective because of the surface depletion layer into the thin active layer. It is demonstrated that dislocations in substrate crystal were clearly revealed to affect FET threshold scattering on the active layer formed by direct ion implantation on an LEC-grown semi-insulating substrate.

Analysis of High-Speed GaAs Source-Coupled FET Logic Circuits

A source-coupled FET logic (SCFL) circuit is proposed for gigabit rate digital signaf processing. FET threshold voltage tolerance in the SCFL circuit and the SCFL circnit performance are presented. The speed of the SCFL gate depends on the operating region of the FET. For high-speed operation, FET's drain-to-source voltage fdgher than a pinchoff voltage has to be suppfied. The SCFL gate, which is composed of 1.5-pm gate-length FET's, showsthat the minimum propagation time is predicted to be 25 ps/gate. Mhimum rise time and fall time are expected to be S4 ps and 51 ps, respectively. Maximum RZ data rate is expected to be 5.6 Gb/s. The SCFL circnit is applicablefor high-speed dlgitaf sigmd processing.

Modulation-doped FET threshold voltage uniformity of a high throughput 3 inch MBE system

We report results of the characterization of a high throughput 3 in. MBE system which we have used to fabricate high quality, uniform modulation‐doped field‐effect transistors (MODFET’s). MODFET threshold voltage of 14.6% and hence Nd2 product uniformity of 11.3% standard deviation across a 3 in. MBE wafer was achieved. MODFET’s with 77 K mobility over 100 000 cm2/V s were fabricated. Silicon was used as the n‐type dopant of the (Al,Ga)As/GaAs heterostructures. Successful calibration of the Si cell temperature resulted in controlled doping in the range 1014 cm−3 to mid‐1018 cm−3 in GaAs. AlxGa1−xAs (x≂0.3) was also doped successfully up to 2.5 ×1018 cm−3. Doping and thickness uniformity of 2% for both (Al, Ga)As and GaAs over the central 2.5 in. of 3 in. substrates was achieved using substrate rotation.

Direct observation of dislocation effects on threshold voltage of a GaAs field-effect transistor

The threshold voltage of a GaAs metal-semiconductor field-effect transistor (MESFET) fabricated on a liquid encapsulated Czochralski grown, semi-insulating substrate was found to be influenced by growth-induced dislocations. Field-effect transistors located at less than 20–30 μm from a dislocation exhibited a threshold voltage lower than that of FET’s located far from a dislocation. The maximum difference in threshold voltage of FET’s located at less than and more than this critical distance was obtained to be about 300 mV. The first definitive correlation between dislocations and FET threshold voltage is reported.

Orientation effect reduction through capless annealing of self-aligned planar GaAs Schottky barrier field-effect transistors

A reduction in the orientation effect on self-aligned ion-implanted planar GaAs Schottky barrier field-effect transistors (FET’s) has been found. The FET’s were fabricated using capless annealing to avoid thermal stress that occurs at a dielectric/GaAs interface during capped annealing. Both mean and standard deviation in FET threshold voltage as a function of gate length are compared for FET’s oriented in the two perpendicular [110] directions. Very little orientation dependence is observed. Similar high-speed switching operation is also found for either orientation. These results indicate that stress-enhanced preferential lateral diffusion which appears to be a major factor in the orientation effect can be reduced through capless annealing.