Ferroelectric Transistors Research Articles

Ferroelectric transistors: the ultralow-power solution? [News

Academics have high hopes for ferroelectric materials. Adding a single layer of these materials, which have unusual electrical properties, to today's transistors could radically decrease the power consumption of chips. But as engineers presented the latest research on ferroelectrics at the IEEE International Electron Devices Meeting (IEDM), in San Francisco in December, the mood in the room fluctuated between excitement and doubt.

Investigations on the effects of electrode materials on the device characteristics of ferroelectric memory thin film transistors fabricated on flexible substrates

For flexible memory device applications, we propose memory thin-film transistors using an organic ferroelectric poly(vinylidene fluoride–trifluoroethylene) [P(VDF–TrFE)] gate insulator and an amorphous In–Ga–Zn–O (a-IGZO) active channel. The effects of electrode materials and their deposition methods on the characteristics of memory devices exploiting the ferroelectric field effect were investigated for the proposed ferroelectric memory thin-film transistors (Fe-MTFTs) at flat and bending states. It was found that the plasma-induced sputtering deposition and mechanical brittleness of the indium–tin oxide (ITO) markedly degraded the ferroelectric-field-effect-driven memory window and bending characteristics of the Fe-MTFTs. The replacement of ITO electrodes with metal aluminum (Al) electrodes prepared by plasma-free thermal evaporation greatly enhanced the memory device characteristics even under bending conditions owing to their mechanical ductility. Furthermore, poly(3,4-ethylenedioxythiophene)–poly(styrene sulfonate) (PEDOT:PSS) was introduced to achieve robust bending performance under extreme mechanical stress. The Fe-MTFTs using PEDOT:PSS source/drain electrodes were successfully fabricated and showed the potential for use as flexible memory devices. The suitable choice of electrode materials employed for the Fe-MTFTs is concluded to be one of the most important control parameters for highly functional flexible Fe-MTFTs.

Mimicking biological neurons with a nanoscale ferroelectric transistor.

Neuron is the basic computing unit in brain-inspired neural networks. Although a multitude of excellent artificial neurons realized with conventional transistors have been proposed, they might not be energy and area efficient in large-scale networks. The recent discovery of ferroelectricity in hafnium oxide (HfO2) and the related switching phenomena at the nanoscale might provide a solution. This study employs the newly reported accumulative polarization reversal in nanoscale HfO2-based ferroelectric field-effect transistors (FeFETs) to implement two key neuronal dynamics: the integration of action potentials and the subsequent firing according to the biologically plausible all-or-nothing law. We show that by carefully shaping electrical excitations based on the particular nucleation-limited switching kinetics of the ferroelectric layer further neuronal behaviors can be emulated, such as firing activity tuning, arbitrary refractory period and the leaky effect. Finally, we discuss the advantages of an FeFET-based neuron, highlighting its transferability to advanced scaling technologies and the beneficial impact it may have in reducing the complexity of neuromorphic circuits.

Hysteresis Reduction in Negative Capacitance Ge PFETs Enabled by Modulating Ferroelectric Properties in HfZrO x

We experimentally demonstrate that hysteresis of negative capacitance (NC) Ge pFETs is reduced through modulating the ferroelectric properties in HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> (HZO) by changing the post annealing temperature. As annealing temperature varies from 350 °C to 450 °C, HZO exhibits a significant increasing in the ratio of remnant polarization P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> to coercive field E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> , which results in the improvement of the magnitude of ferroelectric NC CFE, therefore contributing to the reduction of hysteresis of the ferroelectric NC Ge transistors. It is also reported that the NC Ge transistor annealed at 450 °C has a small hysteresis of 0.10 V, and achieves the improved SS and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> compared to control device without HZO.

A Nitrided Interfacial Oxide for Interface State Improvement in Hafnium Zirconium Oxide-Based Ferroelectric Transistor Technology

We examine the nature of the interface states induced during the integration of ferroelectric hafnium zirconium oxide on silicon. Metal-ferroelectric-insulator-silicon capacitors, with a thin layer of hafnium zirconium oxide grown by atomic layer deposition as the ferroelectric and various interfacial oxide layers as the insulator, are investigated. Since a high-temperature post-annealing is necessary to induce the formation of the ferroelectric phase in this oxide stack, the integrity of the oxide/silicon interface must be preserved after high-temperature processing. As such, we show that a nitrided interlayer provides an improved midgap interface state density among all interfacial oxides investigated. Furthermore, we quantify the interface states using the ac conductance technique and model the interface trap distribution across the silicon bandgap in order to explain and verify the experimental measurements.

Direct visualization of polarization reversal of organic ferroelectric memory transistor by using charge modulated reflectance imaging

By using the charge modulated reflectance (CMR) imaging technique, charge distribution in the pentacene organic field-effect transistor (OFET) with a ferroelectric gate insulator [P(VDF-TrFE)] was investigated in terms of polarization reversal of the P(VDF-TrFE) layer. We studied the polarization reversal process and the carrier spreading process in the OFET channel. The I-V measurement showed a hysteresis behavior caused by the spontaneous polarization of P(VDF-TrFE), but the hysteresis I-V curve changes depending on the applied drain bias, possibly due to the gradual shift of the polarization reversal position in the OFET channel. CMR imaging visualized the gradual shift of the polarization reversal position and showed that the electrostatic field formed by the polarization of P(VDF-TrFE) contributes to hole and electron injection into the pentacene layer and the carrier distribution is significantly dependent on the direction of the polarization. The polarization reversal position in the channel region is governed by the electrostatic potential, and it happens where the potential reaches the coercive voltage of P(VDF-TrFE). The transmission line model developed on the basis of the Maxwell-Wagner effect element analysis well accounts for this polarization reversal process in the OFET channel.

A Ferroelectric Thin Film Transistor Based on Annealing-Free HfZrO Film

A ferroelectric thin film transistor (Fe-TFT) based on annealing-free hafnium zirconium oxide (HfZrO) is demonstrated in this paper. Indium zinc oxide was used as channel semiconductor. The as-deposited 30-nm HfZrO film implemented as gate dielectric was proved to be crystallized with a mixture of monoclinic, tetragonal, and orthorhombic phases and showed ferroelectricity naturally. Thus, high temperature annealing process was avoided. The transfer characteristic of this Fe-TFT was demonstrated with operating voltage that was smaller than 3 V, memory window about 1 V, and small subthreshold slope (SS) about 82 mV/dec. The charge trapping phenomenon in this device was explored by characterizing the transfer curves with different ranges of gate voltages. This HfZrO-based device with low processing thermal budget and small SS has high potential for Fe-TFT memory which can be used in oxide semiconductor-based systems and applications.

Intrinsic speed limit of negative capacitance transistors

The emergence of negative capacitance as a way to limit power dissipation in CMOS logic transistors has raised the question of response delay of ferroelectric negative capacitance. Latency requirements for digital logic require a response time on the order of 10 ps or less. In this letter, we establish a coherent theoretical framework to analyze the delay between the clock edge at the gate and the response of the semiconductor channel in a ferroelectric negative capacitance transistor. The standard Landau–Khalatnikov equation approximates the slow, diffusive limit of the classical equation of motion. Therefore, using it to predict the response speed is unphysical. After extracting the damping and kinetic inductance from THz spectroscopy data, we simulate the full classical equation of motion and analyze the delay. We find that for doped hafnium oxides, the intrinsic delay is around 270 fs, far less than what is required for digital logic.

Excellent low-voltage operating flexible ferroelectric organic transistor nonvolatile memory with a sandwiching ultrathin ferroelectric film

The high operating voltage is a primary issue preventing the commercial application of the ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memory (NVM). In this work, we propose a novel route to resolve this issue by employing two ultrathin AlOX interfacial layers sandwiching an ultrathin ferroelectric polymer film with a low coercive field, in the fabricated flexible Fe-OFET NVM. The operation voltage of Fe-OFET NVMs decreases with the downscaling thickness of the ferroelectric film. By inserting two ultrathin AlOX interfacial layers at both sides of the ultrathin ferroelectric film, not only the gate leakage is prominently depressed but also the mobility is greatly improved. Excellent memory performances, with large mobility of 1.7 ~ 3.3 cm2 V−1 s−1, high reliable memory switching endurance over 2700 cycles, high stable data storage retention capability over 8 × 104 s with memory on-off ratio larger than 102, are achieved at the low operating voltage of 4 V, which is the lowest value reported to data for all Fe-OFET NVMs. Simultaneously, outstanding mechanical fatigue property with the memory performances maintaining well over 7500 bending cycles at a bending radius of 5.5 mm is also achieved in our flexible FE-OFET NVM.

Ferroelectric Negative Capacitance GeSn PFETs With Sub-20 mV/decade Subthreshold Swing

Negative capacitance (NC) GeSn pFETs integrated with HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> (HZO) ferroelectric film is demonstrated with sub-20 mV/decade subthreshold swing (SS) over two orders of magnitude of IDS. The ratio of remnant polarization to coercivity in HZO is significantly improved with the increasing of the annealing temperature from 400°C to 500°C, which contributes to the effective reduction of hysteresis in ferroelectric NC GeSn transistors. Ferroelectric NC GeSn pFET annealed at 500°C achieves a hysteresis of 70 mV while maintaining a steep SS dramatically lower than 60 mV/decade, and an improved IDS over control device without HZO.

Enhancement of the Electrical Performance of the Organic Ferroelectric Memory Transistor by Reducing the Surface Roughness of the Polymer Insulator with a Homo-Bilayer PVDF-TrFE

Enhancement of the Electrical Performance of the Organic Ferroelectric Memory Transistor by Reducing the Surface Roughness of the Polymer Insulator with a Homo-Bilayer PVDF-TrFE

Organic Ferroelectric-Based 1T1T Random Access Memory Cell Employing a Common Dielectric Layer Overcoming the Half-Selection Problem.

Organic electronics based on poly(vinylidenefluoride/trifluoroethylene) (P(VDF-TrFE)) dielectric is facing great challenges in flexible circuits. As one indispensable part of integrated circuits, there is an urgent demand for low-cost and easy-fabrication nonvolatile memory devices. A breakthrough is made on a novel ferroelectric random access memory cell (1T1T FeRAM cell) consisting of one selection transistor and one ferroelectric memory transistor in order to overcome the half-selection problem. Unlike complicated manufacturing using multiple dielectrics, this system simplifies 1T1T FeRAM cell fabrication using one common dielectric. To achieve this goal, a strategy for semiconductor/insulator (S/I) interface modulation is put forward and applied to nonhysteretic selection transistors with high performances for driving or addressing purposes. As a result, high hole mobility of 3.81 cm2 V-1 s-1 (average) for 2,6-diphenylanthracene (DPA) and electron mobility of 0.124 cm2 V-1 s-1 (average) for N,N'-1H,1H-perfluorobutyl dicyanoperylenecarboxydiimide (PDI-FCN2 ) are obtained in selection transistors. In this work, we demonstrate this technology's potential for organic ferroelectric-based pixelated memory module fabrication.

Ferroelectric transistors with monolayer molybdenum disulfide and ultra-thin aluminum-doped hafnium oxide

In this letter, we demonstrate ferroelectric memory devices with monolayer molybdenum disulfide (MoS2) as the channel material and aluminum (Al)-doped hafnium oxide (HfO2) as the ferroelectric gate dielectric. Metal-ferroelectric-metal capacitors with 16 nm thick Al-doped HfO2 are fabricated, and a remnant polarization of 3 μC/cm2 under a program/erase voltage of 5 V is observed. The capability of potential 10 years data retention was estimated using extrapolation of the experimental data. Ferroelectric transistors based on embedded ferroelectric HfO2 and MoS2 grown by chemical vapor deposition are fabricated. Clockwise hysteresis is observed at low program/erase voltages due to slow bulk traps located near the 2D/dielectric interface, while counterclockwise hysteresis is observed at high program/erase voltages due to ferroelectric polarization. In addition, the endurances of the devices are tested, and the effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, are observed. Reliable writing/reading in MoS2/Al-doped HfO2 ferroelectric transistors over 2 × 104 cycles is achieved. This research can potentially lead to advances of two-dimensional (2D) materials in low-power logic and memory applications.

Roughness Reduction of PVDF-TrFE Insulator by Reverse Transfer Printing for Enhanced Performance of Ferroelectric Organic Memory Transistors

Roughness Reduction of PVDF-TrFE Insulator by Reverse Transfer Printing for Enhanced Performance of Ferroelectric Organic Memory Transistors

Cover Picture: Investigation of strain-induced phase transformation in ferroelectric transistor using metal-nitride gate electrode (Phys. Status Solidi RRL 3/2017)

Cover Picture: Investigation of strain-induced phase transformation in ferroelectric transistor using metal-nitride gate electrode (Phys. Status Solidi RRL 3/2017)

Investigation of strain-induced phase transformation in ferroelectric transistor using metal-nitride gate electrode

In this work, we report a ferroelectric memory with strained-gate engineering. The memory window of the high strain case was improved by ∼71% at the same ferroelectric thickness. The orthorhombic phase transition (from ferroelectric to anti-ferroelectric transition) plays a key role in realizing negative capacitance effect at high gate electric field. Based on a reliable first principles calculation, we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. This ferroelectric strain technology shows the potential for emerging device application.

High temperature performance of Si:HfO2 based long channel Double Gate Ferroelectric Junctionless Transistors

In this work, we present a study that explores the suitability of Double Gate Ferroelectric Junctionless Transistor (DGFJL) incorporating Si:HfO2 for high temperature applications. At present, very few studies are focussed on Si:HfO2 to investigate its integrability in the present CMOS design space. Therefore, in the present study, using analytical modeling and TCAD simulations, it is demonstrated that Si:HfO2 based DGFJL exhibits superior performance in terms of substantial gain, reduced leakage currents, improved current drivability and high Ion/Ioff ratio at elevated temperatures as compared to the DGJL counterpart. The study, thus, highlights the fact that DGFJL is a potential candidate for device applications at high temperatures.

High-performance black phosphorus top-gate ferroelectric transistor for nonvolatile memory applications

Two-dimensional (2D) van der Waals (vdW) atomic crystals have been extensively studied and significant progress has been made. The newest 2D vdW material, called black phosphorus (BP), has attracted considerable attention due to its unique physical properties, such as its being a singlecomponent material like graphene, and its having a high mobility and direct band gap. Here, we report on a high-performance BP nanosheet based ferroelectric field effect transistor (FeFET) with a poly(vinylidenefluoride-trifluoroethylene) top-gate insulator for a nonvolatile memory application. The BP FeFETs show the highest linear hole mobility of 563 cm2/Vs and a clear memory window of more than 15 V. For more advanced nonvolatile memory circuit applications, two different types of resistive-load and complementary ferroelectric memory inverters were implemented, which showed distinct memory on/off switching characteristics.

Ultrathin flexible memory devices based on organic ferroelectric transistors

Here, we demonstrate ultrathin, flexible nonvolatile memory devices with excellent durability under compressive strain. Ferroelectric-gate field-effect transistors (FeFETs) employing organic semiconductor and polymer ferroelectric layers are fabricated on a 1-µm-thick plastic film substrate. The FeFETs are characterized by measuring their transfer characteristics, programming time, and data retention time. The data retention time is almost unchanged even when a 50% compressive strain is applied to the devices. To clarify the origin of the excellent durability of the devices against compressive strain, an intermediate plane is calculated. From the calculation result, the intermediate plane is placed close to the channel region of the FeFETs. The high flexibility of the ferroelectric polymer and ultrathin device structure contributes to achieving a bending radius of 0.8 µm without the degradation of memory characteristics.

Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric

The implementation and operation of the nonvolatile ferroelectric memory (NVM) tunnel field effect transistors with silicon-doped HfO2 is proposed and theoretically examined for the first time, showing that ferroelectric nonvolatile tunnel field effect transistor (Fe-TFET) can operate as ultra-low power nonvolatile memory even in aggressively scaled dimensions. A Fe-TFET analytical model is derived by combining the pseudo 2-D Poisson equation and Maxwell’s equation. The model describes the Fe-TFET behavior when a time-dependent voltage is applied to the device with hysteretic output characteristic due to the ferroelectric’s dipole switching. The theoretical results provide unique insights into how device geometry and ferroelectric properties affect the Fe-TFET transfer characteristic. The recently explored ferroelectric, silicon-doped HfO2 is employed as the gate ferroelectric. With the ability to engineer ferroelectricity in HfO2 thin films, a high-K dielectric well established in memory devices, the silicon-doped HfO2 opens a new route for improved manufacturability and scalability of future 1-T ferroelectric memories. In the current research, a Si:HfO2 based Fe-TFET with large memory window and low power dissipation is designed and simulated. Utilizing our presented model, the device characteristics of a Fe-TFET that takes full benefits from Si:HfO2 is compared with the same devices using well-known perovskite ferroelectrics. Finally, the Fe-TFET is compared with a conventional ferroelectric memory transistor highlighting the advantages of using tunneling memory devices.