Ferroelectric Transistor Memory Research Articles

MoS2 Nanosheets for Top‐Gate Nonvolatile Memory Transistor Channel

Top-gate ferroelectric memory transistors with single- to triple-layered MoS2 nanosheets adopting poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] are demonstrated. The nonvolatile memory transistor with a single-layer MoS2 channel exhibits excellent retention properties for more than 1000 s, maintaining ~5 × 103 for the program/erase ratio and displaying a high mobility of ~220 cm2/(V·s). Detailed facts of importance to specialist readers are published as ”Supporting Information”. Such documents are peer-reviewed, but not copy-edited or typeset. They are made available as submitted by the authors. Please note: The publisher is not responsible for the content or functionality of any supporting information supplied by the authors. Any queries (other than missing content) should be directed to the corresponding author for the article.

Organic inkjet-patterned memory array based on ferroelectric field-effect transistors

An inkjet-patterned, flexible organic memory array was demonstrated using non-volatile ferroelectric field-effect transistors which remained functional below 0.6% tensile strain. Each memory cell is comprised of an addressing transistor and a ferroelectric memory transistor. Less than 20% cross-talk was observed between neighboring cells, and binary memory states in a 7 × 8 array were retained for at least 8 h. Variations among the printed memory transistors were characterized and shown to be caused by different rates of charge trapping in the semiconductor–ferroelectric interface.

Electrical characteristics of Si MFIS-FETs using P(VDF-TrFE) thin films

Ferroelectric polymer memory transistors were fabricated by using PMMA (poly methyl metacrylate)-blended P(VDF-TrFE) (polyvinyliden fluoride-trifluoroethylene) as the gate ferroelectric film. The film was spin-coated on an SiO 2-coated n-type Si wafer with the p-type source and drain regions and Au electrodes for the source, drain, and gate terminals were formed by thermal evaporation, followed by wet chemical etching. The on/off ratio and memory window width of the fabricated ferroelectric-gate FET were typically 10 7 and 5 V at the gate voltage swing of ±11 V, respectively. As for the data retention characteristics, the current on/off ratio of approximately 10 3 was obtained at 10 3 s after write operation.

Impact of interface controlling layer of Al2O3 for improving the retention behaviors of In–Ga–Zn oxide-based ferroelectric memory transistor

We characterized the nonvolatile memory thin-film transistors, which was composed of an amorphous indium-gallium-zinc oxide (α-IGZO) active channel and a ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] gate insulator, and investigated the impact of an interface controlling layer. Excellent device performances, such as the field-effect mobility of 60.9 cm2 V−1 s−1, the subthreshold swing of 120 mV/dec, and the memory window of 6.4 V at ±12 V programming, were confirmed for the device without any interface layer. However, the memory retention time was very short. The retention behaviors could be dramatically improved when 4 nm thick Al2O3 layer was introduced between the P(VDF-TrFE) and α-IGZO.

Characterization of Pt/Bi3.15Nd0.85Ti3O12/HfO2/Si structure using a hafnium oxide as buffer layer for ferroelectric-gate field effect transistors

We have investigated the structural and electrical properties of metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with Bi3.15Nd0.85Ti3O12 (BNdT) thin film deposited on Si and hafnium oxide (HfO2)/Si substrates. Microstructural analysis reveals the formation of well-crystallized BNdT perovskite film and good interface between BNdT film and HfO2 buffer layer. Pt/BNdT/HfO2/Si structure exhibits a memory window of 1.12 V at an operation voltage of 3.5 V. The width of memory window for the MFIS structure varies with increasing thickness of HfO2 layer, and 4-nm-thickness is optimum. The results from the fatigue test indicate a slight degradation of the memory window after 1010 switching cycles. These properties are encouraging for the development of ferroelectric memory transistors.

All-organic single-transistor permanent memory device

ABSTRACTWe present an all-organic permanent memory transistor using an amorphous spin-cast gate insulator. This gate insulator exhibits a remanent polarisation in its amorphous state, a unique property, which is best described as “ferroelectric-like”. The memory transistor thus built perform extremely well, even when compared to inorganic ferroelectric memory transistors; the memory “on” to memory “off” current ratio is close to 3×10-a4, while time-dependent studies show retention times of 14 hours and more.

Ferroelectric 1-T memory device—will it be viable for nonvolatile memory applications?

ABSTRACTThe quest for a nonvolatile memory FET based on the metal-ferroelectric-(insulator)-semiconductor (MF(I)S) gate stack concept has greatly intensified in recent years. In principle, such a memory device (MF(I)S) could be a building block of an ideal memory technology which offers random access, high speed, low power, high density and non-volatility. In practice, however, none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days so far. These results are a far cry from the 10-year retention time requirement for non-volatile memory devices. This paper reveals progress and optimization that grain size, interfacial properties, and crystallinity of the annealed ferroelectric SrBi2Ta2O9 (SBT) films have a strong impact on the size of the memory window, as does the choice of the buffer layer material. The properties of SiN buffer layer sandwiched between SBT and Si are discussed. Switches in the polarization of the ferroelectric SBT play a key role for both the ferroelectric-polarization-dominated and the trapping-dominated memory windows. Preliminary results on MFIS capacitors and transistors are reviewed, limited retention time has been observed. A closer look at the physics of device operation reveals two major causes of the short retention time: (1) depolarization fields; (2) finite gate leakage current and the associated charge trapping. Here, the origins of these problems are analyzed and practical difficulties in attempting to realize nonvolatile ferroelectric 1-T memory devices are illustrated. Two possible solutions have been proposed to circumvent problems associated with the finite retention time in ferroelectric FETtype memories: (1) memory refreshes as done in the FEDRAM cell, (2) single-crystallize the ferroelectric film.

Conductive Metal Oxide Thin Film Ferroelectric Memory Transistor

One-transistor (1T) memory devices with MFMPIS (Metal, Ferroelectrics, Metal, Polysilicon, Insulator, Semiconductor) and MFMIS (Metal, Ferroelectrics, Metal, Insulator, Semiconductor) structures have been widely studied. These memory devices exhibit very good switching property but very poor retention properties. Three possible mechanisms are responsible for the poor retention of 1T ferroelectric memories: namely, leakage current with charges trapping within the ferroelectric film, floating gate effect, and the depolarization field. The gate stack of ferroelectric memory transistor consists of a top electrode, a ferroelectric layer, a bottom electrode, and a gate insulator. The bottom electrode is a floating electrode acting as a floating gate. As long as there is field across the ferroelectric thin film there is leakage current. The leakage current charge up the floating gate, the charge accumulation at the floating gate neutralizes the polarization charge at the ferroelectric material and causes the device to loss memory property. In order to overcome this problem we fabricated a metal/ferroelectric on semiconductive metal oxide on silicon substrate structure. There is no insulator in the gate stack. These device structures do not have floating gate and the very low de-polarization field. Therefore, the memory retention time can be very long. In this paper, we will report the integration processes and the working MFMoxS device properties with improved retention properties.

Why is nonvolatile ferroelectric memory field-effect transistor still elusive?

In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed.

All-perovskite-oxide ferroelectric memory transistor composed of Bi2Sr2CuOx and PbZr0.5Ti0.5O3 films

An all-perovskite-oxide transistor composed of a tetragonal perovskite PbZr0.5Ti0.5O3 (ferroelectric) and a layered perovskite Bi2Sr2CuO6 (conducting channel) is fabricated on a cubic perovskite Nb-doped SrTiO3 (gate electrode). We demonstrate a considerably large conductance modulation of Bi2Sr2CuO6 by varying the direction and magnitude of the polarization. The ratio of the ON- and OFF-state drain currents reaches 196. A memory retention time as long as about 8 h is also observed. The drain current versus the drain voltage curves analyzed by adopting a semiconductor model give fairly good agreement with the measurement data. We also discuss the advantages and future prospects of all-perovskite-oxide transistors.

Transmission electron microscope investigation of SrBi2Ta2O9 memory capacitors on Si with silicon dioxide and silicon nitride as buffers

Ferroelectric memory capacitors were made by deposition of SrBi2Ta2O9 (SBT) on Si with thin (∼40–90 Å) buffer layers of jet vapor deposition (JVD) silicon nitride and oxide. Transmission electron microscope analysis was carried out to compare the microscopic integrity of both films after subsequent processing steps. It was found that the thin SiO2 buffer layer failed to prevent further oxidation of the Si substrate and furthermore allowed the diffusion of the SBT towards the SiO2/Si interface. In contrast the silicon nitride layer deposited by the JVD process acted as a good barrier for the diffusion of SBT. It also stopped further oxidation of the Si substrate during subsequent annealing in oxygen. Electrical tests show that the capacitors have large memory windows and that the windows present only slight degradation after 1011 switching cycles. The use of JVD nitride as a buffer is encouraging for the further development of ferroelectric memory transistors.

SrBi 2 Ta 2 O 9 memory capacitor on Si with a silicon nitride buffer

We have made ferroelectric memory capacitors by depositing a SrBi2Ta2O9 thin film on a Si substrate separated by an ultrathin buffer layer of silicon nitride film. The hysteresis in the capacitance–voltage curves suggests a sizable memory window of 2 V with a programming voltage swing of ±7 V. The switching time is estimated to be on the order of nanosecond based on the results of a one-shot pulse experiment. The results from the fatigue test indicate a slight degradation of the memory window after 1011 switching cycles. These properties are encouraging for the development of ferroelectric memory transistors.