Ferroelectric Field Effect Transistor Memory Research Articles

(Invited) Fabrication Technique of Ferroelectric HfxZr1−XO2 Thin Films Using ALD-ZrO2 Nucleation Layers

Ferroelectric HfxZr1−xO2 (HZO) thin films have attracted considerable attention towards high-density and low-power ferroelectric memory devices of ferroelectric random access memory (FeRAM) and ferroelectric field-effect transistors (FeFETs) [1]. To obtain ferroelectric orthorhombic (O) phase of HZO films, several techniques have been investigated, such as the TiN stressor layer technique [2] and controlled annealing conditions [3]. On the other hand, we pay attention to the ZrO2 nucleation layer technique because ZrO2 films deposited by atomic layer deposition (ALD) method formed a nanocrystalline structure and consisted dominantly of O, tetragonal (T), and cubic (C) phases, whose lattice constants are considerably close to that of ferroelectric O phase for HfO2 [4]. In this paper, we report the crystallinity and ferroelectricity of HZO films fabricated using the ZrO2 nucleation layer technique for metal-ferroelectric-metal (MFM) and metal-ferroelectric-semiconductor (MFS) capacitors.First, four types of MFM capacitors of TiN/HZO/TiN (MFM w/o), TiN/HZO/bottom-ZrO2/TiN (MFM B-ZrO2), TiN/top-ZrO2/HZO/TiN (MFM T-ZrO2), and TiN/top-ZrO2/HZO/bottom-ZrO2/TiN (MFM D-ZrO2) were systematically investigated for the FeRAM applications [5]. The thicknesses of the ALD-grown HZO and ZrO2 films were 10 and 2 nm, respectively. The post-deposition annealing was performed at 600°C. The remanent polarization (2P r = P r + − P r −) of the MFM capacitors increased in the following order: MFM w/o (12 µC/cm2) < MFM B-ZrO2 (15 µC/cm2) < MFM T-ZrO2 (23 µC/cm2) < MFM D-ZrO2 (29 µC/cm2), while all capacitors showed almost the same coercive electric field (E c) value of around 1.2 MV/cm. Therefore, maximum 2P rvalue of the MFM capacitor was obtained using the top- and bottom-ZrO2 nucleation layers. For the MFM capacitors with ZrO2 nucleation layers, epitaxial-like grain growth of the HZO film occurred on the nanocrystalline top- and bottom-ZrO2 layers. Moreover, the relative ratio of O/T/C phases in the ferroelectric film, which was estimated using the peak area ratio of O(111)/T(101)/C(111)/{M(−111)+ O(111)/T(101)/C(111)+M(111)}, increased in the following order: MFM w/o < MFM B-ZrO2 < MFM T-ZrO2 < MFM D-ZrO2. Therefore, the top- and bottom-ZrO2 layers play an important role as nucleation layers for the crystallization of the HZO film, resulting in a larger relative ratio of O/T/C phases in the ferroelectric film compared to w/o. Moreover, these results indicate that the top-ZrO2 layer was more effective to form the ferroelectric phase compared to the bottom-ZrO2 layer.Next, two types of MFS capacitors of TiN/HZO/Si (MFS w/o) and TiN/top-ZrO2/HZO/Si (MFS T-ZrO2) were fabricated by low-temperature processes at 300°C of ALD and post-metallization annealing (PMA) for the FeFET applications [6]. The thicknesses of both HZO and ZrO2 films were 10 nm. Both MFS w/o and MFS T-ZrO2 were found to form an extremely thin SiO2 interfacial layer with a thickness of one or two monolayers between the HZO film and Si substrate due to a low temperature fabrication process of 300°C. The HZO film of the MFS T-ZrO2 formed O/T/C phases even with a low thermal budget of 300°C, while that of the MFS w/o had an amorphous structure. This result is attributed to the beneficial role of the nanocrystalline top-ZrO2 nucleation layer for the crystallization of an amorphous HZO film during the PMA process. Therefore, a higher 2P r value of 15 µC/cm2 was obtained for the MFS T-ZrO2 than that (2.2 µC/cm2) for the MFS w/o. Moreover, the endurance properties of the MFS T-ZrO2 were free from the wake-up effect and exhibited less degradation of switching polarization (P sw). This could be attributed to the insertion of a ZrO2 film at the TiN/HZO interface, which promoted the preferential formation of the ferroelectric orthorhombic phase and prevent the formation of oxygen vacancies at the ZrO2/HZO interface. Thus, we concluded that superior ferroelectricity with wake-up free properties and higher fatigue resistance of HZO-based MFS capacitors were achieved by using the ZrO2 nucleation layer technique.These results suggest that the fabrication technique of ferroelectric HZO films using nanocrystalline ALD-ZrO2 nucleation layers is one of the promising processes for the next-generation non-volatile memory device applications.This work was supported by JSPS KAKENHI (Nos. JP21J01667, JP20H02189, and JP18J22998) and MEXT Leading Initiative for Excellent Young Researchers (No. JPMXS0320220213).[1] T. Mikolajick et al., J. Appl. Phys. 129, 100901 (2021).[2] S. J. Kim, et al., Appl. Phys. Lett. 111, 242901 (2017).[3] S. Migita et al., Jpn. J. Appl. Phys. 58, SBBA07 (2019).[4] T. Onaya et. al., Appl. Phys. Express. 10, 081501 (2017).[5] T. Onaya et al., APL Mater. 7, 061107 (2019).[6] T. Onaya et al., APL Mater. 10, 051110 (2022).

Performance improvement of Hf0.45Zr0.55O x ferroelectric field effect transistor memory with ultrathin Al–O bonds-modified InO x channels

Ferroelectric field effect transistor (FeFET) memories with hafnium zirconium oxide (HZO) ferroelectric gate dielectric and ultrathin InO x channel exhibit promising applicability in monolithic three-dimensional (M3D) integrated chips. However, the inferior stability of the devices severely limits their applications. In this work, we studied the effect of single cycle of atomic-layer-deposited Al–O bonds repeatedly embedded into an ultrathin InO x channel (∼2.8 nm) on the Hf0.45Zr0.55O x FeFET memory performance. Compared to the pure InO x channel, three cycles of Al–O bonds modified InO x channel (IAO-3) generates a much larger memory window (i.e. drain current ratio between the programmed and erased devices) under the same program conditions (+5.5 V/500 ns), especially after post-annealing at 325 °C for 180 s in O2 (1238 versus 317). Meanwhile, the annealed IAO-3 FeFET memory also shows quite stable data retention up to 104 s, and much more robust program/erase stabilities till 105 cycles. This is because the modification of strong Al–O bonds stabilizes the oxygen vacancies and reduces the bulk trap density in the channel. Furthermore, it is indicated that the program and erase efficiencies increase gradually with reducing the channel length of the memory device. By demonstrating markedly improved performance of the HZO FeFET memory with the ultrathin IAO-3 channel, this work provides a promising device for M3D integratable logic and memory convergent systems.

Structure, performance regulation and typical device applications of HfO&lt;sub&gt;2&lt;/sub&gt;-based ferroelectric films

The rapid developments of big data, the internet of things, and artificial intelligence have put forward more and more requirements for memory chips, logic chips and other electronic components. This study introduces the ferroelectric origin of HfO&lt;sub&gt;2&lt;/sub&gt;-based ferroelectric film and explains how element doping, defects, stresses, surfaces and interfaces, regulate and enhance the ferroelectric polarization of the film. It is widely accepted that the ferroelectricity of HfO&lt;sub&gt;2&lt;/sub&gt;-based ferroelectric film originates from the metastable tetragonal phase. The ferroelectricity of the HfO&lt;sub&gt;2&lt;/sub&gt;-based film can be enhanced by doping some elements such as Zr, Si, Al, Gd, La, and Ta, thereby affecting the crystal structure symmetry. The introduction of an appropriate number of oxygen vacancy defects can reduce the potential barrier of phase transition between the tetragonal phase and the monoclinic phase, making the monoclinic phase easy to transition to tetragonal ferroelectric phase. The stability of the ferroelectric phase can be improved by some methods, including forming the stress between the substrate and electrode, reducing the film thickness, constructing a nanolayered structure, and reducing the annealing temperature. Compared with perovskite oxide ferroelectric thin films, HfO&lt;sub&gt;2&lt;/sub&gt;-based films have the advantages of good complementary-metal-oxide-semiconductor compatibility and strong ferroelectricity at nanometer thickness, so they are expected to be used in ferroelectric memory. The HfO&lt;sub&gt;2&lt;/sub&gt;-based 1T1C memory has the advantages of fast reading and writing speed, more than reading and writing 10&lt;sup&gt;12&lt;/sup&gt; times, and high storage density, and it is the fast reading and writing speed that the only commercial ferroelectric memory possesses at present. The 1T ferroelectric field effect transistor memory has the advantages of non-destructive reading and high storage density. Theoretically, these memories can achieve the same storage density as flash memory, more than reading 10&lt;sup&gt;10&lt;/sup&gt; times, the fast reading/writing speed, low operating voltage, and low power consumption, simultaneously. Besides, ferroelectric negative capacitance transistor can obtain a subthreshold swing lower than 60 mV/dec, which greatly reduces the power consumption of integrated circuits and provides an excellent solution for further reducing the size of transistors. Ferroelectric tunnel junction has the advantages of small size and easy integration since the tunneling current can be largely adjusted through ferroelectric polarization switching. In addition, the HfO&lt;sub&gt;2&lt;/sub&gt;-based field effect transistors can be used to simulate biological synapses for applications in neural morphology calculations. Moreover, the HfO&lt;sub&gt;2&lt;/sub&gt;-based films also have broad application prospects in antiferroelectric energy storage, capacitor dielectric energy storage, memristor, piezoelectric, and pyroelectric devices, etc. Finally, the current challenges and future opportunities of the HfO&lt;sub&gt;2&lt;/sub&gt;-based thin films and devices are analyzed.

On the Feasibility of 1T Ferroelectric FET Memory Array

To fully exploit the ferroelectric field effect transistor (FeFET) as compact embedded nonvolatile memory for various computing and storage applications, it is desirable to use a single FeFET (1T) as a unit cell and arrange the cells into an array. However, many write mechanisms for an 1T FeFET array reported in the literature are yet to be validated experimentally. In this work, we performed a comprehensive experimental characterization on the write operations in an 1T- NOR and 1T- AND array using n-channel bulk FeFETs. We discovered that: 1) the source/drain contact can only supply minority carriers (i.e., electrons) to the channel for polarization screening during the low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> TH state programming; 2) the body contact can not only supply majority carriers (i.e., holes) for efficient high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> TH state write, but also depletion charge for low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> TH state programming, though with lower efficiency; and 3) during the low/high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> TH programming, only the path that can supply negative/positive screening charges, respectively, need to respond, which necessitates the application of proper write biases on the corresponding terminal. Based on the understanding of these write mechanisms, we show the importance of localized body contact or column-wise body contact for the successful high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> TH state programming. We also show that the previously proposed C- AND write scheme fails to program the FeFET to the low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> TH state for our devices. Finally, we propose several write schemes for both 1T- AND and 1T- NOR arrays for various scenarios providing insights for choosing the appropriate write scheme, which will facilitate the adoption of 1T FeFET memory arrays for emerging applications.

Dynamical Effects of Excess Carriers on SOI FeFET Memory Device Operations

We study the carrier dynamics of memory program (PGM) and readout operations for an n-type silicon-on-insulator (SOI) ferroelectric field-effect transistor (FeFET) through TCAD simulations. We found that gate-induced drain leakages (GIDL) during the PGM operation with large negative gate biases can result in excess hole concentrations as high as 7.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10^{{20}}$ </tex-math></inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-{3}}$ </tex-math></inline-formula> in the potential well formed in the SOI channel. The hole accumulation causes a large electric field across the ferroelectric (FE) layer and results in a polarization boost at a low PGM voltage. For a nano-scale SOI channel, the retention time of the excess holes can exceed microseconds according to our simulations. The outflow of the excess holes leads to a transient effect in the drain current during the readout operation, and we observed additional retention effects for the FeFET memory window due to the hole dynamic effects on the electrostatics and the FE polarizations. While the excess holes result in a ~100 ps delay in the readout phase before a large read margin can be detected, they have boosted the PGM speed and polarization window. The boosted polarization can be retained for milliseconds, and potentially beyond, resulting in an appreciable ON/OFF ratio during readout. Therefore, such effects can be utilized for low-power memory applications through proper SOI FeFET designs with the awareness of excess carrier dynamics.

Effect of thickness scaling on the switching dynamics of ferroelectric HfO2–ZrO2 capacitors

HfO2-based ferroelectric (FE) films have attracted immense attention in the research of ferroelectric random access memory (FeRAM) and ferroelectric field-effect transistors (FeFETs) due to their excellent ferroelectric performance and high compatibility with CMOS integration. The study of switching dynamics is essential in understanding and optimizing HfO2-based FE films for nonvolatile memory applications. To explore the effect of thickness scaling on the polarization switching speed of the HfO2-ZrO2 (HZO) FE film, we demonstrate TaN/HZO/TaN capacitors fabricated with 6, 10, and 20 nm-thick HZO films. The inhomogeneous field mechanism (IFM) model was used to characterize the polarization switching of polycrystalline HZO films. The results showed that the characteristic time constants for the 6, 10, and 20-nm-thick HZO samples were 283, 43.7, and 20.5 ps, respectively, which is inconsistent with the variation in coercive electric field (EC) with sample thickness. These results demonstrate the distribution of the local fields in capacitors with various HZO thicknesses and contribute to the design and optimization of HZO films for advanced nanonode applications.

Numerical simulation of single-event effects in fully-depleted silicon-on-insulator HfO&lt;sub&gt;2&lt;/sub&gt;-based ferroelectric field-effect transistor memory cell

Ferroelectric field-effect transistor (FeFET) memory is currently a popular non-volatile memory. It has many advantages such as nonvolatility, better scalability, energy-efficient switching with non-destructive read-out and anti-radiation. To promote the application of FeFET in radiation environments, the single-event transient effect in HfO&lt;sub&gt;2&lt;/sub&gt;-based fully-depleted silicon-on-insulator (FDSOI) FeFET memory cell is studied by technology computer aided design (TCAD) numerical simulation. The effects of different incident positions and angles of heavy ions and the drain bias voltage on the characteristics of the memory cell are analyzed. The results show that the corresponding polarization state in the HfO&lt;sub&gt;2&lt;/sub&gt; ferroelectric layer will not reverse regardless of the change for the incident position of heavy ions, but the transient change of the output voltage for the memory cell will be affected. The most sensitive area is close to the drain-body junction area. Moreover, with the decrease of the ion incidence angle, the peak of output voltage for the memory cell increases. And the effect of the incident angle change is more obvious when reading data is “0” rather than “1”. The peak of output voltage for the memory cell is modulated by the drain bias voltage, and the modulation effect is more obvious when reading data is “1” rather than “0”. The above findings provide theoretical basis and guidance for the anti-single event design of the FDSOI FeFET memory cell.

Characterizing Ferroelectric Properties of Hf0.5Zr0.5O2 From Deep-Cryogenic Temperature (4 K) to 400 K

Ferroelectric Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) thin film has obtained considerable attention for emerging non-volatile memory (eNVM) and synaptic device applications. To our best knowledge, the polarization switching of HZO has not been comprehensively investigated in wide-ranging temperatures from deep-cryogenic 4 K to elevated temperature 400 K within the same set of test structures. In this work, we experimentally characterize the reliability effects such as endurance (wake-up, fatigue, and breakdown), retention (including imprint), and small-signal response of the HZO capacitor from the lowest temperature reported (4 K) to the elevated temperature (400 K). We demonstrate one of the highest endurance cycles <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ &gt; 3.5\times 10^{10}$ </tex-math></inline-formula> among reported TiN/HZO/TiN capacitors with negligible wake-up/fatigue effects or retention degradation, all obtained at 4 K. Based on the experimental results, we further simulated ferroelectric random access memory (FeRAM) and ferroelectric field-effect transistor (FeFET) to evaluate their potentials as cryogenic memories.

(Invited) Ferroelectric Hafnium Oxide for Non-Volatile Memory Applications: From Single Capacitors to Memory Arrays

This year marks the 10th anniversary of the public announcement of the discovery of ferroelectricity in HfO2-based thin films. Tremendous strides have been made in both the physical understanding and the technological use of ferroelectric HfO2. These unique fluorite-structured ferroelectrics have outstanding potential for commercial applications due to their scalability, CMOS-compatibility, and facile manufacturability. Such advantages make ferroelectric HfO2 particularly attractive for nonvolatile memories technologies such as ferroelectric random access memory (FRAM) and ferroelectric field effect transistors. Due to the wide variety of conditions in which ferroelectricity can emerge in HfO2 thin films, there has been a vast effort by the international scientific community to enhance and optimize the ferroelectric properties using a wide variety of approaches. Advancements in thin film ferroelectric capacitor and memory array technologies are therefore progressing rapidly.The structural properties of HfO2 are a major focal point for technology development because the competition between several crystalline phases in HfO2 thin films can have a major impact on device performance. For thin film memory capacitors, stabilizing the polar orthorhombic phase and eliminating secondary paraelectric phases is paramount in achieving robust polycrystalline HfO2 ferroelectrics. Doping and the presence of a capping electrode during crystallization have been extensively demonstrated to influence the emergence and stability of the ferroelectric orthorhombic phase. Greater attention has been placed recently on the thin film growth conditions in atomic layer deposition and physical vapor deposition, especially with regard to the oxidation conditions that have been shown to have a substantial impact on the device performance of ferroelectric HfO2 and Hf0.5Zr0.5O2 capacitors. Composition, film growth, and the crystallization processes are critical aspects for thin film ferroelectric capacitor development and the latest developments will be comprehensively reviewed in the context of how the material properties relate to nonvolatile memory performance.Developments in thin film HfO2 ferroelectric capacitors are now coming to fruition with the emergence of ferroelectric random access memory arrays and demonstrators. Thin film ferroelectric HfO2 based capacitors are successfully being demonstrated in back-end-of-line (BEOL) processes at the 130nm CMOS technology. The performance of these early demonstrator memory arrays show very promising long term data retention, large memory windows with good statistical distributions, and projections for area scaling to nanoscale dimensions. The transition from large-scale micron-sized laboratory devices to smaller scale integrated capacitors has proven to be a major step forward in endurance cycling with >1011 cycles being reported in memory arrays. The most recent integration of thin film ferroelectric HfO2 capacitors into FRAM memory arrays and what future developments are expected for HfO2 ferroelectric random access memories will be presented. Figure 1

Ferroelectricity in CMOS-Compatible Hafnium Oxides: Reviving the ferroelectric field-effect transistor technology

A Ferroelectric Field-Effect Transistor (FEFET) is a promising candidate for next-generation memory devices because it offers numerous advantages, such as its high speed, low energy profile, and nondestructive readout process. FEFETs merge logic and memory functionality in a single device, allowing efficient data transfer and a high packing density, which could make them vital for use in future in-memory computing architectures. Although issues related to the integration of perovskite materials in the state-of-the art semiconductor industry limited their commercial success, the discovery of ferroelectricity in CMOS-compatible doped hafnium oxides led to a re-emergence of FEFETs in advanced microelectronics. The demonstration of ferroelectricity in doped hafnia at extremely thin film thicknesses plus its low permittivity, high coercive field (Ec), environment-friendly composition, and excellent CMOS compatibility are expected to unleash the promise of FEFETs, and significant progress has been made in this regard.

High Speed and Large Memory Window Ferroelectric HfZrO₂ FinFET for High-Density Nonvolatile Memory

We fabricated the HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) ferroelectric fin field-effect transistors (Fe-FinFET) with fin width of 60 nm and gate length of 100 nm for ferroelectric nonvolatile memory operations. The fabricated Fe-FinFET exhibited a large memory window (MW) of 1.5 V and high (100 ns) program/erase speeds at ±5 V. After 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> program/erase cycles, the MW was maintained at 1.09 V and the retention time was measured up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s with no degradation. The fabricated HZO Fe-FinFET is compatible with the current FinFET process and has a high MW, a fast program/erase speed, and excellent reliability. Therefore, the fabricated Fe-FinFET is a promising candidate for high-density ferroelectric field-effect transistor memory applications.

Performance Improvement by Modifying Deposition Temperature in HfZrO x Ferroelectric Memory

The HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> (HZO) ferroelectric material is a promising material for ferroelectric memory and is compatible with the semiconductor process for ferroelectric random access memory (FeRAM) and negative capacitance field effect transistor. However, defects often exist in the grain boundary to influence the performance or reliability of devices. In addition, uniformity between devices must be considered when they are mass-produced. Therefore, the grain size will become important in determining the performance and reliability. In this study, we use electrical measurements of current-voltage, capacitance-voltage, and polarization-voltage measurements to test high- and low-temperature deposition devices, with a transmission electron microscope (TEM) image to confirm the grain size. Finally, we propose a model to explain the phenomenon and provide a method to obtain better ferroelectric memory.

A FeFET with a novel MFMFIS gate stack: towards energy-efficient and ultrafast NVMs for neuromorphic computing

The discovery of ferroelectricity in the fluorite structure based hafnium oxide (HfO2) material sparked major efforts for reviving the ferroelectric field effect transistor (FeFET) memory concept. A Novel metal-ferroelectric-metal-ferroelectric-insulator-semiconductor (MFMFIS) FeFET memory is reported based on dual ferroelectric integration as an MFM and MFIS in a single gate stack using Si-doped Hafnium oxide (HSO) ferroelectric (FE) material. The MFMFIS top and bottom electrode contacts, dual HSO based ferroelectric layers, and tailored MFM to MFIS area ratio (AR-TB) provide a flexible stack structure tuning for improving the FeFET performance. The AR-TB tuning shows a tradeoff between the MFM voltage increase and the weaker FET Si channel inversion, particularly notable in the drain saturation current I D(sat) when the AR-TB ratio decreases. Dual HSO ferroelectric layer integration enables a maximized memory window (MW) and dynamic control of its size by tuning the MFM to MFIS switching contribution through the AR-TB change. The stack structure control via the AR-TB tuning shows further merits in terms of a low voltage switching for a saturated MW size, an extremely linear at wide dynamic range of the current update, as well as high symmetry in the long term synaptic potentiation and depression. The MFMFIS stack reliability is reported in terms of the switching variability, temperature dependence, endurance, and retention. The MFMFIS concept is thoroughly discussed revealing profound insights on the optimal MFMFIS stack structure control for enhancing the FeFET memory performance.

Post-CMOS Compatible Aluminum Scandium Nitride/2D Channel Ferroelectric Field-Effect-Transistor Memory.

Recent advances in oxide ferroelectric (FE) materials have rejuvenated the field of low-power, nonvolatile memories and made FE memories a commercial reality. Despite these advances, progress on commercial FE-RAM based on lead zirconium titanate has stalled due to process challenges. The recent discovery of ferroelectricity in scandium-doped aluminum nitride (AlScN) presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approximately 350 °C), making it compatible with back end of the line integration on silicon logic. Here, we present a FE-FET device composed of an FE-AlScN dielectric layer integrated with a two-dimensional MoS2 channel. Our devices show an ON/OFF ratio of ∼106, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable memory states up to 104 cycles and state retention up to 105 s. Our results suggest that the FE-AlScN/2D combination is ideal for embedded memory and memory-based computing architectures.

Determination of Hafnium Zirconium Oxide Interfacial Band Alignments Using Internal Photoemission Spectroscopy and X-ray Photoelectron Spectroscopy.

Doped ferroelectric HfO2 is highly promising for integration into complementary metal-oxide semiconductor (CMOS) technology for devices such as ferroelectric nonvolatile memory and low-power field-effect transistors (FETs). We report the direct measurement of the energy barriers between various metal electrodes (Pt, Au, Ta, TaN, Ti/Pt, Ni, Al) and hafnium zirconium oxide (Hf0.58Zr0.42O2, HZO) using internal photoemission (IPE) spectroscopy. Results are compared with valence band offsets determined using the three-sample X-ray photoelectron spectroscopy (XPS) as well as the two-sample hard X-ray photoelectron spectroscopy (HAXPES) techniques. Both XPS and IPE indicate roughly the same dependence of the HZO barrier on metal work function with a slope of 0.8 ± 0.5. XPS and HAXPES-derived barrier heights are on average about 1.1 eV smaller than barrier heights determined by IPE, suggesting the presence of negative charge in the HZO.

On the Reliability of FeFET On-Chip Memory

Ferroelectric Field-Effect Transistor (FeFET) is a promising future technology for non-volatile on-chip memories. It is rapidly attracting an ever-increasing attention from industry. The key advantage of FeFETs is full compatibility with the existing CMOS fabrication process beside their very low power consumption. To enable ultra-dense memories, 1-FeFET AND Arrays were proposed in which a memory cell is formed from merely a single FeFET. All access transistors, which are traditionally needed to operate memory cells, are removed. However, this imposes a new challenge of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">indirect write disturbances</i> . Neighboring memory cells are indirectly degraded whenever a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">direct write operation</i> occurs to a particular FeFET cell. Only recently the impact of such indirect disturbances on the FeFET reliability was experimentally investigated at device (i.e., transistor) level. However, to explore and properly judge the feasibility of 1-FeFET AND Arrays for on-chip memories, investigating only the reliability of individual cells is indeed insufficient. Bridging the gap between the device level and system (i.e., chip) level is inevitable. In the presence of indirect disturbances, the position of a write access within the array plays a key role, which is governed by the running workloads. In addition, whether the write operation flips the previously stored value or not also plays an important role with regards to reliability. Hence, running workloads, which determine not only the position of the memory cells to be written but also the values written to them, plays an essential role in determining 1-FeFET AND Array reliability over time. Therefore, studying the reliability of FeFETs only at the device level (as done in state of the art) is insufficient. In this work, we investigate, for the first time, the reliability of FeFET memories from device to system level. To achieve that, we develop a unified model capturing the impact of both <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">indirect</i> disturbances and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">direct</i> writes on the reliability of FeFET cells. Our study at system level then employs the unified model in the context of application workloads. We investigate different array sizes, write voltages, write methods and a wide range of workloads using the example of CPU caches as an example of on-chip memory. We demonstrate that indirect write disturbances are the dominate effect degrading the reliability of FeFET memories. For most cells, it contributes over 90 percent to the overall induced degradation. This provides guidelines for researchers at both device and circuit level to optimize the FeFET reliability further while considering the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">hidden</i> impact of indirect write disturbances.

Enabling large memory window and high reliability for FeFET memory by integrating AlON interfacial layer

A thin film of AlON with a nitrogen concentration of 13% was developed as the interfacial layer (IL) of HfZrOx-based ferroelectric field-effect transistor (FeFET) memory devices on a Si substrate. Compared to the conventional SiO2/SiON IL, due to a higher dielectric constant value that allows a smaller voltage drop across it and a larger valence band offset (ΔEv) with respect to Si along with prominent passivation of Si dangling bonds that effectively suppress hole trapping, memory devices with the AlON IL demonstrate a large memory window (MW) of 3.12 V by ±4 V gate voltage sweeping, robust endurance after 105 cycles with a long pulse width of 10−4 s, and a stable MW of 2.95 V up to 10 years, standing out from other HfZrOx-based FeFET memory reported in the literature. Furthermore, the AlON IL can be integrated with HfZrOx in the same atomic layer deposition step, which greatly simplifies the process. From the device performance and process integration points of view, the AlON IL unleashes the potential of FeFET memory by enabling high reliability with a large MW.

Polarization switching in thin doped HfO2 ferroelectric layers

The deployment of ferroelectrics in device concepts such as Ferroelectric Random Access Memory and Ferroelectric Field Effect Transistors requires a good understanding of the polarization switching mechanisms. While several reports already exist involving classical perovskite ferroelectrics, only recently has the switching dynamics in HfO2-based layers started to be addressed. In this work, the Kolmogorov–Avrami–Ishibashi (KAI), the Nucleation Limited Switching (NLS), the Landau–Khalatnikov (LK), and the Inhomogeneous Field Mechanism (IFM) models for polarization switching are surveyed and evaluated with the existing body of literature. Data concerning NLS and IFM are compared to experiments undertaken in this study. After excluding the KAI model because of considerations dealing with film morphology and domain wall energy, we conclude that the NLS, the LK, and the IFM models do not necessarily mutually exclude each other, but rather give a diverse perspective on the switching phenomenon based on thermodynamic, kinetic, statistic, microscopic, and/or macroscopic points of view.

A simulation study on low voltage operability of hafnium oxide based ferroelectric FET memories

Lower limit of operable voltage for ferroelectric field effect transistor memories using hafnium oxide based ferroelectric gate dielectrics was estimated using circuit simulations. Assuming realistic array architecture, memory weakening by disturbs and restrictions set by sneak current were taken into account. For modeling ferroelectricity, a continuous Preisach model of hysteresis was used. The results show that the lowest possible operation voltage, not including variability and reliability margin, will be around ±2 V. It was found that moderate reduction of remanent polarization is beneficial for lowering both operation voltage and interfacial layer electric field stress.

Ferroelectric memory field-effect transistors using CVD monolayer MoS2 as resistive switching channel

Ferroelectric field-effect transistors (FeFETs) have been considered as promising electrically switchable nonvolatile data storage elements due to their fast switching speed, programmable conductance, and high dynamic range for neuromorphic applications. Meanwhile, FeFETs can be aggressively shrunk to the atomic scale for a high density device integration, ideally, without comprising the performance by introducing two-dimensional (2D) materials. So far, the demonstrated 2D material-based FeFETs mainly rely on mechanically exfoliated flakes, which are not favorable for large-scale industrial applications, and FeFETs based on organic ferroelectrics typically show a large writing voltage (e.g., &amp;gt;±20 V), making these types of memory devices impractical to be commercially viable. Here, we demonstrate that monolayer MoS2 grown by chemical vapor deposition (CVD) can be used as a resistive switching channel to fabricate FeFETs, in which the MoS2 channel is modulated by a hybrid gate stack of HfO2/ferroelectric HfZrOx thin films. The programming processes in the 2D MoS2 FeFETs originate from the ferroelectric polarization switching, yielding two distinct write and erase states for data storage and cumulative channel conductance for artificial synapse applications. Our 2D FeFETs show a low-voltage-driven feature (&amp;lt;±3 V) and gate-tunable ferroelectric hysteresis characteristics. The thin HfO2 layer in the hybrid gate stack likely plays crucial roles in preserving the ferroelectricity of the device and lowering the threshold of switching voltages through energy redistribution. Our findings open an avenue for the use of CVD-grown layered materials as the resistive switching mediums combined with HfO2-based ferroelectrics for future energy-efficient “brain-on-a-chip” hardware.