Ferroelectric Gate Oxide Research Articles

Low-Temperature Nanosecond Laser Process of HZO-IGZO FeFETs toward Monolithic 3D System on Chip Integration.

Ferroelectric field-effect transistors (FeFETs) are increasingly important for in-memory computing and monolithic 3D (M3D) integration in system-on-chip (SoC) applications. However, the high-temperature processing required by most ferroelectric memories can lead to thermal damage to the underlying device layers, which poses significant physical limitations for 3D integration processes. To solve this problem, the study proposes using a nanosecond pulsed laser for selective annealing of hafnia-based FeFETs, enabling precise control of heat penetration depth within thin films. Sufficient thermal energy is delivered to the IGZO oxide channel and HZO ferroelectric gate oxide without causing thermal damage to the bottom layer, which has a low transition temperature (<250 °C). Using optimized laser conditions, a fast response time (<1 µs) and excellent stability (cycle >106, retention >106 s) are achieved in the ferroelectric HZO film. The resulting FeFET exhibited a wide memory window (>1.7V) with a high on/off ratio (>105). In addition, moderate ferroelectric properties (2·Pr of 14.7 µCcm-2) and pattern recognition rate-based linearity (potentiation: 1.13, depression: 1.6) are obtained. These results demonstrate compatibility in HZO FeFETs by specific laser annealing control and thin-film layer design for various structures (3D integrated, flexible) with neuromorphic applications.

Fabrication and characterization of HfxAl(1-x)Oy ceramic targets and thin films by RF sputtering

The potential of HfO2 as a memory semiconductor material with ferroelectric properties in thin-film deposition has been recently analyzed. In this study, the preparation, composition, and physical properties of Al-doped hafnium oxides were analyzed. HfxAl(1-x)Oy (HAO) [x = 0.33, 0.5, and 0.67] powders were prepared by controlling the ratio of Hf to Al and using ball milling. The HAO powder was calcined at 1000 °C in a furnace and then sintered in a temperature range of 1000–1600 °C by a solid-state reaction method to fabricate high-quality targets with high densities. The density and crystal size increased with the sintering temperature. The 1600-°C Hf0.67Al0.33Oy target was optimal for thin-film deposition. In addition, the target properties were affected by an increase in the HfO2 content x. The crystal structures and sizes, surface free energies, contact angles, and band gaps of the HAOs were evaluated to analyze their potential as high-k dielectric materials. HAO is a promising high-k dielectric and memory material, valuable for further studies on ferroelectric gate oxide materials. This study contributes to the increasing number of studies on the ferroelectricity of HfO2 thin films and provides a fundamental understanding of this material and its potential for novel device applications.

Assessment of the Biosensing Capabilities of SiGe Heterojunction Negative Capacitance-Vertical Tunnel Field-Effect Transistor.

In this study, a comparison of the negative capacitance vertical tunnel field-effect transistor (NC-VTFET) and VTFET for biosensing applications was conducted. Dielectrically modulated TFET demonstrates better sensitivity than the traditional metal oxide field effect transistor as a biosensor in label-free biosensing applications. The TFET biosensor, however, has much room for advancement by enhancing its DC characteristics. This research addresses the impact of ferroelectric gate oxide for integration of negative capacitance (NC) effect with the SiGe heterojunction pocket at the source-channel junction to enhance performance for biosensor applications. By putting the NC layer over SiO2, the channel voltage increases with decreased subthreshold slope and OFF current, thereby creating an NC effect. Because SiGe has a narrow band gap, pocket doping of SiGe near the source channel junction will increase the concentration of charge carriers, improving the band-to-band tunneling. In order to aid in the integration of biomolecules and to modulate band-to-band tunneling based on charge density (qf), dielectric constant (k), temperature, and cavity length, a cavity is additionally inserted above the source channel junction and underneath the NC layer, near to SiO2. These values were compared with and without the incorporation of NC layer with respect to various electrical properties such as drain current (Id), sensitivity, and electric field (E). According to the findings, labeled and label-free biosensors' sensitivity may be increased by incorporating the NC effect into VTFET biosensors.

Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor

Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we demonstrate a single vertical nanowire ferroelectric tunnel field-effect transistor (ferro-TFET) that can modulate an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing with significant suppression of undesired harmonics for reconfigurable analogue applications. We realize this by a heterostructure design in which a gate/source overlapped channel enables nearly perfect parabolic transfer characteristics with robust negative transconductance. By using a ferroelectric gate oxide, our ferro-TFET is non-volatilely reconfigurable, enabling various modes of signal modulation. The ferro-TFET shows merits of reconfigurability, reduced footprint, and low supply voltage for signal modulation. This work provides the possibility for monolithic integration of both steep-slope TFETs and reconfigurable ferro-TFETs towards high-density, energy-efficient, and multifunctional digital/analogue hybrid circuits.

Ge/GaAs Based Negative Capacitance Tunnel FET Biosensor: Proposal and Sensitivity Analysis

A highly sensitive, accurate, fast and power efficient biosensor is the need of the hour. Undoubtedly, dielectrically modulated (DM) tunnel FET (TFET) assures better sensitivity as compared to MOSFET biosensors in case of label-free biosensing. However, there exists immense possibilities to upgrade TFET biosensor properties through the improvement of its DC characteristics. Therefore, in this paper a ferroelectric (FE) gate oxide and a hetero material (HM) source/drain-channel based TFET is designed for biosensor applications. A FE layer of HfZrO2 above SiO2 gives rise to negative capacitance (NC) effect that causes voltage amplification and hence, boosts subthreshold swing (SS) and ION/IOFF ratio. In addition, use of a low band gap material (Ge) in source and a high band gap material (GaAs) in drain-channel junctions enhances the probability of band-to-band-tunneling (BTBT) of charge carriers. Further, to introduce biomolecules, a cavity is impinged below HfZrO2 near SiO2 above source/channel junction that modulates BTBT as a function of charge density (Nf) and dielectric constant (K). This paper presents a detailed comparative analysis of Ge/GaAs-NCTFET and Ge/GaAs-TFET biosensors for different K and Nf values from which we can conclude that the incorporation of NC effect in TFET biosensors leads to enhanced sensitivity with high speed and low power consumption.

Polarization Gradient Effect of Negative Capacitance LTFET.

In this paper, an L-shaped tunneling field effect transistor (LTFET) with ferroelectric gate oxide layer (Si: HfO2) is proposed. The electric characteristic of NC-LTFET is analyzed using Synopsys Sentaurus TCAD. Compared with the conventional LTFET, a steeper subthreshold swing (SS = 18.4 mV/dec) of NC-LTFET is obtained by the mechanism of line tunneling at low gate voltage instead of diagonal tunneling, which is caused by the non-uniform voltage across the gate oxide layer. In addition, we report the polarization gradient effect in a negative capacitance TFET for the first time. It is noted that the polarization gradient effect should not be ignored in TFET. When the polarization gradient parameter g grows larger, the dominant tunneling mechanism that affects the SS is the diagonal tunneling. The on-state current (Ion) and SS of NC-LTFET become worse.

Performance Enhancement and Signal Distortion Analysis of Virtually Doped Nanotube Tunnel FET with Embedded Ferroelectric Gate Oxide

This paper demonstrates the effect of ferroelectric gate oxide on the electrostatic doped nanotube tunnel field-effect transistor (FE-ED-NTTFET). The proposed device is a dopingless device, and the electrostatic doped method is used for the operation of the device. For electrostatic doped operation, the operating source voltage (VS) for the proposed device is −1.2 V. The intrinsic doping is used throughout the device. The thin ferroelectric material with a width of 2 nm is used as the gate oxide, to improve the performance of the proposed FE-ED-NTTFET device. For the detailed investigation of the proposed FE-ED-NTTFET device, the following parameters are taken into consideration such as device parameters, analogue parameters, and linearity parameters. In device parameters, energy band diagram, quasi Fermi-level of electron and hole, electron/hole mobility, electric filed, non-local tunneling (BTBT), and hole/electron concentration are taken into consideration. In analogue parameters ON current, OFF current, ION/IOFF current ratio, threshold voltage, and sub-threshold swings are considered. For small-signal analysis linearity parameters such as TGF, cut-off frequencies, HD2, HD3, VIP2, VIP3, IIP3, and IMD3 have been discussed. The proposed FE-ED-NTTFET device shows the higher ON current (ION) 6.24uA, lower OFF current (IOFF) order of 10−17 A, higher ION/IOFF current ratio 1*1012, and better sub-threshold swing (SS) 12 mV/decade for gate voltage (VGS) 1.2 V.

Effect of Curie Temperature on Ferroelectric Tunnel FET and Its RF/Analog Performance.

In this article, a numerical simulation study for the ferroelectric gate oxide tunnel field-effect transistor (Ferro-TFET) has been presented. The performance of the device is analyzed following Landau's theory and its behavior in the temperature range of 200-300 K. A minimum subthreshold swing and maximum transconductance is obtained around the Curie temperature ( TC ) of 580 ± 10 K for the simulated device. The simulation result is supported by the simple analytical model. The temperature sensitivity analysis is studied on different analog and RF figure of merits for Ferro-TFET. In this study, the Ferro-TFET shows the remarkable result in reducing the detrimental effect of mobility degradation at high gate voltage and performance degradation at high temperatures as compared to conventional TFETs and MOSFET. Therefore, at Curie temperature, the operation of the Ferro-TFET shows the remarkable results for analog and RF applications.

Impact of ferroelectric on the electrical characteristics of silicon–germanium based heterojunction Schottky barrier FET

This work investigates the impact of ferroelectric gate oxide on high-k gate dielectric with low band gap Silicon Germanium ferroelectric Schottky barrier FET (SiGe Fe-SBFET), has been qualitatively simulated. The present research focuses on major improvement over the conventional device in terms of drain current and reduced subthreshold swing and analog performances. The proposed device has been analyzed in terms of numerous device electrostatic parameters such as electric field and energy band diagram using a ferroelectric material. A novel approach of SiGe-Fe-SBFET provides an effective technique helps to increase the performance in terms of on-current and off-state current of the device. The SiGe-Fe-SBFET also provides high Ion/Ioff ratio of 4.188 × 1012 and low Subthreshold swing of 67 mV/dec in comparison with germanium (Ge) and silicon (Si) material based ferroelectric SBFET. Apart from this, the increasing of tunneling width for the drive of carriers in the drain-channel junction, which results in a reduction of ambipolar conduction in off-state with gate drain underlap. Further, the analog performances of proposed and conventional device are evaluated such as transconductance, intrinsic gate delay, output conductance and cut-frequency which is dependent of parasitic gate capacitances are also investigated through a 2D Silvaco Atlas simulator.

On the Characterization and Separation of Trapping and Ferroelectric Behavior in HfZrO FET

$N$ -channel FETs with ferroelectric (FE) HfZrO gate oxide are fabricated, showing steep subthreshold slope under certain conditions. Possible origins of ${I} _{D}$ – ${V} _{G}$ hysteresis, the hysteresis versus subthreshold slope tradeoff, dependence on the bias voltage and temperature and the competition between trapping and FE behavior are reported and discussed. A band of active traps in the FE layer responsible for charge trapping during device operation is characterized. Transient ${I} _{D}$ – ${V} _{G}$ measurements are introduced to facilitate differentiating between trapping and FE behavior during subthreshold slope measurements.

Ferro-electric stacked gate oxide heterojunction electro-statically doped source/drain double-gate tunnel field effect transistors: A superior structure

The effect of ferro-electric (Fe) gate oxide on heterojunction and band-gap engineering based electro-statically doped source/drain (EDSD) double-gate Tunnel Field Effect Transistors (DG-TFETs), has been studied through 2-D TCAD device simulation. The combined effects of ferroelectric gate stack oxide and the hetero-junction, with low band gap material at source side and high band gap material in rest of the device helps to improve the performance of TFETs. The comparison of various low band gap source region materials shows that Hetrojunction Si-Ge EDSD Fe-DGTFET gives highest on-off current ratio of approx. 1013 and approximately 3mV/dec subthreshold swing. Further, comparison of different hetro-structures is done on the basis of analog characteristics and shows that Hetrojunction Si-Ge EDSD Fe-DGTFET gives lowest intrinsic delay of 1.576×10−11s, thus improving device speed. Moreover, some other analog parameters like gate to source capacitance, gate to drain capacitance, total capacitance, and transconductance and unity gain frequency are also studied to give an idea about improvement in device characteristics

Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics

We study the effects of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs (NCFETs). Based on this, we propose the concept of conservative design of NCFETs, where any unintentional yet reasonable and simultaneous variation ( $\sim \pm 3$ %) in ferroelectric parameters does not result in the emergence of hysteresis and causes only a reasonable variation in the ON-current (≤5%) and, within these constraints, the enhancement of ON-current due to the addition of the ferroelectric gate oxide, which is is maximized.

Effects of Electrostatically Doped Source/Drain and Ferroelectric Gate Oxide on Subthreshold Swing and Impact Ionization Rate of Strained-Si-on-Insulator Tunnel Field-Effect Transistors

This letter reports an electrostatically doped source/drain (EDSD) ferroelectric strained-Si-on-insulator (Fe-SSOI) tunnel field-effect transistor (TFET) with the subthreshold swing (SS) as low as 10 mV/dec for sub-30 nm applications. The proposed device, named as EDSD Fe-SSOI TFET in this report, uses two metal electrodes of Pt and Hf placed at the two sides of the gate on a thin intrinsic (dopingless) strained-Si layer to convert the undoped strained-Si regions below the Pt and Hf electrodes into the respective p+ source and n + drain regions (by plasma charge phenomenon) of the TFET using the ferroelectric stacked gate oxides. While the plasma charge concept provides the abrupt source (drain)–channel junction by avoiding dopant migration from the source (drain) to channel, the intrinsic channel makes the proposed TFET device free from the random dopant fluctuation-related problems. The combined effects of the ferroelectric stacked gate oxides and the strain in intrinsic-Si channel of the proposed TFET structure are observed to result in a significant improvement in the SS as well as the drain current of the proposed EDSD Fe-SSOI TFET under consideration.

Silicon-on-Ferroelectric Insulator field effect transistor (SOFFET): Partially depleted structure for sub-60 mV/decade applications

This paper presents the concept of a new field effect transistor (FET) named a Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). Our design proposes to utilize the negative capacitance (NC) of ferroelectric material in a partially depleted silicon-on-insulator (PD-SOI) device structure. We suggest to substitute the buried insulator oxide (SiO2) inside the SOI substrate with a ferroelectric material, which converts it to the Silicon-on-Ferroelectric Insulator (SOF) substrate. The proposed integration of a ferroelectric material into the body of the MOSFET device will provide the required NC effect to overcome the fundamental thermionic barrier of the current and emerging FETs. This new SOFFET device would provide enhanced device gain, speed and channel conduction. A theoretical model is developed to validate the concept of the new device, which can lower the subthreshold swing (S) below the theoretical minimum S=60mV/decade that is imposed by the thermodynamic limit (kT/q) of the FET devices. Analytical models have been derived to show that the subthreshold swing and the threshold voltage of the proposed device depend on the thicknesses of ferroelectric insulator and gate oxide, and the doping profile of the silicon body. It has been demonstrated that by carefully optimizing different geometric and electrical parameters the proposed PD-SOFFET can provide S value significantly below 60mV/decade.

Theoretical studies of the capacitance‐voltage characteristics of metal‐ferroelectric‐GaN structures

SUMMARYWe have simulated the capacitance versus voltage characteristics (C‐V) of metal‐ferroelectric‐gallium nitride (GaN metal‐ferroelectric‐semiconductor) structures and found useful design rules for improving the devices' performance. The thickness effects of ferroelectric film on the C‐V are studied. When the ferroelectric Pb(Zr, Ti)O3 thickness is no more than 100 nm, the GaN metal‐ferroelectric‐semiconductor structures can approach inversion just under 5 V, which is the generally applied voltage used in semiconductor‐based integrated circuits. This marked improvement of C‐V behaviors is mainly due to the high dielectric constant and large polarization of the ferroelectric gate oxide. Copyright © 2011 John Wiley &amp; Sons, Ltd.

Effect of ZnO channel thickness on the device behaviour of nonvolatile memory thin film transistors with double-layered gate insulators of Al2O3 and ferroelectric polymer

Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF–TrFE) (80 nm)/Al2O3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of −10 to 12 V, and 107 on/off ratio, and a gate leakage current of 10−11 A.

Improvement of electrical properties of ferroelectric gate oxide structure by using Al 2O 3 thin films as buffer insulator

SrBi 2Nb 2O 9 (SBN) and Al 2O 3 thin films were prepared by r.f.-sputtering as a ferroelectric material and as a buffer insulator for metal/ferroelectric/insulator/semiconductor (MFIS) structure, respectively. The electrical properties of those films on Si substrate were studied. Coercive field that decisively affects the memory window was greatly increased by inserting an Al 2O 3 insulator between SBN and Si, and thus the memory window also increased with the increasing electric field to the SBN. The Al 2O 3 intermediate layer between the perovskite SBN film and Si substrate prevent SBN from the serious inter-diffusion into Si substrate. Memory windows of MFIS structure were in the range of 0.7–3.4 V when the gate voltage varied from 3 to 9 V. Memory windows of MFIS structure were found to be dependent on the thickness and stoichiometry of the buffer layer. We obtained the maximum memory window in the MFIS structure with an optimized insulator thickness of 11.4 nm.

Growth and characterization of Al2O3 thin films for the buffer insulator in Pt/SrBi2Nb2O9/Al2O3/Si ferroelectric gate oxide structure

Pt/SrBi2Nb2O9 (SBN)/Al2O3/Si (MFIS) ferroelectric gate oxide structures were prepared with the rf (radio frequency) magnetron sputtering method for the application of non-destructive read-out ferroelectric RAM (NDRO-FRAM) devices. An Al2O3 intermediate layer between the perovskite SrBi2Nb2O9 film and Si substrate prevents the serious inter-diffusion of the SrBi2Nb2O9 (SBN) into the Si substrate. The coercive field that decisively affects the memory window was increased by inserting the Al2O3 insulator between the SBN and Si, and thus the memory window also increased with the increase in the electric field to the SBN. The memory windows of the metal-ferroelectric-insulator-semiconductors (MFIS) structures were in the range of 0.7–3.4 V when the gate voltage varied from 3 to 9 V. The memory windows of the MFIS structures were found to be dependent on the thickness and stoichiometry of the buffer layer. We obtained the maximum memory window in an MFIS with an insulator of 11.4 nm in thickness deposited in the deposition condition of a 15∶5 flow ratio (Ar:O2) during sputtering.

The effect of ZrO 2 buffer layer on electrical properties in Pt/SrBi 2Ta 2O 9/ZrO 2/Si ferroelectric gate oxide structure

We have investigated metal/ferroelectric/insulator/semiconductor (MFIS) structure with strontium bismuth tantalate (SBT) as ferroelectric thin film and ZrO 2 as the insulating buffer layer. Sr 0.8Bi 2.4Ta 2O 9 thin films were prepared by metal organic deposition (MOD) method and ZrO 2 films were deposited by r.f.-sputtering. Coercive field that decisively affects the memory window was increased greatly by inserting the ZrO 2 insulator between SBT and SiO 2 and, thus, the memory window also increases with an electric field to the SBT. Memory windows of MFIS structure were in the range of 0.3–2.6 V when the gate voltage varied from 3 to 10 V. Memory windows of MFIS structure were found to be dependent on the thickness of the buffer layer. We observed the maximum memory window in MFIS with a 28-nm thickness of ZrO 2 layer. Auger electron spectroscopy (AES) depth profile and high resolution transmission electron microscopy (HRTEM) of SBT/ZrO 2 (28 nm)/Si structure showed that the ZrO 2 thin films as a buffer layer helped to prevent the formation of interfacial layer and interdiffusion between SBT and Si.

Fabrication and Characterization of Metalferroelectric-GAN Structures

GaN-based metal-ferroelectric-semiconductor (MFS) structure has been fabricated by using ferroelectric Pb(Zr0.53Ti0.47)O3 (PZT) instead of conventional oxides as gate insulators. The GaN and PZT films in the MFS structures have been characterized by various methods such as photoluminescence (PL), wide-angle X-ray diffraction (XRD) and high-resolution X-ray diffraction (HRXRD). The Electric properties of GaN MFS structure with different oxide thickness have been characterized by high-frequency C-V measurement. When the PZT films are as thick as 1 μm, the GaN active layers can approach inversion under the bias of 15V, which can not be observed in the traditional GaN MOS structures. When the PZT films are about 100 nm, the MFS structures can approach inversion just under 5V. All the marked improvements of C-V behaviors in GaN MFS structures are mainly attributed to the high dielectric constant and large polarization of the ferroelectric gate oxide.