Ferroelectric Field-effect Transistors Research Articles

Photoelectric synapses based on all-two-dimensional ferroelectric semiconductor heterojunction

Abstract Photoelectric synapses are attaching intensive attention due to its low power consumption and adaptive learning. However, traditional ferroelectric field effect transistors are not conducive to the integrated application in artificial intelligence systems. Here, we design the all two-dimensional photoelectric synapse device based on WSe2/MoS2/α-In2Se3 ferroelectric van der Waals heterojunction, which has high memory capacity (memory on/off = 105) and synaptic function. In addition, we simulate an artificial neural network to modify the handwritten digit recognition of the National Institute of Standards and Technology. In particular, the recognition rates are 92.4% and 93.6% for electrical synapse and photoelectric synapse, respectively. This work provides an effective strategy for achieving stable integration of neuromorphic computing.

(Invited) Ferroelectric Nonvolatile Capacitive Synapse for Charge Domain Compute-in-Memory

The ferroelectric field effect transistor (FeFET) can be configured in nvCAP mode to enable a small-signal capacitive readout. Operating the FeFET in nvCAP mode for Charge-domain Compute-in-Memory provides benefits such as reduced power consumption and suppressed read disturb. In this review article, working of FeFET in nvCAP mode is described. Further, the TCAD study results are summarized to optimize the FeFET structure for maximizing the device performance in nvCAP mode, where the gate area and the overlap region decides the ON and OFF state capacitance. Next, the reliability aspects of nvCAP are discussed. The FeFET in nvCAP demonstrates an initial endurance of 106 P/E cycles, which can be further extended by 100× by performing a recovery operation. The nvCAP device shows a retention of at least 1 day at 850C for the fresh, fatigued and recovered state of the device, making it a suitable candidate for Compute-in-Memory.

TCAD simulation study of dual ferroelectric gate field-effect transistors with a recessed channel geometry for non-volatile memory applications

TCAD simulation study of dual ferroelectric gate field-effect transistors with a recessed channel geometry for non-volatile memory applications

Low-Temperature Nanosecond Laser Process of HZO-IGZO FeFETs toward Monolithic 3D System on Chip Integration.

Ferroelectric field-effect transistors (FeFETs) are increasingly important for in-memory computing and monolithic 3D (M3D) integration in system-on-chip (SoC) applications. However, the high-temperature processing required by most ferroelectric memories can lead to thermal damage to the underlying device layers, which poses significant physical limitations for 3D integration processes. To solve this problem, the study proposes using a nanosecond pulsed laser for selective annealing of hafnia-based FeFETs, enabling precise control of heat penetration depth within thin films. Sufficient thermal energy is delivered to the IGZO oxide channel and HZO ferroelectric gate oxide without causing thermal damage to the bottom layer, which has a low transition temperature (<250 °C). Using optimized laser conditions, a fast response time (<1 µs) and excellent stability (cycle >106, retention >106 s) are achieved in the ferroelectric HZO film. The resulting FeFET exhibited a wide memory window (>1.7V) with a high on/off ratio (>105). In addition, moderate ferroelectric properties (2·Pr of 14.7 µCcm-2) and pattern recognition rate-based linearity (potentiation: 1.13, depression: 1.6) are obtained. These results demonstrate compatibility in HZO FeFETs by specific laser annealing control and thin-film layer design for various structures (3D integrated, flexible) with neuromorphic applications.

Applying the Wake-Up-like Effect to Enhance the Capabilities of Two-Dimensional Ferroelectric Field-Effect Transistors.

For traditional ferroelectric field-effect transistors (FeFETs), enhancing the polarization domain of bulk ferroelectric materials is essential to improve device performance. However, there has been limited investigation into the enhancement of polarization field in two-dimensional (2D) ferroelectric material such as CuInP2S6 (CIPS). In this study, similar to bulk ferroelectric materials, CIPS exhibited enhanced polarization field upon application of external cyclic voltage. Moreover, unlike traditional ferroelectric materials, the polarization enhancement of CIPS is not due to redistribution of the defect but rather originates from a mechanism: the long-distance migration of Cu ions. We termed this mechanism the "wake-up-like effect". After incorporating the wake-up-like effect into the graphene/CIPS/WSe2 FeFET device, we successfully increased the hysteresis window and enhanced the current on/off ratio by 4 orders of magnitude. Moreover, the FeFET yielded remarkable achievements, such as multilevel nonvolatile memory with 21 distinct conductance levels, a high on/off ratio exceeding 106, a long retention time exceeding 103 s, and neuromorphic computing with 93% accuracy at recognizing handwritten digits. Introducing the wake-up-like effect to 2D CIPS may pave the way for innovative approaches to achieve advanced multilevel nonvolatile memory and neuromorphic computing capabilities for next-generation micro-nanoelectronic devices.

Atomic-level polarization reversal in sliding ferroelectric semiconductors

Intriguing “slidetronics” has been reported in van der Waals (vdW) layered non-centrosymmetric materials and newly-emerging artificially-tuned twisted moiré superlattices, but correlative experiments that spatially track the interlayer sliding dynamics at atomic-level remain elusive. Here, we address the decisive challenge to in-situ trace the atomic-level interlayer sliding and the induced polarization reversal in vdW-layered yttrium-doped γ-InSe, step by step and atom by atom. We directly observe the real-time interlayer sliding by a 1/3-unit cell along the armchair direction, corresponding to vertical polarization reversal. The sliding driven only by low energetic electron-beam illumination suggests rather low switching barriers. Additionally, we propose a new sliding mechanism that supports the observed reversal pathway, i.e., two bilayer units slide towards each other simultaneously. Our insights into the polarization reversal via the atomic-scale interlayer sliding provide a momentous initial progress for the ongoing and future research on sliding ferroelectrics towards non-volatile storages or ferroelectric field-effect transistors.

Energy efficient artificial gustatory system for in-sensor computing

In this work, a novel bio-inspired artificial gustatory system is proposed for in-sensor neuromorphic computing. The system is demonstrated using a novel material-engineered compound-semiconductor double-gate ferroelectric tunnel FET. The behaviour of the device as a biosensor and as a spiking neuron is verified individually. Using extensive simulation in Atlas TCAD, the biosensor functionality is validated with ION sensitivity of 108. Likewise, the device shows excellent neuronal behaviour with energy consumption of 37 aJ/spike, without using any external circuitry. It also exhibits control over the spiking frequency through amplitude, frequency, and duty cycle of input synaptic current. By cascading the biosensor and neuron, a complete bio-mimicked gustatory system is designed to identify a separate pattern for different tastes. The proposed gustatory system integrates both the devices, and simultaneously performs sensing and spike encoding. The biosensor transduces the pH and dielectric constant of the target biomolecule, corresponding to gustatory neurons present in the taste buds of a biological gustatory system. The neuron performs spike encoding and acts as an input neuron in a classifying network, which corresponds to gustatory cortex of its biological counterpart. The system consumes an average power of 49.58 pW which is ∼1000 × lesser than the state-of-the-art artificial gustatory system, eliminating the need for complex hardware and exorbitant energy consumption. Therefore, the proposed gustatory system provides a highly efficient and compact solution for neuromorphic gustatory sensing and classification, with potential applications in portable, wearable, and implantable devices.

A design methodology for highly reliable operation for 2T0C DRAM application based on IGZO CAA FeFETs

Abstract In this paper, the memory characteristics of In-Ga-Zn-O (IGZO)-channel ferroelectric FETs (FeFETs) with stackable vertical Channel-All-Around (CAA) structure are investigated by technology computer-aided design (TCAD) simulation. The simulated IDS~VGS curves of IGZO FeFET exists a large on-off ratio of 107 and memory window, proving that ferroelectric hafnium oxide is satisfied for 2T0C transistor design. To solve the potential current sharing problem of 2T0C dynamic random access memory (DRAM) array, an advanced operation design methodology is proposed, which utilizes the bipolar polarization characteristics of ferroelectric hafnium oxide. This solution shows the remarkable current ratio between data “1” and data “0”, not only demonstrating the feasibility of IGZO-based FeFET on 2T0C DRAM memory cell, but also providing array design guideline for highly reliable 2T0C memory applications.

Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads

This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate machine learning (ML) workloads. We conducted an exploration of device fabrication and proposed system-algorithm co-design to boost performance. A novel FeCap device, incorporating an interfacial layer (IL) and Hf0.5Zr0.5O2\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ ext {Hf}_{0.5}\ ext {Zr}_{0.5}\ ext {O}_2$$\\end{document} (HZO), ensures a reduction in operating voltage and enhances HZO scaling while being compatible with CMOS circuits. The IL also enriches ferroelectricity and retention properties. When integrated into crossbar arrays, FeCaps and FeFETs demonstrate their effectiveness as IMC components, eliminating sneak paths and enabling selector-less operation, leading to notable improvements in energy efficiency and area utilization. However, it is worth noting that limited capacitance ratios in FeCaps introduced errors in multiply-and-accumulate (MAC) computations. The proposed co-design approach helps in mitigating these errors and achieves high accuracy in classifying the CIFAR-10 dataset, elevating it from a baseline of 10% to 81.7%. FeFETs in crossbars, with a higher on-off ratio, outperform FeCaps, and our proposed charge-based sensing scheme achieved at least an order of magnitude reduction in power consumption, compared to prevalent current-based methods.

Pure ZrO2 Ferroelectric Thin Film for Nonvolatile Memory and Neural Network Computing.

The recent discovery of ferroelectricity in pure ZrO2 has drawn much attention, but the information storage and processing performances of ferroelectric ZrO2-based nonvolatile devices remain open for further exploration. Here, a ZrO2 (∼8 nm)-based ferroelectric capacitor using RuO2 oxide electrodes is fabricated, and the ferroelectric orthorhombic phase evolution under electric field cycling is studied. A ferroelectric remnant polarization (2Pr) of >30 μC/cm2, leakage current density of ∼2.79 × 10-8 A/cm2 at 1 MV/cm, and estimated polarization retention of >10 years are achieved. When the ferroelectric capacitor is connected with a transistor, a memory window of ∼0.8 V and eight distinct states can be obtained in such a ferroelectric field-effect transistor (FeFET). Through the conductance manipulation of the FeFET, a high object image recognition accuracy of ∼93.32% is achieved on the basis of the CIFAR-10 dataset in the convolutional neural network (CNN) simulation, which is close to the result of ∼94.20% obtained by floating-point-based CNN software. These results demonstrate the potential of ferroelectric ZrO2 devices for nonvolatile memory and artificial neural network computing.

Transistors with ferroelectric ZrXAl1−XOY crystallized by ZnO growth for multi-level memory and neuromorphic computing

Ferroelectric (FE) field-effect transistors are interesting for their non-destructive readout characteristic and energy efficiency but are difficult to integrate on silicon platforms. Here, FE ZrXAl1−XOY (ZAO) is demonstrated by compressive strain in contact with ZnO. The metal-ferroelectric-semiconductor-metal capacitor exhibits a substantial remnant polarization of 15.2 µC cm−2, along with a bowknot-like anti-clockwise hysteresis in the capacitance curves. The FE-ZAO gated ZnO thin-film transistor presents a large memory window (3.84 V), low subthreshold swing (55 mV dec−1), high ION/IOFF ratio (≈108), and low off-state current (≈1 pA). The grazing incidence X-ray diffraction and scanning transmission electron microscopy analyses reveal the ferroelectric rhombohedral phase (space group R3m) in the nanocrystal ZAO, containing an angle of ≈71.7° between the [111] and [11-1] directions with d111-spacing of 3.037 Å and d11-1-spacing of 2.927 Å. Finally, the memory and neuromorphic applications are analyzed by demonstrating multi-level memory and synaptic weight performance with a high learning accuracy of 91.82%.

Non-volatile memory characteristics of flexible ferroelectric field-effect transistors consisting of Sm-doped BiFeO3 thin films

This study investigates the impact of Sm doping on the structural, electrical, and functional properties of BiFeO3 (BFO) thin films. The aim is to improve their non-volatile memory characteristics for use in flexible ferroelectric field-effect transistors (FeFETs). We fabricated Sm-doped BFO (SBFO) thin films on flexible mica substrates with Sm concentrations ranging from 0 to 15 %. The FeFET device structures, which include MoS2 monolayer channels and SBFO thin films with Pt bottom electrodes, were analyzed. The SBFO thin films displayed a (111) preferential orientation due to the influence of underlying Pt electrodes. Notably, the SBFO thin film doped with a 10 % Sm concentration showed optimal enhancements, including a reduction in leakage current density and an increase in remanent polarization to 55.8 μC/cm2, compared to undoped thin film (35.5 μC/cm2). Furthermore, the thin film exhibited superior fatigue resistance for up to 1012 switching cycles and maintained stable values under significant bending stress for ferroelectric polarizations. On the other hand, SBFO thin film with 15 % Sm doping displayed relaxor antiferroelectric behavior, highlighting the importance of doping concentration. Therefore, for non-volatile memory application reliability, the FeFET device featuring a 10 % Sm-doped SBFO thin film not only enhanced the memory window but also showed superior fatigue characteristics over 1012 switching cycles, compared to its undoped counterpart. These findings demonstrate the effect of Sm doping in customizing the properties of BFO thin films for advanced, flexible non-volatile memory devices, offering a novel insight to optimize ferroelectric field-effect transistor performance.

Logic-in-memory application of ferroelectric-based WS2-channel field-effect transistors for improved area and energy efficiency

In this study, we applied ferroelectrics to the gate stack of Field Effect Transistors (FETs) with a 2D transition-metal dichalcogenide (TMDC) channel, actively researching for sub-2nm technology node implementation. Subsequently, we analyzed the circuit characteristics of Logic-in-Memory (LiM) operation and utilized LiM features after applying ferroelectrics to achieve a single-device configuration. Based on well-calibrated simulations, we performed compact modeling in a circuit simulator to depict the temperature-dependent electrical characteristics of ferroelectric FETs with a double gate structure and 2D channel (DG 2D-FeFET) in sub-2nm dimensions. Through this, we have confirmed that the 2D FeFET-based LiM technology, designed for the 2 nm technology node, exhibits superior characteristics in terms of delay, power/energy consumption, and circuit area under all temperature conditions, compared to the conventional CMOS technology based on 2D FETs. This verification serves as proof of the future technological potential of 2D-FeFET in extremely scaled-down technology nodes.

Analysis of the Role of Interfacial Layer in Ferroelectric FET Failure as a Memory Cell

Analysis of the Role of Interfacial Layer in Ferroelectric FET Failure as a Memory Cell

Demonstration of bias scheme for ferroelectric field-effect transistor (FeFET) based AND array operation

In this study, we experimentally demonstrated a simplified write inhibition bias scheme for a ferroelectric field-effect transistor (FeFET) based AND array, which is the promising energy- and area-efficient memory. The write inhibition scheme that only employs the bit line (BL) voltages was optimized through the single cell FeFET measurements. The program and erase operations were confirmed to be apparently inhibited with the BL/source line (SL) voltages of 3.5 V/0 V, respectively. The suggested inhibition bias scheme was then applied to the 16 × 16 FeFET AND array for demonstrating its validity. It was clearly verified that selective program/erase operations were possible without modulating the SL voltages, suggesting its benefits in terms of area-efficiency.

Multi-level storage in cleaved-gate ferroelectric FETs investigated by 3D phase-field-based quantum transport simulation

In this work, we investigate the feasibility of cleaved-gate ferroelectric FET (CG-FeFET) as multi-level cell (MLC) memory devices, by conducting 3-dimensional quantum transport simulations based on time-dependent-Ginzburg–Landau equation, and the non-equilibrium Green’s function method. Our results indicate that CG-FeFET can achieve multi-level operations by utilizing different thicknesses of the ferroelectric layer. We analyze the influence of electron–phonon interaction and also verify that CG-FeFET is robust to noise. Furthermore, we identify the critical role of the spacing between two ferroelectric layers in determining the memory window, considering the effects of polarization cancellation and electrostatic coupling. These findings provide valuable insights into designing stable and reliable nonvolatile memory technologies, which could offer potential solutions for high-density memory requirements.

Understanding Quasi-Static and Dynamic Characteristics of Organic Ferroelectric Field Effect Transistors.

Leveraging poly(vinylidene fluoride-trifluoroethylene) [(PVDF-TrFE)] as the dielectric, we fabricated organic ferroelectric field-effect transistors (OFe-FETs). These devices demonstrate quasi-static transfer characteristics that include a hysteresis window alongside transient phenomena that bear resemblance to synaptic plasticity-encapsulating excitatory postsynaptic current (EPSC) as well as both short-term and long-term potentiation (STP/LTP). We also explore and elucidate other aspects such as the subthreshold swing and the hysteresis window under dynamic state by varying the pace of voltage sweeps. In addition, we developed an analytical model that describes the electrical properties of OFe-FETs, which melds an empirical formula for ferroelectric polarization with a compact model. This model agrees well with the experimental data concerning quasi-static transfer characteristics, potentially serving as a quantitative tool to improve the understanding and design of OFe-FETs.

High-performance ferroelectric field-effect transistors with ultra-thin indium tin oxide channels for flexible and transparent electronics

With the development of wearable devices and hafnium-based ferroelectrics (FE), there is an increasing demand for high-performance flexible ferroelectric memories. However, developing ferroelectric memories that simultaneously exhibit good flexibility and significant performance has proven challenging. Here, we developed a high-performance flexible field-effect transistor (FeFET) device with a thermal budget of less than 400 °C by integrating Zr-doped HfO2 (HZO) and ultra-thin indium tin oxide (ITO). The proposed FeFET has a large memory window (MW) of 2.78 V, a high current on/off ratio (ION/IOFF) of over 108, and high endurance up to 2×107 cycles. In addition, the FeFETs under different bending conditions exhibit excellent neuromorphic properties. The device exhibits excellent bending reliability over 5×105 pulse cycles at a bending radius of 5 mm. The efficient integration of hafnium-based ferroelectric materials with promising ultrathin channel materials (ITO) offers unique opportunities to enable high-performance back-end-of-line (BEOL) compatible wearable FeFETs for edge intelligence applications.

Deep insights into the mechanism of nitrogen on the endurance enhancement in ferroelectric field effect transistors: Trap behavior during memory window degradation

The nitridation process can significantly improve the quality of the interfacial layer and suppress the unrecoverable electron trapping of the interfacial states during cycling, which is the main cause of endurance enhancement. In this work, through in-depth analysis of defect behavior during memory window (MW) degradation in ferroelectric field effect transistors (FeFETs), it is found that the degradation of FeFET devices with SiON interfacial layer starts within the HZO layer, while the degradation process of FeFET devices with SiO2 interlayer initially begins at the interlayer and then penetrates into the HZO layer. First, the MW degradation processes of nitridation/non-nitridation devices are measured and compared. Moreover, through the extended measure-stress-measure method, three types of defects are defined and the defect behaviors including trapping kinetics and energy locations during degradation are systematically investigated. The mechanism of nitrogen on the endurance enhancement is finally revealed. These results are valuable to better understand the reliability issues of FeFET and pave the way for future process optimization.

Toward Optimized In‐Memory Reinforcement Learning: Leveraging 1/f Noise of Synaptic Ferroelectric Field‐Effect‐Transistors for Efficient Exploration

Reinforcement learning (RL), exhibiting outstanding performance in various fields, requires large amounts of data for high performance. While exploration techniques address this requirement, conventional exploration methods have limitations: complexity of hardware implementation and significant hardware burden. Herein, in‐memory RL systems leveraging intrinsic 1/f noise of synaptic ferroelectric field‐effect‐transistors (FeFETs) for efficient exploration are proposed. The electrical characteristics of fabricated FeFETs with low‐power operation capability verify their suitability for neuromorphic systems. The proposed system achieves comparable performance to the conventional exploration method without additional circuits. The intrinsic 1/f noise of the FeFETs facilitates efficient exploration and offers significant advantages: efficiency in hardware implementation and simplicity in adjusting the 1/f noise level for optimal performance. This approach effectively addresses the challenges of conventional exploration methods. The operation mechanism of the exploration method utilizing the 1/f noise is systematically analyzed. The proposed in‐memory RL system demonstrates robustness and reliability to the device‐to‐device variation and the initial conductance distribution. This work provides further insights into the exploration methods of RL, paving the way for advanced in‐memory RL systems.