Feedback Shift Register Research Articles

Public Authentic-Replica Sampling Mechanism in Distributed Storage Environments

With the rapid development of wireless communication and big data analysis technologies, the storage of massive amounts of data relies on third-party trusted storage, such as cloud storage. However, once data are stored on third-party servers, data owners lose physical control over their data, making it challenging to ensure data integrity and security. To address this issue, researchers have proposed integrity auditing mechanisms that allow for the auditing of data integrity on cloud servers without retrieving all the data. To further enhance the availability of data stored on cloud servers, multiple replicas of the original data are stored on the server. However, in existing multi-replica auditing schemes, there is a problem of server fraud, where the server does not actually store the corresponding data replicas. To tackle this issue, this paper presents a formal definition of authentic replicas along with a security model for the authentic-replica sampling mechanism. Based on time-lock puzzles, identity-based encryption (IBE) mechanisms, and succinct proof techniques, we design an authentic replica auditing mechanism. This mechanism ensures the authenticity of replicas and can resist outsourcing attacks and generation attacks. Additionally, our schemes replace the combination of random numbers and replica correspondence tables with Linear Feedback Shift Registers (LFSRs), optimizing the original client-side generation and uploading of replica parameters from being linearly related to the number of replicas to a constant level. Furthermore, our schemes allow for the public recovery of replica parameters, enabling any third party to verify the replicas through these parameters. As a result, the schemes achieve public verifiability and meet the efficiency requirements for authentic-replica sampling in multi-cloud environments. This makes our scheme more suitable for distributed storage environments. The experiments show that our scheme makes the time for generating copy parameters negligible while also greatly optimizing the time required for replica generation. As the amount of replica data increases, the time spent does not grow linearly. Due to the multi-party aggregation design, the verification time is also optimal. Compared to the latest schemes, the verification time is reduced by approximately 30%.

A lightweight dual-link accelerated authentication protocol based on NLFSR-XOR APUF

Physical Unclonable Function (PUF) circuits, as a lightweight hardware security primitive, can provide reliable authentication for resource-constrained Internet of Things (IoT) devices. However, in real-time environments and systems, authentication of embedded devices has strict requirements on resources and low latency. Therefore, this paper proposes a lightweight dual-link accelerated authentication protocol design based on NLFSR-XOR APUF, through the study of Non-Linear Feedback Shift Registers (NLFSR) and XOR APUF circuits. First, the scheme utilizes the symmetric path delay deviation characteristics of APUF and the complexity of NLFSR state transitions to form a nonlinear output function that changes with the challenge signal. Then, a lightweight and attack-resistant authentication protocol is established by combining the random probability of shuffling array bits with the XOR confusion mechanism. Finally, the advantages of GPU parallel computing and AES T-table reconfiguration scheme are used to achieve an accelerated and side-channel attack-resistant authentication protocol. Experimental results show that the PUF circuit can effectively resist various modeling attacks, including logistic regression (LR), artificial neural network (ANN), and support vector machine (SVM). The security of the protocol has been formally verified, and the prototype has been implemented on the Xilinx xc100T development board, effectively resisting deception attacks, physical attacks, and modeling attacks. The protocol's area overhead in terms of LUT and encryption time is reduced by 58.6 % and 67.8 %, respectively, compared to similar protocols.

Nonsingularity of grain-like cascade feedback shift registers subject to fault attacks

Nonsingularity of grain-like cascade feedback shift registers subject to fault attacks

Block Cipher Nonlinear Component Generation via Hybrid Pseudo-Random Binary Sequence for Image Encryption

To analyze the security of encryption, an effectual encryption scheme based on colored images utilizing the hybrid pseudo-random binary sequence (HPRBS) and substitution boxes, known as S-boxes, is proposed. The presented work aims to design S-boxes using pseudo-random binary numbers acquired by Linear Feedback Shift Registers (LFSRs) in combination with a modified quadratic chaotic map. Firstly, cryptographically robust S-boxes are constructed by using binary pseudo-random number sequences, and then the cryptographic properties of the presented S-boxes are tested. The suggested S-boxes showed good results. Secondly, an RGB image encryption algorithm utilizing sequences generated by modified quadratic chaotic maps and S-boxes is offered. The new color image encryption techniques comprise two steps, including a permutation and a substitution step. The key association with the content of the image is also addressed. This strategy can result in a “one-time pad” effect and make the algorithm resistant to chosen-plaintext attack (CPA). The proposed scheme has been confirmed to be more valuable than most of the existing schemes. S-boxes are analyzed by the nonlinearity test, bit independence criterion (BIC), linear and differential approximation probabilities (LPs; DPs), and Strict-Avalanche Criterion (SAC) tests. A comparison with different S-boxes presented in the literature is also carried out. The comparison shows encouraging results about the quality of the proposed box. From security and experimental outcomes, the effectiveness of the presented color image encryption technique is verified. The proposed scheme has evident efficiency benefits, which implies that the proposed colored encryption of the image scheme has better potential for application in encryption schemes in real-time.

Randomness Generation for Secure Hardware Masking – Unrolled Trivium to the Rescue

Masking is a prominent strategy to protect cryptographic implementations against side-channel analysis. Its popularity arises from the exponential security gains that can be achieved for (approximately) quadratic resource utilization. Many variants of the countermeasure tailored for different optimization goals have been proposed. The common denominator among all of them is the implicit demand for robust and high entropy randomness. Simply assuming that uniformly distributed random bits are available, without taking the cost of their generation into account, leads to a poor understanding of the efficiency vs. security tradeoff of masked implementations. This is especially relevant in case of hardware masking schemes which are known to consume large amounts of random bits per cycle due to parallelism. Currently, there seems to be no consensus on how to most efficiently derive many pseudo-random bits per clock cycle from an initial seed and with properties suitable for masked hardware implementations. In this work, we evaluate a number of building blocks for this purpose and find that hardware-oriented stream ciphers like Trivium and its reduced-security variant Bivium B outperform most competitors when implemented in an unrolled fashion. Unrolled implementations of these primitives enable the flexible generation of many bits per cycle, which is crucial for satisfying the large randomness demands of state-of-the-art masking schemes. According to our analysis, only Linear Feedback Shift Registers (LFSRs), when also unrolled, are capable of producing long non-repetitive sequences of random-looking bits at a higher rate per cycle for the same or lower cost as Trivium and Bivium B. Yet, these instances do not provide black-box security as they generate only linear outputs. We experimentally demonstrate that using multiple output bits from an LFSR in the same masked implementation can violate probing security and even lead to harmful randomness cancellations. Circumventing these problems, and enabling an independent analysis of randomness generation and masking, requires the use of cryptographically stronger primitives like stream ciphers. As a result of our studies, we provide an evidence-based estimate for the cost of securely generating n fresh random bits per cycle. Depending on the desired level of black-box security and operating frequency, this cost can be as low as 20 n to 30 n ASIC gate equivalents (GE) or 3 n to 4 n FPGA look-up tables (LUTs), where n is the number of random bits required. Our results demonstrate that the cost per bit is (sometimes significantly) lower than estimated in previous works, incentivizing parallelism whenever exploitable. This provides further motivation to potentially move low randomness usage from a primary to a secondary design goal in hardware masking research.

Genetic algorithms and deep learning for unique facial landmark-based key generation

Generating secure secret keys remains essential in the realm of biometric authentication systems. Traditional methods have often suffered from inefficiency, insecurity, or the requirement for additional hardware. In this study, an innovative approach to secret key generation is proposed, leveraging deep learning, facial feature extraction, genetic algorithms, and linear feedback shift registers (LFSRs). These techniques are combined to create robust, unique keys based on users' facial features. A convolutional neural network (CNN) is employed for the extraction of facial features from user images and for the optimization of LFSR parameters using a genetic algorithm. Furthermore, another neural network is utilized to establish a connection between facial features and the LFSR-generated output, resulting in the secret key. Rigorous evaluation of the method is conducted across various facial datasets, with a comparison against existing approaches. The results demonstrate the effectiveness of the method, yielding secret key length of 92,706 characterized by an entropy value of 3.24, a low average correlation value of 0.1554, and a high level of security. This research represents a significant advancement in secure biometric authentication, addressing the limitations of conventional key generation methods.

An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

The bose-chaudhuri-hocquenghem (BCH) codes are a cyclic error correction codes (ECC) class. The BCH is constructed by using a polynomial over the Galois field. The BCH codes can detect and correct the multi-bits with an easy decoding mechanism. The BCH codes are used in most of the storage device's cryptography, disk drives, and satellite applications. This manuscript presents an efficient high-throughput BCH module with an encoding and decoding mechanism for multi-bit corrections. The BCH code of (15, k) is used to construct the encoder and decoder architectures. The BCH encoder decoder (ED) module with single error correction (SEC), double error correction (DEC), and triple-error correction (TEC) are discussed in detail. The BCH encoder module uses a linear feedback shift register (LFSR). The BCH decoder with SEC and DEC is constructed using the syndrome generator module (SGM) and chien search module (CSM). The BCH decoder with TEC is designed using SGM, inversion-based berlekamp-massey-algorithm (BMA), and CSMs. The BCH-ED module with SEC, DEC, and TEC utilizes <1 % chip area on Artix-7 FPGA. The BCH-ED with SEC, DEC, and TEC achieves a throughput of 7.13 Gbps, 1.2 Gbps, and 0.803 Gbps, respectively. Lastly, the BCH module is compared with existing BCH approaches with better improvement in chip area, frequency, and throughput parameters.

The security analysis on the rabbit stream cipher

In recent years, stream cipher systems that have been traditionally designed using linear feedback shift register have been almost entirely compromised by algebraic attack methods. Thus, identifying a method to establish concepts for new-generation ciphers, prevent existing security problems, and design new stream cipher systems that consider both security and performance has become a crucial concern in the field of cryptography. In 2004, the European Union initiated the eSTREAM project to emulate the Advanced Encryption Standard used in the United States. The project consisted of 48 participating stream cipher candidates. Through open selection, review, and runoff voting, the results were announced in May 2008. This research investigated one of the finalists of the eSTREAM competition: The Rabbit stream cipher. Additionally, stream cipher attack methods have been extensively studied in recent years, especially those for distinguishing attacks. Thus, contributions of this article is explored the design concepts of the core algorithms in the new-generation stream cipher systems for determining the corresponding mathematical principles and practical approaches to contribute to the study of stream cipher systems.

Design and Analysis of High Performance FinFET-Based Linear Feedback Shift Register for Cryptography Applications

Nowadays, all the elements of our surrounding is occupied by electronics. Electronics occupies major role on our day today life. Electronics device integration on a single chip enhances performance in terms of speed, low-power circuits, and area. Integration of VLSI provides better scalability and reliability. This research paper focused on the implementation of Linear feedback shift registers (LFSR) using FinFET techniques at the layout level for various applications, including cryptography. FinFETs are highlighted as a replacement for CMOS technology, offering advantages such as improved performance in terms of speed, low-power circuits, and area. Linear feedback shift registers are commonly used in digital systems and cryptography for generating pseudo-random sequences. The use of FinFET technology in the layout level suggests an interest in exploring advanced semiconductor technologies to enhance the performance of these circuits. The paper appears to cover different design methods of LFSRs, which could include aspects like circuit optimization, power efficiency, and reliability. The integration of electronics on a single chip, particularly with FinFET technology, is noted for its potential to provide better scalability and reliability. The first architecture is created using bulk CMOS techniques; whereas the second is constructed using two fin FinFET LFSRs. Using the Microwind designing tool, the third technique is developed with a 3-fin FinFET LFSR. It provides a solution for a novel FinFET architecture that implements LFSR. When comparing CMOS and FinFET circuit designs for LFSR, the latter achieves superior performance in terms of area and power efficiency. An analysis is conducted on the design techniques and performance of CMOS LFSR, 2 fin FinFET based LFSR, and 3 fin FinFET. According to the experimental findings, the CMOS-based LFSR uses 1.243 mW of power; the FinFET-based LFSR uses 90.47 μW, and the two fin FinFET LFRS uses 0.254 mW.

Design and Implementation of 32 Bit Linear Feedback Shift Register using FPGA

Abstract: Shift register is a common device for generating signals and sequences. Usually register is the combination of flipflops.The shift register is of two types which are: linear and nonlinear. Various sequences including pseudorandom codes are generated by linear and nonlinear feedback shift registers, respectively. Linear feedback shift register (LFSR) is composed of dynamic or static master-slave flip-flop. Its characteristics are usually characterized by a characteristic polynomial. The twoinput XOR gate is used to calculate the characteristic polynomial of the maximum or near maximum length of the feedback function without rectifying the register.

Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture

Due to the reduction in transistor size, test engineers face a severe issue in power minimization. VLSI circuit's power dissipation has become a vital concern due to the switching activity of the Circuit Under Test (CUT). Switching activity is a significant factor in determining power consumption for CMOS VLSI circuits. In this paper, we formulate a distance estimation technique and reordering using the Tversky index. Here, the distance between the test vectors is calculated using the Tversky index with the formation of an adjacency matrix, and reordering is performed. The experimental results of the proposed method have been compared to different distance measures and existing techniques. It shows that the switching activity is reduced from 52.5% to 21.5%, and the average power reduction is from 42% to 14.6% when the distance is estimated on reordering using the Tversky index measure. Thus, the Tversky index distance measure performs better than the Hamming, gray, and Linear feedback shift register (LFSR) methods. Switching activity estimation for complex ISCAS circuits has been performed and compared with existing methods for superior performance. We have also developed a Built in Self-Test (BIST) for the C17 benchmark circuit, which uses the Tversky counter as a test pattern generator using the TANNER EDA tool. Thus, an efficient deterministic BIST for the C17 benchmark circuit was designed to detect all the stuck-at faults, and the same procedure can be used to create BIST for all CUT and precomputed test sets for real-time field testing.

Design of a New Neuro-Generator with a Neuronal Module to Produce Pseudorandom and Perfectly Pseudorandom Sequences

This paper presents the design of a new neuro-generator of pseudorandom number type PRNG Pseudorandom Number Generator, which produces complex sequences with an adequate bit distribution. The circuit is connected to a neuronal module with six impulse neurons with different behaviors: spike frequency adaptation, phasic spiking, mixed mode, phasic bursting, tonic bursting and tonic spiking. This module aims to generate a non-periodic signal that becomes the clock signal for one of the LFSRs Linear Feedback Shift Register that the neuro-generator has. To verify its correct operation, the neuro-generator was subjected to a series of tests where the frequencies of the impulse neurons were modified. This modification allows the generation of a greater number of pulses at the output of the neuronal module, to obtain sequences with different characteristics that pass different NIST statistical tests (National Institute of Standards and Technology of U.S.). The results show that the new neuro-generator maintains pseudo-randomness in the sequences obtained with different frequencies and it can be implemented on a reconfigurable FPGA Field Programmable Gate Array Virtex 7 xc7vx485t-2ffg1761 device. Therefore, it can be used for applications such as biological systems.

The equivalence between Galois and Fibonacci NFSRs

Nonlinear feedback shift registers (NFSRs) are used in many stream ciphers as their main building blocks. In particular, Galois NFSRs with terminal bits are used in typical stream ciphers Grain and Trivium. Seven types of Galois NFSRs have been found equivalent to Fibonacci ones, among which three types are particular cases of another type of lower triangular Galois NFSRs. This paper continues the research of equivalence between Galois NFSRs and Fibonacci ones. It first enumerates the Galois NFSRs with terminal bits that are equivalent to a Fibonacci NFSR. It then discloses n-stage (n−2)-terminal-bit Galois NFSRs equivalent to Fibonacci ones, must be lower triangular Galois NFSRs. Finally, it presents two new types of Galois NFSRs that are equivalent to Fibonacci NFSRs. Some examples show that, compared to a Fibonacci NFSR, its equivalent Galois NFSR from our new types may decrease the area and increase the throughput of the circuits implementing feedback functions.

A simultaneous area, delay and leakage current reduction method for Linear Feedback Shift Register (LFSR) using pulsed latches and DTMOS transistors

In digital circuits, the shift registers are the significant elements having the ability of storing and transmitting the data in sequential manner.The linear feedback shift register (LFSR) uses large number of flips-flops that consumes maximum amount of power. To overcome this issue, this research work concentrates on the design of LFSR for the area efficient, power reduction, minimization of delay and leakage current. By replacing the d-flip-flop with the bi-enabled pulsed latch to reduce the power consumption and delay of the proposed LFSR design. For the minimization of area, leakage current and delay, the hybrid body bias generator with dynamic threshold MOS (BBG-DTMOS) is used. Moreover, the pulsed clock signal is generated in the digital circuit with the aid of hybrid BBG-DTMOS technique. The proposed LFSR design is implemented in the tanner EDA tool with the available CMOS model libraries. Based on the implementation result, the proposed LFSR area is 1824 μm2and its power consumption is 172μW at a 100 MHz clock frequency withVDD=5V. Furthermore, having the better performance in different corners of the method, reduces the propagation delay and leakage current in the digital circuit. The proposed LFSR design is compared with some of the shift registers such as unidirectional and bidirectional shift registers. The existing clock pulse generator such as conventional, delayed clock pulse, TIMBER logic, PTL-AND logic and multiplexer based clock pulse generator (MCPG) are compared with the proposed BBG-DTMOS technique.

FPGA-Based Speed Control Strategy of PMSM Using Improved Beetle Antennae Search Algorithm

To improve performance in terms of overshoot and motor response speed when a permanent-magnet synchronous motor (PMSM) with a proportional–integral (PI) controller is subjected to external disturbances, this paper proposes a speed control strategy based on an enhanced Beetle Antennae Search algorithm, which allows for adjustable parameters of the PI controller within a certain range. Firstly, to enhance the global and local search capabilities of each individual beetle, the step size was improved by linearly decreasing it. Secondly, a simulation model of a PMSM closed-loop control system was built to verify the effectiveness of the improved Beetle Antennae Search (BAS) algorithm. Finally, a linear feedback shift register model that generates four random numbers was developed on a field-programmable gate array (FPGA). The improved BAS algorithm for the PMSM control system was implemented on an FPGA using the Verilog hardware description language, and the feasibility of the system was verified through hardware simulation. Additionally, the hardware resource consumption on different FPGA platforms was analyzed. The simulation results demonstrate that the proposed new speed control strategy can reduce the overshoot and improve the motor response speed.

Analysis of linear feedback shift registers and chaos-based techniques for image encryption

ABSTRACT Image encryption is not new. Several different encryption algorithms have been used. Some of the algorithms are based on random sequences generated using chao systems and DNA sequencing and others are based on compression. Still, others are based on Linear Feedback Shift Registers. This paper focuses on research solutions for securing digital images including medical images. Medical images are important and are generally regarded as sensitive in nature. In this research paper, higher order linear feedback shift registers are developed using combination of lower order LFSRs by suitable clocking and the ciphers generated are utilized to encrypt digital images. Our analysis involves using suitable metrics to compare the chaos-based and LFSR-based stream ciphers for image encryption.

Design of Universal Code Generator for Multi-Constellation Multi-Frequency GNSS Receiver

A multi-constellation, multi-frequency Global Navigation Satellite System (GNSS) receiver is capable of simultaneously receiving signals from multiple satellite constellations across various frequency bands. This allows for increased observations, thereby enhancing navigation accuracy, continuity, effectiveness, and reliability. The spread spectrum code structures used in satellite navigation signals differ among systems. Compatible code generators are employed in multi-constellation, multi-frequency GNSS receivers to support tasks such as signal acquisition and tracking. There are three main types of spread spectrum code structures: Linear Feedback Shift Register (LFSR), Legendre sequences, and Memory codes. The Indian Regional Navigation Satellite System (IRNSS) released the L1-SPS (Standard Positioning Service) signal format in August 2023, which utilizes the Interleaved Z4-linear ranging code (IZ4 code) as its spread spectrum code. Currently, there is no universal code generator design compatible with the IZ4 code. In this paper, a proposed universal code generator is based on the hardware structure of the IRNSS IZ4 code generator. It achieves compatibility with all LFSR-based spread spectrum codes and enables parallel generation of multiple sets of GNSS signal spread spectrum codes, thereby improving hardware utilization efficiency. The proposed structure is implemented and validated using FPGA design, and resource consumption is provided as part of the validation results.

Enhancing Data Protection through Advanced Encryption or Improving Data Security with Advanced Encryption

The protection of information content is becoming a key concern with the recent exponential growth of digital data interchange over computer networks. Numerous security vulnerabilities can readily jeopardize the information sent over a network. An enhanced modification for the Advanced Encryption Standard (AES) algorithm is proposed and implemented using an additional key that generated using a linear feedback shift register (LFSR), which provides an efficient technique to pseudo random number generation and also reduces the number of rounds. Cryptography plays a crucial role in ensuring the security of digital data transmission over these unsafe networks. When compared to the original AES algorithm result, the suggested technique produces the expected results for several data types, including text, images, It is more important than ever to strengthen data protection procedures in an era of rising cyber dangers and growing reliance on digital data. A thorough framework for "Enhancing Data Protection through Advanced Encryption" (EDPAE) is introduced in this study. The project's goal is to protect sensitive data by utilizing state-of-the-art encryption techniques in response to the ever-changing cyber security scenario. In addition, the project places a strong emphasis on how to seamlessly incorporate advanced encryption into current data storage and communication systems in order to minimize interference with user operations and greatly improve overall security posture. In order to guarantee the secure creation, distribution, and storage of encryption keys and to reduce potential risks related to key compromise, key management features are addressed.

Bisimulations of nonlinear feedback shift registers

This work investigates how to reduce nonlinear feedback shift registers (NFSRs) in combination with bisimulation method via semi-tensor product (STP). By considering a large-scale NFSR as a smaller-scale Boolean system utilising bisimulation relations, the computing complexity of the system can be decreased. On the one hand, the properties of the bisimulation relation between two different NFSRs are examined, while on the other hand, a necessary and sufficient condition is discovered, as well as a reduction strategy utilising bisimulation. Besides, it is talked about how NFSR properties spread throughout the reduction process. The nonsingularity, driven stability and other aspects of the original NFSR are confirmed to be preserved by the reduced Boolean system.

Deciding Irreducibility/Indecomposability of Feedback Shift Registers Is NP-Hard

Feedback shift registers (FSRs) are used as a fundamental component in electronics and confidential communication. A FSR f is said to be reducible if all the output sequences of another FSR g can also be generated by f and the FSR g costs less memory than f. A FSR is said to be decomposable if it has the same set of output sequences as a cascade connection of two FSRs. Two polynomial-time computable transformations from Boolean circuits to FSRs are proposed such that the output FSR of the first (resp. second) transformation is irreducible (resp. indecomposable) if and only if the input Boolean circuit is satisfiable. Through the two transformations, it is proved that deciding irreducibility (indecomposability) of FSRs is NP-hard. Additionally, FSRs are constructed to show that there exist infinitely many irreducible (resp. indecomposable) FSRs which are decomposable (resp. reducible).