ABSTRACT In this article, a self-bias MOSFET-based dual-resistive feedback low-noise amplifier (LNA) is investigated. A detailed mathematical analysis of the addressed amplifier has been carried out using the return ratio-based feedback analysis technique. Furthermore, the LNAs have been simulated via Cadence using the TSMC 65 nm PDK. Two g m / I D strategies are described to handle the performance trade-offs for enhancing gain, noise figure (NF) and power consumption. The two strategies are conceptually similar to one another, with the selection of the transconductance efficiency being the only difference. While the first technique uses a transconductance efficiency to achieve the lowest power consumption while keeping an acceptable NF, the second strategy uses a particular transconductance efficiency for flawless noise cancelling without consideration for reduced power consumption. According to simulation results, the first recommended LNA has a voltage gain of 12 dB over a 3 dB bandwidth of 0.5–10 GHz, a minimal NF of 1.7 dB @ 7.014 GHz, a maximum NF of 1.932 dB @ 0.5 GHz, consumes 12.42 mW from a low supply voltage of 1.2 V and achieved a third-order intercept of −2.34 dBm @ 1 GHz. The simulation results of the second recommended LNA also show that it can operate with a low supply voltage of 1.2 V and still achieve a minimum NF of 0.978 dB @ 2.729 GHz, a maximum NF of 1.048 dB @ 6 GHz, II P 3 of 1.34 dBm and a voltage gain of 13 dB over a 3 dB bandwidth of 0.5–6 GHz with a consuming power of 25 mW.