FDSOI Technology Research Articles

High Scalability and Low Variability of Planar Fully Depleted SOI MOSFETs

We review recent results obtained on ultra-thin body SOI at CEA-LETI and STMicroelectronics to address the 22nm CMOS technology node and beyond. For such scaled devices, variability of threshold voltage (VT) is now widely recognized as one of the most critical challenges, especially for dense SRAM cells. Fully Depleted (FD) SOI MOSFETs, with its undoped channel, are proposed here as a solution to overcome this issue: The lowest variability compared to bulk and FinFETs devices has been recently reported in planar devices down to 25nm gate length. Thinning SOI and BOX thicknesses has been also investigated as solutions to scale further this planar FDSOI technology. All these experimental results make the planar FDSOI technology one of the best candidate for the low power 22nm technology node and beyond.

Proposal of a Double-Gate Split-Drain/Source MAGFET with Bulk Conduction in FD SOI Technology

Proposal of a Double-Gate Split-Drain/Source MAGFET with Bulk Conduction in FD SOI Technology

Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors

The transient radiation response of single- and multiple-gate fully depleted silicon-on-insulator (FD SOI) transistors is investigated with heavy ion and pulsed laser experiments. Very fast transients are shown on single-gate devices while non-planar Omega-gate transistors exhibit longer transient pulses. The current process of multi-gate devices, which includes long resistive access to source and drain electrodes, is shown to be responsible for these longer pulses, they are not an intrinsic characteristic of multi-gate devices. The charge collection mechanisms are discussed with 3-D device simulations as a function of device architecture and design. Mixed-mode simulations are used to present trends on the sensitivity to single event upset and single event transient of elementary cells based on a 50 nm FD SOI technology.

Direct Measurement of SET Pulse Widths in 0.2-$\mu$m SOI Logic Cells Irradiated by Heavy Ions

Heavy-ion-induced SET-pulse widths in NOR-logic cells fabricated by a 0.2-mum FD-SOI technology are directly measured by using an on-chip self-triggering flip-flop circuit. The pulse widths are distributed from 0.3 to 1.0 ns under a constant LET of 40 MeVmiddot cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg

A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

A 0.25-/spl mu/m, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm/sup 2/ silicon die has been developed leveraging the existing bulk design. FD-SOI technology is used because it has better immunity for dynamic leakage current than partially depleted SOI in high speed dynamic circuits without body contact. C-V characteristics of metal-oxide-silicon-oxide-silicon with and without source-drain junctions are described to explain the behavior of FD-SOI transistor. Race, speed, and dynamic stability have been simulated to reassure the circuit operation. Key process features are shallow trench isolation, 4-nm gate oxide, 30-nm co-silicide, 46-nm silicon film, and 200-nm buried oxide. The FD-SOI microprocessor runs 30% faster than that of bulk, and it passes the reliability and system test.

Quality circles—an experience in Jyoti Limited : A. V. Dandekar. QR J. (India). 107 (September 1983)

This paper investigates the impact of terrestrial radiation on soft error (SE) sensitivity along the very large-scale integration (VLSI) roadmap of bulk, FDSOI and finFET nano-scale technologies using the MUSCA SEP3 tool. The terrestrial radiation considered in this work includes neutron, proton, and muon particles and alpha-emitters.The results indicate that protons and muons must be taken into account for ground environments. However, significant differences were observed for bulk, FDSOI and FinFET technologies. The downscaling induces an increase in SEU susceptibility to radiation. An overall analysis indicates that the SER does not increase drastically with technological integration for the three technologies considered. Moreover, the results show that FDSOI and FinFET technologies provide resistance to the ionizing radiation effects due to narrow sensitivity volumes. At the ground altitudes, the total SER ranges from 103 and 104 FIT/Mbit for the planar bulk technology while it ranges from 102 and 103 FIT/Mbit for the FDSOI and FinFET technologies.The results of analyses show that for the avionic altitude, neutron and/or the proton environments induce the main contribution to the total SER, whereas muon and α-SER impacts are negligible. For the 45-nm technological node (all types), the neutron contribution is around 60–70% of the total SER. Concerning the ground altitude, α-SER is the main contribution down to the 28-nm node. Moreover, the results suggest muon-induced upset affects the soft error rate from 32-nm SRAM operated at a nominal supply voltage and has a significant impact for circuits fabricated in smaller process technologies (22-nm and 14-nm). In addition, the results show that the muon impact can be the main contribution at 22-nm and beyond. Future terrestrial error rate predictions will require characterizations of the linear energy transfer (LET) threshold with consideration of muon and/or proton environments.