FB Shift Research Articles

Simultaneous electric dipoles and flat-band voltage modulation in 4H-SiC MOS capacitors through HfO2/SiO2 interface engineering

We report an approach to simultaneously tune the electric dipoles and flat-band voltage (V FB) of 4H-silicon carbide (SiC) metal-oxide-semiconductor (MOS) capacitors through high-k oxide dielectric interface engineering. With an additional HfO2 thin layer on atomic layer deposition (ALD) of SiO2 film, a dipole layer was formed at the HfO2/SiO2 interface, leading to a small positive shift of the V FB of 0.3 V in 4H-SiC MOS capacitors. The Kelvin probe method was used to examine the dipole layers induced at the direct-contact oxide/4H-SiC interfaces. It was found that a minor difference of 0.3 V in the contact potential difference (V CPD) is observed between the SiO2/4H-SiC and HfO2/SiO2/4H-SiC stacks, which signifies the presence of a weak interface dipole layer at the interface of HfO2 and SiO2. Additionally, investigation of the interface state density reveals that ALD of the HfO2 process had a negligible impact on the quality of the SiO2/4H-SiC interface, suggesting that the observed small positive V FB shift originated from the HfO2/SiO2 interface rather than the SiO2/4H-SiC interface.

Thickness-Dependent Flat-Band Voltage of Ferroelectric Al0.7Sc0.3n Films on SiO2/Si Substrate

Ferroelectric films have a high potential for random access memory (RAM) thanks to the switching speed with low power consumption. Along with the advent of ferroelectric HfO2 films, various materials have been reported to show high remnant polarization (P r) with thickness scalability. Although its high P r can be utilized for data storage, and charge trapping in addition to the depolarization field to compensate the P r has been the issue for ferroelectric/paraelectric stacked structure. It was recently reported that Al1-x Sc x N (ASN) films have a high P r of above 100 µC/cm2 and are expected for high-density RAM applications [1]. However, the charge trapping behavior at AlScN/paraelectric interface is not characterized yet. In this work, we fabricated Al0.7Sc0.3N(1~50nm)/SiO2(27nm)/nSi MOS capacitors to measure the surface potential change induced by the thickness of the ASN films.ASN films were sputter deposited on a thermally oxidized 27-nm-thick SiO2. The thickness of the ASN films was changed from 1 to 50 nm. TiN films were in-situ deposited atop, and patterned to be the gate electrodes. Finally, annealing at 420oC in forming gas was conducted. The ASN films used in this study have a coercive field of 5.3 MV/cm and are already up-polarized [2]. Therefore, no ferroelectric switching is involved during the capacitance-voltage (C-V) measurements.Fig. 1 shows the obtained C-V curves of the MOS capacitors, where we can see a strong thickness-dependent shift in the C-V curves. No apparent hysteresis nor SiO2/Si interface degradation was observed. Fig. 2 shows the summary of the extracted V fb on equivalent oxide thickness (EOT). In the thin layer region, V fb shifts to a positive direction and saturates with a shift by 0.27 V. Further increase in the thickness shifts back to the negative direction, and again gradually to the positive direction. Although the physical origin of the complicated V fb shift behavior is not clear, we anticipate that the thickness-dependent stain to induce an inverse piezoelectric effect with charge trapping is the origin of the behavior.In conclusion, we measured the V fb shift of ASN films on the SiO2/Si substrate. The thickness-dependent V fb shift showed complicated behavior with a thickness that can be attributed to the piezoelectric property of ASN films.

Investigation of degradation mechanism after negative bias temperature stress in Si/SiGe channel metal–oxide–semiconductor capacitors induced by hydrogen diffusion

In this research, based on I–V and C–V measurement at different temperatures, the interface defect density in the device with the Si/SiGe channel was discussed. In addition, negative bias temperature instability (NBTI) is also studied. In previous research, most of the flat-band voltage (V FB) shifts during NBTI stress was attributed to hole injection. In this article, however, the release of atomic hydrogen from the Si–H bonds at the SiO2/Si interface and at the SiGe interface produces a fixed oxide charge, which causes V FB shifts which vary with material.

(Invited) Study of HfO2-Based High-k Gate Insulators for GaN Power Device

We discussed about usefulness of HfO2-based high dielectric constant (High-k) materials such as HfO2, HfSiOx and HfAlOx as gate insulator for GaN power device. Here, we systematically studied characteristics of Hf0.55Al0.45Ox gate insulator which fabricated by plasma-enhanced atomic layer deposition and post-deposition annealing (PDA) at 800°C in N2 ambient. The Hf0.55Al0.45Ox film had an amorphous structure but Ga diffusion into Hf0.55Al0.45Ox film was observed after PDA. The k-value of the Hf0.55Al0.45Ox film was 17.2, which was larger than that of HfSiOx (13.5). The Hf0.55Al0.45Ox also showed superior electrical properties such as a minimal flatband voltage (V fb) hysteresis ( +10 mV) and a relatively small V fb shift ( £ -0.95 V), as well as a low interface state density (~ 1 ´ 1011 cm-2eV-1 at Ec-E=0.25 eV), and a high breakdown electric field (8.6 MVcm-1). Based on these experimental data and previous our research of HfO2 and HfSiOx films, we concluded the HfSiOx and HfAlOx had candidate materials as gate insulator for GaN power device.

(Invited) Characteristics of Several High-k Gate Insulators for GaN Power Device

We systematically investigated characteristics of Pt-gated capacitors with four kinds of gate insulators such as Hf0.57Si0.43Ox, Hf0.64Si0.36Ox, HfO2, and Al2O3. The Hf0.64Si0.36Ox films fabricated by post-deposition annealing (PDA) at 800°C in O2 (PDO), N2(PDN), and 3% H2 (PDH) ambient exhibited quite different characteristics. After PDO, the Hf0.64Si0.36Ox film was partially crystallized and had a thick interfacial layer at the n-GaN/Hf0.64Si0.36Ox interface, while the Hf0.64Si0.36Ox films after PDN and PDH maintained an amorphous structure. The PDH capacitor exhibited an order of magnitude larger interface state density than the PDN capacitor, indicating that the PDN process can produce superior Hf0.64Si0.36Ox film. The Hf0.57Si0.43Ox,Hf0.64Si0.36Ox, HfO2, and Al2O3 films after PDA at 800°C in N2 were 15.4, 15.9, 17.6, and 9, respectively. The HfO2 and Al2O3 films consist of polycrystalline structure while the Hf0.57Si0.43Ox and Hf0.64Si0.36Ox films maintain an amorphous structure. The different structure strongly affected to electrical properties. The Hf0.57Si0.43Ox and Hf0.64Si0.36Ox capacitors showed superior electrical properties such as a minimal flatband voltage (V fb) hysteresis ( ≤ +70 mV) and a small V fb shift ( ≤ -0.46 V), as well asa low interface state density (~ 3 × 1011 cm-2eV-1 at -0.45 eV fromconduction band), and a high breakdown electric field ( ≥ 8.6 MV/cm) compared to those of the HfO2 and Al2O3 capacitors.

Compensation of oxygen defects in La-silicate gate dielectrics for improving effective mobility in high-k/metal gate MOSFET using oxygen annealing process

Oxygen incorporation for compensation of oxygen defects is investigated with La-silicate dielectrics in directly contacted with the Si substrate. The amount of oxygen is controlled by the temperature of annealing in oxygen atmosphere (oxygen annealing) and the thickness of the gate electrode. The positive shift in flatband voltage ( V FB) by oxygen incorporation is an experimental evidence for defects compensation in La-silicate dielectrics. Optimum oxygen annealing provides the V FB shift toward positive direction without increasing equivalent oxide thickness (EOT). Although the oxygen annealing degrades the interfacial property at La-silicate/Si interface, subsequent forming gas annealing (FGA) can recover the interfacial property. It is experimentally revealed that the positive V FB shift of La-silicate dielectrics is stable even after subsequent FGA. The supplied oxygen in La-silicate is expected to maintain even after reducing process. Movement of Fermi level toward the Si valence band edge caused by oxygen incorporation is successfully observed by XPS. Moreover, no chemical reaction between La-silicate and Si substrate by oxygen annealing are confirmed from TEM observation and analyses of X-ray photoelectron spectra. It is experimentally demonstrated that effective hole mobility can be improved without increase in EOT by combination of oxygen annealing and FGA.

Thickness and material dependence of capping layers on flatband voltage ( VFB) and equivalent oxide thickness (EOT) with high-k gate dielectric/metal gate stack for gate-first process applications

We investigated controllability and scalability of flatband voltage ( V FB) and equivalent oxide thickness (EOT) using various thin capping films such as single layers (Hf, La, Ti, Al, Ta) and mixed layers (Hf/Ti, Al/Ti, Ta/Ti) with high-k gate dielectric/metal gate stack for gate-first process. With increasing thickness, negative V FB shift observed with Hf and La while Ti and Al provided positive shift in conjunction with EOT scaling down to 0.6 nm simultaneously. Ti-based mixed cap layers showed both positive V FB shift and EOT scaling with increasing thickness and higher Ti ratio. Al cap exhibited turn-around effect in V FB shift behaviors beyond 0.7 nm thickness, which is attributed to strong scavenging interfacial layer rather than dipole formation. Based on V FB modulation and EOT scaling, we propose novel process integration scheme for the gate first CMOS by adjusting Al composition in TiAlN single metal gate.

High work function metal gate and reliability improvement for MOS device by integration of TiN/MoN and HfAlO dielectric

Electrical characteristics and thermal stability of MOS devices with MoN/TiN metal stacks and various gate dielectrics were studied in this work. High work function (5.0 eV) gate is achieved by integrating MoN/TiN stack with HfAlO dielectric. The gate stack structures can enhance the thermal stability and reduce the interaction between the metal gate and the dielectric. The Ti diffusion in the dielectric can be suppressed by AlN in HfAlO. Reliability characteristics, in terms of stress-induced leakage current and stress-induced V fb shift, are improved for metal gate stack on HfAlO high- k dielectric in comparison with that on SiO 2. The work function of metal gate also can be turned by different Al contents in high- k dielectrics and metal gate stacks (4.88–5.0 eV).

Preparation and performance of dye-sensitized solar cells based on ZnO-modified TiO2 electrodes

The ZnO-modified TiO2 electrode was prepared by adding Zn(CH3COO)2·2H2O to the TiO2 colloid during the sol-gel production process, and was used in dye-sensitized solar cells (DSCs). The open circuit voltage (V OC) and fill factor (ff) of the cells were improved significantly. The performances of the ZnO-modified TiO2 electrode such as dark current, transient photocurrent, impedance, absorption spectra, and flat band potential (V fb) were investigated. It is found that the interface charge recombination impedance increases and V fb shifts about 200 mV toward the cathodic potential. The effect mechanism of ZnO modification on the performance of DSCs may be that ZnO occupies the surface states of the TiO2 film.

Sensory integration in PMd: position-dependent dynamic reweighting of vision and proprioception

Event Abstract Back to Event Sensory integration in PMd: position-dependent dynamic reweighting of vision and proprioception Matthew Fellows1* and Phillip Sabes1 1 University of California San Francisco (UCSF), Department of Physiology and Keck Center , United States It has been observed behaviorally that human and non-human primates combine information from multiple sensory modalities. In many situations this combination has been found to be statistically near-optimal, meaning that the multi-modal (i.e., integrated) percept is formed by weighting each modality in proportion to its precision. However, sensory modalities are not represented homogeneously across cortex - for a given modality, both the strength of sensory representation and its functional role vary from area to area. How, then, do disparate local cortical representations manifest as globally optimal behavior? To begin addressing this question, we quantified – both behaviorally and in neurons – the integration of visual and proprioceptive information about hand location across a range of arm positions. We recorded simultaneous activity from large ensembles of dorsal premotor cortex (PMd) neurons in a monkey performing "out-to-center" reaching movements from multiple start locations to a central target, which he was required to fixate. We provided artificial visual feedback ("FB", a cursor) about the animal’s otherwise unseen hand location. This allowed us to impose a discrepancy ("FB shift") between the visual and proprioceptive feedback. We used FB shifts in different directions to measure how the animal weighted each modality when estimating hand location for reach planning. Optimality arguments predict that the integrated estimate of hand location should depend on the relative uncertainty of vision and proprioception. In general, these uncertainties are anisotropic and vary over space. That is, for hand localization, proprioceptive uncertainty changes with hand position, and visual uncertainty depends on hand position relative to gaze location. Therefore, due to the anisotropies, FB shifts in different directions should induce localization errors that differ in both magnitude and direction. In addition, due to the position-dependence, this pattern of shift-induced errors should change with start location. We quantified these error patterns both from the animal’s behavior and from population activity in PMd, and compared them. Behavioral analysis showed that the animal flexibly integrates vision and proprioception, with the weighting of each modality varying as a function of arm configuration: the observed error patterns showed systematic, position-dependent anisotropies. We observed flexible sensory reweighting in the PMd population activity as well, with error patterns that were similar to behavior in both orientation and position-dependence. However, the dependence on vision was greater for PMd than for behavior: for a given FB shift, the integrated hand location read-out from PMd is closer to the cursor than the location read-out from behavior. The spatial dependence we observed supports the idea that multi-modal integration, as measured with PMd activity and with behavior depends, at least in part, on the (anisotropic) variability of the sensory modalities. However, the greater dependence on vision in PMd suggests that sensory integration varies across the cortical reach circuit. For example, we expect that integration in primary motor cortex would look more like behavior than does PMd. This highlights the question of how diverse local cortical circuits are used in concert to drive overall behavior. Conference: Computational and Systems Neuroscience 2010, Salt Lake City, UT, United States, 25 Feb - 2 Mar, 2010. Presentation Type: Poster Presentation Topic: Poster session I Citation: Fellows M and Sabes P (2010). Sensory integration in PMd: position-dependent dynamic reweighting of vision and proprioception. Front. Neurosci. Conference Abstract: Computational and Systems Neuroscience 2010. doi: 10.3389/conf.fnins.2010.03.00094 Copyright: The abstracts in this collection have not been subject to any Frontiers peer review or checks, and are not endorsed by Frontiers. They are made available through the Frontiers publishing platform as a service to conference organizers and presenters. The copyright in the individual abstracts is owned by the author of each abstract or his/her employer unless otherwise stated. Each abstract, as well as the collection of abstracts, are published under a Creative Commons CC-BY 4.0 (attribution) licence (https://creativecommons.org/licenses/by/4.0/) and may thus be reproduced, translated, adapted and be the subject of derivative works provided the authors and Frontiers are attributed. For Frontiers’ terms and conditions please see https://www.frontiersin.org/legal/terms-and-conditions. Received: 20 Feb 2010; Published Online: 20 Feb 2010. * Correspondence: Matthew Fellows, University of California San Francisco (UCSF), Department of Physiology and Keck Center, Rijeka, United States, mrfellows@phy.ucsf.edu Login Required This action requires you to be registered with Frontiers and logged in. To register or login click here. Abstract Info Abstract The Authors in Frontiers Matthew Fellows Phillip Sabes Google Matthew Fellows Phillip Sabes Google Scholar Matthew Fellows Phillip Sabes PubMed Matthew Fellows Phillip Sabes Related Article in Frontiers Google Scholar PubMed Abstract Close Back to top Javascript is disabled. Please enable Javascript in your browser settings in order to see all the content on this page.

Structural characterization and electro-physical properties for SiOC(–H) low-k dielectric films

Abstract Low dielectric constant SiOC(–H) thin films with different structural orders were fabricated, and the influence of the replacement of Si–O bonds to the (Si–R) bonds on structural and electro-physical properties has been investigated. The structural characteristics can be explained on the basis of the optical emission spectra and the electrical properties. It was found that the excess –CH 3 or Si–CH 3 and Si–H bonds in SiOC(–H) films produced the effective positive charges coming from excessive interstitial defects. The electro-physical properties of the deposited films, such as capacity, V fb shifts, density of charges and mechanisms of conduction strongly depended of the excessive (Si–CH 3 ) + /(Si–O) − bonds ratio and have been significantly changed (controlled) by the addition of oxygen.

Characterization of Ni/Ho and Ni/Er fully silicided metal gates on SiO 2 gate dielectric

This paper investigates the effects of Ho and Er on the sheet resistance and crystallinity of Ni(Ho) and Ni(Er) silicides, the work function (WF) modulation of Ni(Ho) and Ni(Er) fully silicided (FUSI) gate electrodes on SiO 2 dielectric, and the FUSI gated SiO 2/Si interface trap properties by using high-frequency capacitance–voltage ( C– V) and photonic high-frequency C– V measurements. It was found that as the thickness percentage of rare earth (RE) metal in the Ni(Ho) or Ni(Er) increases, the sheet resistance of the silicide increases. The crystallinity decreases in the Ni(Ho) and Ni(Er) silicides, and the crystallinity decreases as the Ho thickness percentage increases. As the thickness percentage of Ho in the Ni(Ho) increases from 13% to 30%, the flatband voltage ( V FB) shift increases from −0.19 to −0.27 V. The V FB shifts negatively 0.17 V due to 10% Er incorporation in the Ni(Er). The V FB shift can be attributed to the effective WF decrease which may be due to the crystallinity decrease of Ni(Ho) and Ni(Er) FUSI. The interface trap density D it calculated from the photonic high-frequency C– V curves is in good agreement with that calculated from the high-frequency and photonic high-frequency C– V curves. The Ho or Er addition does not increase the D it.

Dual layer SrTiO 3/HfO 2 gate dielectric for aggressively scaled band-edge nMOS devices

We have fabricated TiN/Poly-Si gated MOS devices with SrTiO 3/HfO 2 dual layer gate dielectric. These gate dielectrics show EOT (Equivalent Oxide Thickness) scaling of less than 0.7 nm as well as large V fb shift in the nMOS direction after conventional gate first process. A sweet spot is observed for 0.5 nm SrTiO 3 where a band-edge effective work-function is obtained with improved EOT, reduced gate leakage and minimal hysteresis increase. But Sr diffuse into the interfacial layer leads to interface degradation. It is shown that proper PDA (post-deposition anneal) can improve interface quality while maintaining thinner EOT.

Forming gas anneal induced flat-band voltage shift of metal-oxide-semiconductor stacks and its link with hydrogen incorporation in metal gates

Detailed studies were performed on the forming gas anneal (FGA, 10% H 2 in N 2) induced flat-band voltage (V fb) shift of Ru and Mo gated Metal-Oxide-Semiconductor (MOS) stacks. The dependence of the V fb shift on the FGA temperature was studied on Ru gated stacks. For the first time, the FGA-induced V fb decrease was also observed on Mo and MoO x gated stacks. The FGA-induced decrease in V fb was found to be unstable as a low temperature N 2 anneal could significantly restore the V fb. Incorporation of hydrogen in the interfacial RuO x or MoO x layers is believed to be the main cause for the V fb decrease, at least for relatively low FGA temperatures.

Mechanism of O 2-anneal induced Vfb shifts of Ru gated stacks

A systematic study of the flat-band voltage ( V fb) shift of Ru gated metal-oxide-semiconductor (MOS) capacitors subjected to thermal treatment in O 2 has been performed. The dependence of the V fb shift on the thickness of Ru, anneal temperature and time is studied. The V fb shift is ascribed to the shift of metal gates’ work function (WF), and is not significantly dependent on the type of dielectric (HfO 2 or SiO 2). From time-of-flight secondary ion mass spectrometry (TOF-SIMS) measurement, it was found that after thermal treatment in 18O 2, 18O penetrated through Ru and was incorporated in the Ru/dielectric interface region. We believe that the formation of the thin interfacial RuO x layer is responsible for the V fb shift.

Characteristics of mechanically milled silicon nanocrystals embedded in TEOS thin films

In this work, the unique synthesis of mechanically milled silicon nanocrystals (Si nc) embedded in tetraethylorthosilicate (TEOS) thin films is reported. The Si nc are required to be synthesized externally via inexpensive mechanical milling before it is mixed with the TEOS solution for spin coating. Si nc with a range of sizes, from 10 to 25 nm, have been synthesized using mechanical milling. These milled Si nc and milled Si nc embedded in TEOS thin film are characterized by differential thermal analysis (DTA), Raman spectroscopy and photoluminescence excitation (PLE). The defects, such as non-bridging oxide hole centers (NBOHCs), in amorphous SiO 2 are found to be the most probable dominant mechanism for the PL of milled Si nc embedded in films. The milled Si nc embedded in TEOS thin film is further developed into MOS capacitor. Charge trapping in Si nc with a V FB shift of 0.4 V is observed.

Improvement of the SiO 2/Si interface characteristics by two-step deposition with intermediate plasma treatment using N 2/He or O 2/He gas

Two-step deposition using O 2/He or N 2/He intermediate plasma treatment was studied to improve the characteristics of SiO 2/Si interfaces. Under this method plasma damage on the Si surface could be minimized and the interface characteristics such as intermediate oxidation states, causing P b center, and V fb shift could be improved. In the case of the intermediate plasma treatment on 6 nm 1st oxide, the improvement of the interface characteristics was best. N 2/He plasma intermediate treatment showed better interface characteristics than O 2/He plasma treatment. The number of Si atoms (N SiO x ) in the sub-oxide region was decreased by approximately 27% after N 2/He plasma intermediate treatment compared with the sample without plasma treatment. Also, the transition layer thickness was decreased to 1.34 monolayers. P b center density decreased from 4.7×10 12/eV cm 2 to 2.29×10 11/eV cm 2 due to nitrogen incorporation in the transition region. The moderate nitrogen incorporation near the SiO 2/Si interface reduced the V fb shift due to the decrease in the fixed oxide charge.

The 1.3–1.6 nm nitrided oxide prepared by NH 3 nitridation and rapid thermal annealing for 0.1 μm and beyond CMOS technology application

High quality and high performance gate dielectrics prepared by NH 3 nitridation, with equivalent oxide thickness (EOT) down to 1.3–1.6 nm, were firstly investigated. NH 3 nitridation can effectively reduces the EOT to a lower down gate leakage current for more than one order in comparison to the control oxide with identical EOT. More significant barrier height lowering in valence band than in conduction band leads to inferior gate leakage behavior in PMOS after NH 3 nitridation. In addition, NH 3 nitrided NMOS shows a significant improvement in current drivability. But, larger V fb shift and drivability degradation were observed in PMOS. Fortunately, the most of them can be reduced with post-deposition annealing to meet the process target. The quality and reliability were also exanimated by the hysteresis, temperature and time-to-breakdown characteristics.

Na 0.5 K 0.5 NbO 3 Thin Films for MFIS_FET Type Non-Volatile Memory Applications

Na 0.5 K 0.5 NbO 3 (NKN) thin films have been prepared on Pt 80 Ir 20 , SiO 2 /Si, and Ta 2 O 5 /Si substrates for ferroelectric non-volatile memory applications. Ferroelectric hysteresis loops for Au/NKN/Pt 80 Ir 20 vertical capacitor yielded remnant polarization of 12 w C/cm 2 and coercive field ∼20 kV/cm. Significant flat-band voltage V FB shifts with buffer layer thickness in Au/NKN/SiO 2 /Si structures have been attributed to the intermixing between Na and K alkali ions and SiO 2 layer. On the other hand, Au/NKN/Ta 2 O 5 /Si structure exhibited wide memory window without significant V FB deviations, low leakage currents, and rather long retention time at zero bias.

Na 0.5 K 0.5 NbO 3 Thin Films for MFIS_FET Type Non-Volatile Memory Applications

Na 0.5 K 0.5 NbO 3 (NKN) thin films have been prepared on Pt 80 Ir 20 , SiO 2 /Si, and Ta 2 O 5 /Si substrates for ferroelectric non-volatile memory applications. Ferroelectric hysteresis loops for Au/NKN/Pt 80 Ir 20 vertical capacitor yielded remnant polarization of 12 w C/cm 2 and coercive field ∼20 kV/cm. Significant flat-band voltage V FB shifts with buffer layer thickness in Au/NKN/SiO 2 /Si structures have been attributed to the intermixing between Na and K alkali ions and SiO 2 layer. On the other hand, Au/NKN/Ta 2 O 5 /Si structure exhibited wide memory window without significant V FB deviations, low leakage currents, and rather long retention time at zero bias.