Dual layer SrTiO 3/HfO 2 gate dielectric for aggressively scaled band-edge nMOS devices

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We have fabricated TiN/Poly-Si gated MOS devices with SrTiO 3/HfO 2 dual layer gate dielectric. These gate dielectrics show EOT (Equivalent Oxide Thickness) scaling of less than 0.7 nm as well as large V fb shift in the nMOS direction after conventional gate first process. A sweet spot is observed for 0.5 nm SrTiO 3 where a band-edge effective work-function is obtained with improved EOT, reduced gate leakage and minimal hysteresis increase. But Sr diffuse into the interfacial layer leads to interface degradation. It is shown that proper PDA (post-deposition anneal) can improve interface quality while maintaining thinner EOT.