Faulty Memory Research Articles

Trauma, Mind Style, and Unreliable Narration in Toni Morrison’sHome

ABSTRACTThis article provides a twofold reading of Toni Morrison’s novel Home. In the first instance, the stylistic representation of post-traumatic stress disorder (PTSD) is explored in relation to Frank’s mind style; this is done through a focused examination on passages related to Frank’s misremembered murder of a girl during his time as a soldier in the Korean War. Frank’s guilt and faulty memories, and his lingering experience of PTSD, lead to the issue of narrative unreliability. This article shows how not just Frank himself but also the unspecified third-person narrator is just as unreliable as Frank, if not more so. The seemingly contentious relationship between Frank and the other narrator ultimately leads to Frank’s realization about his hand in the murder of the Korean girl, and hence to a coming to terms with and recovery from war-induced PTSD.

RescueSNN: enabling reliable executions on spiking neural network accelerators under permanent faults.

To maximize the performance and energy efficiency of Spiking Neural Network (SNN) processing on resource-constrained embedded systems, specialized hardware accelerators/chips are employed. However, these SNN chips may suffer from permanent faults which can affect the functionality of weight memory and neuron behavior, thereby causing potentially significant accuracy degradation and system malfunctioning. Such permanent faults may come from manufacturing defects during the fabrication process, and/or from device/transistor damages (e.g., due to wear out) during the run-time operation. However, the impact of permanent faults in SNN chips and the respective mitigation techniques have not been thoroughly investigated yet. Toward this, we propose RescueSNN, a novel methodology to mitigate permanent faults in the compute engine of SNN chips without requiring additional retraining, thereby significantly cutting down the design time and retraining costs, while maintaining the throughput and quality. The key ideas of our RescueSNN methodology are (1) analyzing the characteristics of SNN under permanent faults; (2) leveraging this analysis to improve the SNN fault-tolerance through effective fault-aware mapping (FAM); and (3) devising lightweight hardware enhancements to support FAM. Our FAM technique leverages the fault map of SNN compute engine for (i) minimizing weight corruption when mapping weight bits on the faulty memory cells, and (ii) selectively employing faulty neurons that do not cause significant accuracy degradation to maintain accuracy and throughput, while considering the SNN operations and processing dataflow. The experimental results show that our RescueSNN improves accuracy by up to 80% while maintaining the throughput reduction below 25% in high fault rate (e.g., 0.5 of the potential fault locations), as compared to running SNNs on the faulty chip without mitigation. In this manner, the embedded systems that employ RescueSNN-enhanced chips can efficiently ensure reliable executions against permanent faults during their operational lifetime.

Investigating false memories among “winners” and “losers” in the prisoner’s dilemma

ABSTRACT Many legal cases hinge on evaluating the veracity of two versions of events (“he said, she said”). Expert witnesses are often called upon to testify on the malleability of memory, most often testifying for the defence. This may lead to the theoretically unfounded assumption that it is only victims who are vulnerable to distorted memories of a crime. Inspired by this question, we conducted a series of five experiments in which 2010 participants played a novel version of the Prisoner’s Dilemma. Participants could either betray their partner in the game (“winners”) or be betrayed by their partner (“losers”). We exposed participants to misinformation concerning the other player’s statements to assess whether winners and losers may be differentially susceptible to false memories of the event in question. Across our experiments, including where real financial rewards were at stake, we found that winners were just as susceptible as losers to memory distortion. We highlight the need to consider the possibility of faulty memory affecting all parties to in legal cases, though further research is needed beyond this highly artificial paradigm.

Thomas Kuhn, Hyperbole, and the Ashtray: Evidence of Morris’ Faulty Memory

AbstractErrol Morris has claimed that Kuhn threw an ashtray at him during a dispute about some matter in the history of science. Morris also claims that Kuhn threw him out of the graduate program at Princeton for disagreeing with him. I argue that Morris’s attack on Kuhn contains some degree of hyperbole. Further, I present evidence that shows that Morris is mistaken about key events during this period. In fact, Kuhn was supportive of Morris in his pursuit of a career in the history of science.

Curing faulty memory in early modern times

À l’époque moderne, la mauvaise mémoire est prise en charge par un discours médical relativement cohérent, qui l’analyse en termes de déséquilibre humoral et qui préconise des traitements externes et des régimes de santé. Pour autant, l’approche médicale à laquelle la mémoire est soumise semble inaboutie : parce que la résistance de la nature, pour de nombreux auteurs, n’autorise pas une véritable médecine de la mémoire, parce que d’autres voies de réforme, par la discipline intellectuelle, sont offertes à travers, entre autres, les « arts de la mémoire », enfin parce que l’idée même d’une amélioration de la mémoire ne semble pas toujours opportune. Ce recours contrarié au soin invite les individus à s’accommoder de leurs aptitudes intellectuelles et à faire usage de techniques plus routinières mais aussi plus opératoires.

Effective fault localization and context‐aware debugging for concurrent programs

SummaryConcurrent programs are difficult to debug because concurrency faults usually occur under specific inputs and thread interleavings. Fault localization techniques for sequential programs are often ineffective because the root causes of concurrency faults involve memory accesses across multiple threads rather than single statements. Previous research has proposed techniques to analyse passing and failing executions obtained from running a set of test cases for identifying faulty memory access patterns. However, stand‐alone access patterns do not provide enough contextual information, such as the path leading to the failure, for developers to understand the bug. We present an approach, Coadec, to automatically generate interthread control flow paths that can link memory access patterns that occurred most frequently in the failing executions to better diagnose concurrency bugs. Coadec consists of two phases. In the first phase, we use feature selection techniques from machine learning to localize suspicious memory access patterns based on failing and passing executions. The patterns with maximum feature diversity information can point to the most suspicious pattern. We then apply a data mining technique and identify the memory access patterns that occurred most frequently in the failing executions. Finally, Coadec identifies faulty program paths by connecting both the frequent patterns and the suspicious pattern. We also evaluate the effectiveness of fault localization using test suites generated from different test adequacy criteria. We introduce and have evaluated Coadec on 10 real‐world multithreaded Java applications. Results indicate that Coadec outperforms state‐of‐the‐art approaches for localizing concurrency faults and that Coadec's context debugging can help developers understand concurrency fault by inspecting a small percentage of code.

Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC.

The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit to allocate the redundancy when defects appear in the memory. The data are accessed from the redundancy allocation when the faulty memory is operative. Thus, this BIRA scheme affects the area overhead for the BISR circuit when it integrates to the SoC. The spare row and spare column–based BISR method is proposed to receive the optimal repair rate with a low area overhead. It tests the memories for almost all the fault types and repairs the memory by using spare rows and columns. The proposed BISR block’s performance was measured for the optimal repair rate and the area overhead. The area overhead, timing, and repair rate were compared with the other approaches. Furthermore, the study noticed that the repair rate and area overhead would increase by increasing the spare-row/column allocation.

On the Rope by Erich Hackl

Reviewed by: On the Rope by Erich Hackl Viktoria Pötzl Erich Hackl, On the Rope. Translated by Stephen Brown. London: Haus Publishing, 2020. 180 pp. Erich Hackl was one of the first authors I ever saw give a reading. I was seventeen years old when he visited my high school. His book Auroras Anlaß was part of our curriculum. My school was not too far from Braunau am Inn, in Ried im Innkreis, where neo-Nazi youth and lefties (referred to as Zecken by the neo-Nazis) traded punches, and where Jörg Haider found a broad audience for his Aschermittwoch speeches. It was in this peculiar context that I listened to Erich Hackl give a reading from one of my favorite books in the late 1990s. At that time, I was as impressed as a teenager could get. I loved the author's poignant language and his choice of topics—especially since his [End Page 176] texts spoke to the budding feminist in me. Hackl's texts did not only inform my love for reading, they also offered a refreshingly rare female perspective—refreshing, at least, in the late '90s in rural Upper Austria. As I write these lines, and while I am thinking about what it means to offer female perspectives as a male author, Gayatri Spivak comes to mind, in particular her reflections on representation. Spivak discriminates between the act of speaking for someone (that is, to represent, vertreten) and that of speaking as someone (to portray, darstellen). However, Hackl handles the thorny issue of representation with utmost care, dedication, and love, which has the effect of making On the Rope an edifying read. The story's focus on the heroism of the three main protagonists, Reinhold Duschka, Regina Steinig, and Lucia Heilman, leaves little room for the perpetrators, and as a result it negates a voyeuristic reading. In Hackl's On the Rope, the narrator mostly speaks for Lucia, a Jewish girl, who survived the Shoah while in hiding with her mother Regina in Vienna. The narrator changes from the omniscient narrative voice to Lucia's own voice, allowing for a multilayered perspective. It is a story filled with compassion, bravery, and heroism and at the same time a story about the most horrible atrocity committed by millions, which ultimately ended in the killing of millions. On the Rope is based on a true story. It is a story about motherhood, friendship, resilience, survival, and solidarity. Reinhold works to save the lives of two Jewish women, Regina and Lucia, by hiding them in his workshop and providing them with food, care, and work. The book's first and main part narrates the story of our two female heroines. In the second, shorter section, we learn more about Reinhold from various perspectives, thus giving us a complex portrayal of a flawed hero, whose biography leaves us with many questions. It is exactly here that the book and the author's language show their strengths: a constant change of perspective and the bravery to write the unknown, to address gaps, to narrate various versions of one event. Here, faulty memories are not a deficiency but the very fabric from which life stories are made. Hackl's mastery in using the uncertain to his advantage culminates in offering a magnitude of perspectives, especially while creating wholesome characters about whom more is unknown than known. Though the plot is told in a linear way, the story itself questions the very concept of linearity, allowing for not only a single story but a multiplicity of versions that could have happened all at the same time, embracing the gaps, the unknown, as not everything needs to be told. It doesn't matter when exactly events took place [End Page 177] and how many people were involved; facts and numbers are just that. On the Rope transgresses facts and numbers by simply providing us with a multitude of narratives without falling into the trap of identifying the "singular," "authentic" version or truth—as there cannot be one. On the Rope is not a story about another white man saving Jewish women, who are portrayed as mere victims; the story's focus lies...

Early Shakespeare, 1588–1594. Edited by Rory Loughnane and Andrew J. Power. Cambridge: Cambridge University Press, 2020. Pp. v+324.

<i>Early Shakespeare, 1588–1594</i>. Edited by Rory Loughnane and Andrew J. Power. Cambridge: Cambridge University Press, 2020. Pp. v+324.

RETRACTED ARTICLE: A saboteur and mutant based built-in self-test and counting threshold-based built-in self repairing mechanism for memories

In system on chip (SOC) design, memory occupies a large area, if any defects in the memory that will affect the SOC’s total yield. To avoid this, spare rows and columns are added to the memory. When the fault cells need to be operated, spares rows/columns will be used instead of faulty cells using Built-in self-repair (BISR) logic. Repairing logic includes either row repair/column repair or a combination of both. In this paper, we propose two methods, one is on the memory built-in self-test (BIST) for checking the memory array circuit. In the second method, an optimized BISR is employed to repair the faulty memory cells based upon the Built-in redundancy analysis. In the BIST method, our proposed method injects the faults into memory by using two fault injection techniques called saboteurs and mutants with optimized test pattern logic. After the injection of the faults in the memory cell, the fault memory is repaired with the proposed counting threshold algorithm for the BISR scheme. Simulation and synthesis results are obtained using Mentor Graphics and Xilinx ISE Design Suite. From our obtained results it can be inferred that various performance measures like power, area, and timing details are reduced in the proposed methods when compared with the existing exhaustive methods. And this proves that the performance of the overall process is found to be enhanced. Thereby yield can also be enhanced with minimum time to market.

Prior Consistent Statement Witness Rehabilitation, Fed.R.Evid. 801(d)(1)(B), and Prior Identification Statements, Fed.R.Evid. 801(d)(1)(C)

Prior Consistent Statement Witness Rehabilitation, Fed.R.Evid. 801(d)(1)(B), and Prior Identification Statements, Fed.R.Evid. 801(d)(1)(C)

Fault Tolerant Suffix Trees

Classical algorithms and data structures assume that the underlying memory is reliable, and the data remain safe during or after processing. However, the assumption is perilous as several studies have shown that large and inexpensive memories are vulnerable to bit flips. Thus, the correctness of output of a classical algorithm can be threatened by a few memory faults. Fault tolerant data structures and resilient algorithms are developed to tolerate a limited number of faults and provide a correct output based on the uncorrupted part of the data. Suf- fix tree is one of the important data structures that has widespread applications including substring search, super string problem and data compression. The fault tolerant version of the suffix tree presented in the literature uses complex techniques of encodable and decodable error-correcting codes, blocked data structures and fault-resistant tries. In this work, we use the natural approach of data replication to develop a fault tolerant suffix tree based on the faulty memory random access machine model. The proposed data structure stores copies of the indices to sustain memory faults injected by an adversary. We develop a resilient version of the Ukkonen’s algorithm for constructing the fault tolerant suffix tree and derive an upper bound on the number of corrupt suffixes.

Autoencoders Based Deep Learner for Image Denoising

Abstract Nowadays, digital images have a valuable role in our daily life, and can be used for various of applications like fingerprint recognition, video surveillance etc. Sometimes, images get infected with noise due to many reasons such as defects in camera sensors, transmission in noisy channel, faulty memory locations in the hardware etc. Processing a noisy image is not advisable because usually it yields erroneous outcomes. So, as to improve it for subsequence processing, the noise must be eliminated from the image in advance. Therefore, there is a need of an efficient image denoising technique that helps to deal with noisy image. Image de-noising is a process to realign the original image from the degraded image. In this paper, autoencoders based deep learning model is proposed for image denoising. The autoencoders learns noise from the training images and then try to eliminate the noise for novel image. The experimental outcomes prove that this proposed model for PSNR has achieved higher result compared to the conventional models.

An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults

The current growth of micro-semiconductor technologies requires that an effective solution be found to address the yield and reliability issues associated with embedded memories. A common solution is built-in redundancy analysis (BIRA), which is utilized to guarantee reasonable memory yields. The most common form of BIRA is a module that stores and analyzes fault addresses with a 2-D spare architecture. When the performance of BIRA is evaluated, numerous different parameters are considered, such as repair rate, area overhead, and analysis speed. Because there is a tradeoff between these criteria, many BIRA approaches have been studied so that an ideal BIRA can be found. A novel BIRA approach that focuses on a 100% repair rate and a minimal area overhead is proposed in this paper. In the fault collection phase, the proposed BIRA stores only the essential part of fault addresses in content addressable memories (CAMs), with the rest of the fault addresses being stored in spare memories. After the fault collection phase, a redundancy analysis procedure is performed with the minimum amount of fault information that is stored in the proposed CAM structure. By doing so, the proposed BIRA algorithm can repair all repairable faulty memories while maintaining a minimal area overhead. Our experimental results confirm that the proposed approach exhibits outstanding performance for area overhead, especially when compared to other BIRA approaches that have 100% repair rates.

Highly Accurate Image Reconstruction for Multimodal Noise Suppression Using Semisupervised Learning on Big Data

Impulse noise corruption in digital images frequently occurs because of errors generated by noisy sensors or communication channels, such as faulty memory locations in devices, malfunctioning pixels within a camera, or bit errors in transmission. Although recently developed big data streaming enhances the viability of video communication, visual distortions in images caused by impulse noise corruption can negatively affect video communication applications. In addition, ${{sparsity}}$ , ${{density}}$ , and ${{multimodality}}$ in large volumes of noisy images have often been ignored in recent studies, whereas these issues have become important because of the increasing viability of video communication services. To effectively eliminate the visual effects generated by the impulse noise from the corrupted images, this study proposes a novel model that uses a devised cost function involving semisupervised learning based on a large amount of corrupted image data with a few labeled training samples. The proposed model qualitatively and quantitatively outperforms the existing state-of-the-art image reconstruction models in terms of the denoising effect.

Data Block Partitioning Methods to Mitigate Stuck-At Faults in Limited Endurance Memories

Deep scaling in conjunction with increased process variation has resulted in increasingly faulty memories. Emerging memories, particularly phase-change and resistive memories, can experience stuck-at faults due to limited endurance. Partition and flip (PAF) schemes partition data into blocks and invert these blocks as needed to ensure data that is written matches the stuck-at cells. In this paper, we propose two novel correction schemes that substantially enhance the fault-tolerance capabilities of existing PAF techniques. First, dynamic partitioning increases the number of possible configurations with equivalent auxiliary bits. At high fixed error rates, the increase in configurations results in improved write error rates for flip-N-write and Aegis partitioning by 7%–72% and 5– $53\times $ , respectively. Our second novel partitioning method, relaxed partitioning, dramatically and effectively increases the partitioning search space by specifying minimally overlapping configurations. Through Monte Carlo simulations, data-aware dynamic partitioning tolerates 25% and 27% more faults over its lifetime than Aegis with 36 and 43 auxiliary bits per 512-bit data block, respectively, while relaxed partitioning achieves an extra 15% and 24% additional improvement while requiring two fewer overhead bits per data block.

BIRA With Optimal Repair Rate Using Fault-Free Memory Region for Area Reduction

As manufacturing process technology scales down, memory capacity and density continue to grow. As the number of memory cells per area increases, so does the possibility of having defects in the memory cells. Therefore, built-in redundancy analysis (BIRA) is widely used for memory test and repair. BIRA repairs faulty cells by replacing them with healthy spare cells. To perform BIRA, the faulty memory cell information is required and is collected via a memory test. By using the faulty cell information, BIRA can analyze and perform the repair by assigning spares to defective cells. However, it requires extra hardware to store the faulty cell information. Most conventional BIRA approaches utilize content-addressable memories (CAMs) to store faulty cell information. Owing to the CAMs’ fast access speed, the repair time can be reduced. However, CAMs are the critical source of an area overhead for BIRA, and a CAM could be shared across multiple memory banks. The shared structure limits simultaneous repair operations for the banks, and when the CAM is faulty, the conventional CAM-based BIRA cannot be performed. This paper proposes a new BIRA method, which does not require extra memory and instead utilizes a fault-free memory region to store the faulty cell information. Because extra memory is not required in the proposed BIRA method, the area overhead is decreased. The proposed hierarchical repair algorithm thus helps to reduce the analysis time, while achieving optimal normalized repair rate.

Dreams from Another Dimension

Abstract: In 2015, I began communicating with an events planner for the U.S. Army who shared with me a series of anomalous dreams -- anomalous in the sense that the dreams usually contained specific names of deceased servicement previously unknown to her but known to an assistant chaplain with whom she worked. The goal of my ensuing case study research into this apparent episode of spontaneous mediumship was to collect these dreams, search for commonalities, and propose explanations for their anomalous aspects. Alternative explanations included fraud, faulty memory, coincidence, and telepathy or some other form of remote perception. None of these alternatives explained these anomalies as well as what the experiencer herself proposed: that the deceased themselves had successfully communicated with her during her nighttime dreams.

A Survey of Repair Analysis Algorithms for Memories

Current rapid advancements in deep submicron technologies have enabled the implementation of very large memory devices and embedded memories. However, the memory growth increases the number of defects, reducing the yield and reliability of such devices. Faulty cells are commonly repaired by using redundant cells, which are embedded in memory arrays by adding spare rows and columns. The repair process requires an efficient redundancy analysis (RA) algorithm. Spare architectures for the repair of faulty memory include one-dimensional (1D) spare architectures, two-dimensional (2D) spare architectures, and configurable spare architectures. Of these types, 2D spare architectures, which prepare extra rows and columns for repair, are popular because of their better repairing efficiency than 1D spare architectures and easier implementation than configurable spare architectures. However, because the complexity of the RA is NP-complete, the RA algorithm should consider various factors in order to determine a repair solution. The performance depends on three factors: analysis time, repair rate, and area overhead. In this article, we survey RA algorithms for memory devices as well as built-in repair algorithms for improving these performance factors. Built-in redundancy analysis techniques for emergent three-dimensional integrated circuits are also discussed. Based on this analysis, we then discuss future research challenges for faulty-memory repair studies.

Negative polarity illusions and the format of hierarchical encodings in memory

Linguistic illusions have provided valuable insights into how we mentally navigate complex representations in memory during language comprehension. Two notable cases involve illusory licensing of agreement and negative polarity items (NPIs), where comprehenders fleetingly accept sentences with unlicensed agreement or an unlicensed NPI, but judge those same sentences as unacceptable after more reflection. Existing accounts have argued that illusions are a consequence of faulty memory access processes, and make the additional assumption that the encoding of the sentence remains fixed over time. This paper challenges the predictions made by these accounts, which assume that illusions should generalize to a broader set of structural environments and a wider range of syntactic and semantic phenomena. We show across seven reading-time and acceptability judgment experiments that NPI illusions can be reliably switched “on” and “off”, depending on the amount of time from when the potential licensor is processed until the NPI is encountered. But we also find that the same profile does not extend to agreement illusions. This contrast suggests that the mechanisms responsible for switching the NPI illusion on and off are not shared across all illusions. We argue that the contrast reflects changes over time in the encoding of the semantic/pragmatic representations that can license NPIs. Just as optical illusions have been informative about the visual system, selective linguistic illusions are informative not only about the nature of the access mechanisms, but also about the nature of the encoding mechanisms.