Faulty Blocks Research Articles

Sharding-Based Proof-of-Stake Blockchain Protocols: Key Components & Probabilistic Security Analysis

Blockchain technology has been gaining great interest from a variety of sectors including healthcare, supply chain, and cryptocurrencies. However, Blockchain suffers from a limited ability to scale (i.e., low throughput and high latency). Several solutions have been proposed to tackle this. In particular, sharding has proved to be one of the most promising solutions to Blockchain's scalability issue. Sharding can be divided into two major categories: (1) Sharding-based Proof-of-Work (PoW) Blockchain protocols, and (2) Sharding-based Proof-of-Stake (PoS) Blockchain protocols. The two categories achieve good performances (i.e., good throughput with a reasonable latency), but raise security issues. This article focuses on the second category. In this paper, we start by introducing the key components of sharding-based PoS Blockchain protocols. We then briefly introduce two consensus mechanisms, namely PoS and practical Byzantine Fault Tolerance (pBFT), and discuss their use and limitations in the context of sharding-based Blockchain protocols. Next, we provide a probabilistic model to analyze the security of these protocols. More specifically, we compute the probability of committing a faulty block and measure the security by computing the number of years to fail. We achieve a number of years to fail of approximately 4000 in a network of 4000 nodes, 10 shards, and a shard resiliency of 33%.

Rebirth-FTL: Lifetime Optimization via Approximate Storage for NAND Flash Memory

The lifetime of NAND flash cells significantly degrades with feature-size reductions and multilevel cell technology. On the other hand, we have more and more approximate data, such as images and videos that are more error tolerant than regular data like text. In this article, we propose Rebirth-FTL, which reuses faulty blocks that contain uncorrectable errors to store approximate data for lifetime optimization. Rebirth-FTL effectively manages two spaces, namely, the approximate space and the normal space, with an efficient address translator, a coordinated garbage collection, and a differential wear leveler. In addition, we develop an migration times restriction (MTR) policy to restrict the movement of the approximate data in the approximate space. We also develop a scheme to pass approximate information from userland to kernel space in Linux. Finally, a lifetime model is presented for lifetime analysis. Our experimental results show that Rebirth-FTL can extend the lifetime by 41.63% on average.

Comparative evaluation of two different doses of intravenous dexmedetomidine infusion for sedation in patients undergoing lower abdominal general surgical procedures under spinal anesthesia

BACKGROUND: Spinal anesthesia is the most popular regional anesthesia technique for lower abdominal surgeries. The failure of many spinal anesthesia techniques is more due to inadequate sedation and anxiolysis than technically faulty blocks. This study was designed to determine the appropriate dose of intravenous dexmedetomidine maintainance infusion to provide adequate sedation for spinal anesthesia. METHODS: A prospective, randomized, controlled double-blind study was carried out on 75 patients aged 18-60 years with ASA I and ASA II physical status who were scheduled for elective lower abdominal surgery under spinal anesthesia. Before the spinal anesthesia, all study participants were given an initial loading dose of 0.5 µg/kg dexmedetomidine infusion. Participants were randomly divided into three groups for maintenance drug infusion, Group A (to receive dexmedetomidine infusion at 0.2 µg/kg/hr), Group B (to receive dexmedetomidine infusion at 0.4 µg/kg/hr) and Group C to receive an intravenous infusion of normal saline during surgery. The Ramsay Sedation Scale (RSS) score, duration of analgesia, hemodynamic variables and occurrence of adverse events were monitored in all patients. RESULTS: Dexmedetomidine group had increased RSS score in intraoperative period and upto first 30 minutes in postoperative period compared to control group . Time to request for first analgesic was prolonged and incidence of shivering and PONV in postoperative period was less in group B than group A. The hemodynamic parameters, Respiratory parameters were not statistically significant among group A and group B. CONCLUSION: We conclude that intravenous administration of dexmedetomidine0.5 µg/kg loading dose followed by 0.4 µg/kg/hr as maintenance infusion is the optimum dose to produce sedation during spinal anesthesia with an additional advantage of increased duration of analgesia and reduced postoperative sideeffects .

Sparse modeling and monitoring for industrial processes using sparse, distributed principal component analysis

Driven by the strong demand for sparsity in dimensional reduction techniques, a sparse modeling and monitoring approach based on sparse, distributed principal component analysis (SDPCA) is proposed to achieve sparsity. To this end, the data set is first divided into highly correlated blocks (HCBs) and one remainder block (RB) on the basis of the mutual-information-based correlation matrix. From this, the sparse loading vectors for the HCBs are obtained using the PCA models, while for the RB, it is obtained using the sparse PCA model. It is worth noting that the sparsity in SDPCA enables the sparse loading vectors to produce interpretable principal components, which keeps the correlations between the highly correlated variables and achieves the sparsity for the weakly correlated ones. Moreover, to fully appreciate the interpretation of the sparse principal components, a fault diagnosis strategy named blockwise contribution plots is proposed by first determining the faulty block, and then, identifying the faulty variables. Compared with PCA and SPCA, the proposed SDPCA detects more faulty samples and gives more accurate diagnosis results.

Modelling of seismicity in southern pakistan using GIS techniques

This study is aimed to elucidate individual fault response and peculiar earthquake characteristics in complex seismotectonic environment of southern Pakistan (Balochistan, Sindh and frontal offshore areas). The southern Pakistan is a seismic-melange wherein earthquake prone sources are diversified and closely associated with active plate margins. The spatial patterns of seismicity are significant in reckoning seismic potential of active fault lineaments in intraplate cohorts of Arabian, Eurasian and Indian plates. The tectonic earthquakes during the period of 325 B.C to February 2020 are compiled in a catalog. This updated catalog has been thoroughly processed by standard procedures necessary for magnitude coherency, main shocks declustering, magnitude completeness etc. Since, the faulty blocks are extending beyond international borders, a wide region is outlined for cataloging and thorough screening of fault lines. The fault lineaments are digitized after geo-referencing of structural and tectonic maps. A rigorous effort is made to review literature to gather allied data sets of plate kinematics, GPS constraints across faulty blocks and slip-sense during major events. Individual fault lines are examined carefully to discriminate seismicity yield by considering their geometry and influence of seismotectonic settings. The seismicity characteristics of fault lines are used to ascribe ‘seismicity index’ that helped to rank potential faults from I (least active) to V (highly active). Kernel density maps are prepared to allure vulnerable pockets of the fault lineaments for specific magnitude classes. Seismicity Index and Kernel density models are significant to analyze spatial changes in potential magnitude strength which may be pertinent for urban planners and developers to design earthquake resistant buildings in study area.

Toward Fault-Tolerant Deadlock-Free Routing in HyperSurface-Embedded Controller Networks

HyperSurfaces (HSFs) consist of structurally reconfigurable metasurfaces whose electromagnetic properties can be changed via a software interface, using an embedded miniaturized network of controllers. With the HSF controllers, interconnected in an irregular, near-Manhattan geometry, we propose a robust, deterministic Fault-Tolerant (FT), deadlock- and livelock-free routing protocol where faults are contained in a set of disjointed rectangular regions called faulty blocks. The proposed FT protocol can support an unbounded number of faulty nodes as long as nodes outside the faulty blocks are connected. Simulation results show the efficacy of the proposed FT protocol under various faulty node distribution scenarios.

Fault Tolerance Technique Offlining Faulty Blocks by Heap Memory Management

As dynamic random access memory (DRAM) cells continue to be scaled down for higher density and capacity, they have more faults. Thus, DRAM reliability becomes a major concern in computer systems. Previous studies have proposed many techniques preserving the reliability in various system components, such as DRAM internal, memory controller, caches, and operating systems. By reviewing the techniques, we identified the following two considerations: First, it is possible to recover faults with reasonable overhead at high fault rate only if the recovery unit is fine-grained. Second, since hardware modification requires additional cost in the employment of a technique, a pure software-based recovery technique is preferable. However, in the existing software-based recovery technique, the recovery unit is too coarse-grained to tolerate the high fault rate. In this article, we propose a pure software-based recovery technique with fine-granularity. Our key idea is based on heap segments being managed by the system library with variable-sized chunks to handle dynamic allocation in user applications. In our technique, faulty blocks in pages are offlined by marking them as allocated chunks. Thus, not only fault-free pages but also the remaining clean blocks in faulty pages are allowed to be usable space. Our technique is implemented by modifying the operating system and the system library. Since hardware assistance is unnecessary in the implementation, we evaluated our method on a real machine. Our evaluation results show that our technique has negligible performance overhead at high bit error rate (BER) 5.12e-5, which a hardware-based recovery technique could not tolerate without unacceptable area overhead. Also, at the same BER, our method provides 5.22× usable space, compared with page-offline, which is the state-of-the-art pure software-based technique.

Latency, Throughput and Power Aware Adaptive NoC Routing on Orthogonal Convex Faulty Region

Reliability of a Network-on-Chip (NoC) relies vastly upon the efficiency of handling faults. Faults those lead to trouble during on-chip communication process are basically of two types namely soft and hard. Here, hard faults are considered. Hard faults may be caused due to failure of links, routers, or other processing units. These are mainly dealt with fault-tolerant routing algorithms or by employing redundant hardware. Multiple faulty nodes are being avoided by acquiring region-based approaches. Most of the fault-tolerant routing techniques are designed on homogeneous faulty regions where some active nodes also act as deactivated nodes to build the region homogeneous. On the other hand, adaptive routing on nonhomogeneous faulty regions increases load on its boundary and most of them does not assure deadlock freeness. This paper proposes a deadlock-free adaptive fault-tolerant NoC routing named F-Route-NoC-Mesh (FRNM) ignoring any virtual channel on orthogonal convex faulty regions. Contributions of this work focus on balancing network traffic by assuming a virtual faulty block boundary and routing packets through this virtual boundary. Destination does not exist within that virtual faulty block regions to reduce load on the boundary of orthogonal faulty regions. Thus, this work is aimed at acquiring proper incorporation of procedures being able to reach fault-tolerant degree, routing efficiency and performance enhancement. Using the proposed algorithm (FRNM), a fault block model-based approach is developed. Significant improvements of average latency (43.37% to 60.44%), average throughput (4.18% to 90.81%) and power consumption (5.93% to 33.28%) are achieved over the state-of-the-art by using a cycle accurate simulator.

Early Identification of Critical Blocks: Making Replicated Distributed Storage Systems Reliable Against Node Failures

In large-scale replicated distributed storage systems consisting of hundreds to thousands of nodes, node failures are not rare and can cause data blocks to lose their replicas and become faulty. A simple but effective approach to prevent data loss from the node failures, i.e., ensuring reliability, is to shorten the identification time of the node failures and faulty blocks, which is determined by both timeouts and check intervals for node states. However, to maintain low repair network traffic, the identification time is actually relatively long and even dominates repair processes of critical blocks. In this paper, we propose a novel scheme, named RICK, to explore the potential in the identification time, and thus improve data reliability of replicated distributed storage systems while maintaining a low repair cost. First, by introducing an additional replica state, critical blocks (with two or more lost replicas) have individual short timeouts while sick blocks (with only one lost replica) preserve the long timeouts. Second, by replacing the static check intervals for node states with adaptive ones, the check intervals and the identification time of critical blocks are further shortened, which improves data reliability. Meanwhile, due to the low ratio of critical blocks in all faulty blocks, the repair network traffic remains low. The results from our simulation and prototype implementation show that RICK improves data reliability of replicated distributed storage systems by a factor of up to 14 in terms of mean time to data loss. Meanwhile, the extra repair network traffic caused by RICK is less than 1.5 percent of the total network traffic for data repairs.

A Self-Repairing Digital System with High-Quality Scalability and Fault Coverage

In any fault tolerant or BIST system the primary goal is to covenant with faults that arise in the indented system. The proposed system using genetic algorithm to optimize the performance and area of given circuit. This approach is supple for combinational circuit design. The use of four spare cells simplifies the operation of the active block in the current system; it needs more space to establish itself so it is considered as overhead. The proposed method of fault detection and correction for logical errors using genetic algorithm decreases the area overhead. Detection of Fault in the memory unit through BIST implementation increases the speed but replacing the existing faulty block with fault free block degrades the fault analyzing capabilities. Utmost care has on all the works implemented for the process of minimizing the error in different digital process. Therefore, with the new scope of proposing the method of reducing the error flow for the application of medical field, aeronautical, satellite broadcasting is described very efficiently in this paper. The simulation results of the fault tolerant and self-repairing method using genetic algorithm is presented.

Optimizing RAID/SSD controllers with lifetime extension for flash-based SSD array

Flash-based SSD RAID arrays are increasingly being deployed in data centers. Compared with HDD arrays, SSD arrays drastically enhance storage density and I/O performance, and reduce power and rack space. Nevertheless, SSDs suffer aging issues. Though prior studies have been conducted to address this disadvantage, effective techniques of RAID/SSD controllers are urgently needed to extend the lifetime of SSD arrays. In this paper, we for the first time apply approximate storage via the interplay of RAID and SSD controllers to optimize the lifespan of SSD arrays. Our basic idea is to reuse faulty blocks (those contain pages with uncorrectable errors) to store approximate data (which can tolerate more errors). By relaxing the integrity of flash blocks, we observed that the endurance of NAND flash memory can be significantly boosted, thereby providing huge potentials to significantly extend the lifetime of SSDs. Based on this observation, we propose the use of an efficient space management scheme for data allocation and FTL strategies by coordinating the interplay of RAID and SSD controllers to optimize the lifetime of SSD arrays. We implemented a prototype, called FreeRAID, based on an SSD array simulator. Our experiments show that we can significantly increase the lifetime by up to 2.17× compared with conventional SSD-based RAID arrays.

A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip

In 2D mesh Network on Chips (NoCs), fault-tolerant algorithms usually deactivate healthy nodes to form rectangular or convex fault blocks. However, the deactivated nodes can possibly form an available tunnel in a faulty block. We propose a method to discover these tunnels, and propose a fault-tolerant routing algorithm to route messages through such paths such that the overall communication performance is improved. In addition, the algorithm is deadlock-free by prohibiting some turns. Simulation results demonstrate that the reuse of the sacrificed nodes in fault blocks can significantly reduce the average message latency.

Localization of faulty multi-output unit in discrete device

The matrix method for localization of a faulty block that was proposed earlier by the present author was considered as applied to a discrete device with multi-output blocks At that, the question of reducing the amount of the test hardware was solved by constructing appropriately the matrix of block outputs. An algorithm for such construction was given.

NoC-based fault-tolerant cache design in chip multiprocessors

Advances in technology scaling increasingly make emerging Chip MultiProcessor (CMP) platforms more susceptible to failures that cause various reliability challenges. In such platforms, error-prone on-chip memories (caches) continue to dominate the chip area. Also, Network-on-Chip (NoC) fabrics are increasingly used to manage the scalability of these architectures. We present a novel solution for efficient implementation of fault-tolerant design of Last-Level Cache (LLC) in CMP architectures. The proposed approach leverages the interconnection network fabric to protect the LLC cache banks against permanent faults in an efficient and scalable way. During an LLC access to a faulty block, the network detects and corrects the faults, returning the fault-free data to the requesting core. Leveraging the NoC interconnection fabric, designers can implement any cache fault-tolerant scheme in an efficient, modular, and scalable manner for emerging multicore/manycore platforms. We propose four different policies for implementing a remapping-based fault-tolerant scheme leveraging the NoC fabric in different settings. The proposed policies enable design trade-offs between NoC traffic (packets sent through the network) and the intrinsic parallelism of these communication mechanisms, allowing designers to tune the system based on design constraints. We perform an extensive design space exploration on NoC benchmarks to demonstrate the usability and efficacy of our approach. In addition, we perform sensitivity analysis to observe the behavior of various policies in reaction to improvements in the NoC architecture. The overheads of leveraging the NoC fabric are minimal: on an 8-core, 16-cache-bank CMP we demonstrate reliable access to LLCs with additional overheads of less than 3% in area and less than 7% in power.

Smart Reliable Network-on-Chip

In this paper, we present a new network-on-chip (NoC) that handles accurate localizations of the faulty parts of the NoC. The proposed NoC is based on new error detection mechanisms suitable for dynamic NoCs, where the number and position of processor elements or faulty blocks vary during runtime. Indeed, we propose online detection of data packet and adaptive routing algorithm errors. Both presented mechanisms are able to distinguish permanent and transient errors and localize accurately the position of the faulty blocks (data bus, input port, output port) in the NoC routers, while preserving the throughput, the network load, and the data packet latency. We provide localization capacity analysis of the presented mechanisms, NoC performance evaluations, and field-programmable gate array synthesis.

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels

Fault-tolerant routing is usually used to provide reliable on-chip communication for many-core processors. This paper focuses on a special class of algorithms that do not use virtual channels. One of the major challenges is to keep the network deadlock free in the presence of faults, especially those locating on network edges. State-of-the-art solutions address this problem by either disabling all nodes of the faulty network edges or including all faults into one faulty block. Therefore, a large number of fault-free nodes will be sacrificed. To address this problem, the proposed ZoneDefense routing not only includes faults into convex faulty blocks but also spreads the faulty blocks' position information in corresponding columns. The nodes, which know the position of faulty blocks, form the defense zones. Therefore, packets can find the faulty blocks and route around them in advance. Exploiting the defense zones, the proposed ZoneDefense routing could tolerate many more faults with significantly reduced sacrificed fault-free nodes compared with the state-of-the-art algorithms. Furthermore, the ZoneDefense routing does not degrade the network performance in the absence of faults, and could get similar performance as its counterparts in the presence of faults.

Adaptive Fault-Tolerant Routing in 2D Mesh with Cracky Rectangular Model

This paper mainly focuses on routing in two-dimensional mesh networks. We propose a novel faulty block model, which is cracky rectangular block, for fault-tolerant adaptive routing. All the faulty nodes and faulty links are surrounded in this type of block, which is a convex structure, in order to avoid routing livelock. Additionally, the model constructs the interior spanning forest for each block in order to keep in touch with the nodes inside of each block. The procedure for block construction is dynamically and totally distributed. The construction algorithm is simple and ease of implementation. And this is a fully adaptive block which will dynamically adjust its scale in accordance with the situation of networks, either the fault emergence or the fault recovery, without shutdown of the system. Based on this model, we also develop a distributed fault-tolerant routing algorithm. Then we give the formal proof for this algorithm to guarantee that messages will always reach their destinations if and only if the destination nodes keep connecting with these mesh networks. So the new model and routing algorithm maximize the availability of the nodes in networks. This is a noticeable overall improvement of fault tolerability of the system.

A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip

This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indicate how packets must detour thefaulty block. The most recent routing algorithm on this approach is Message-Route (Holsmark and Kumar J Inf Sci Eng 23:1649---1662, 2007) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. Moreover, an FPGA implementation of the proposed algorithm is also discussed.

Fault diagnosis of continuous annealing processes using a reconstruction-based method

The continuous annealing process line (CAPL) has complex process characteristics, such as strong correlation of a large number of process variables and interconnected multi-subsystems and multiple operation zones. Practitioners are concerned with typical process faults, such as strip-break and roll-slippage, whose effects are often confined in a specific zone. Considering the large-scale process characteristics and fault characteristics, a multi-block fault diagnosis method is proposed. A novel reconstruction-based block contribution (RBBC) is first proposed in order to diagnose the faulty block. The reconstruction-based variable contribution (RBVC) within a block is also proposed to determine the faulty variables. The proposed RBBC–RBVC hierarchical scheme is applied successfully to a real CAPL on two fault cases. A finite state machine is utilized to diagnose strip-break and reconstructed combined index is studied to diagnose roll-slippage.

Fault-tolerant image filter design using particle swarm optimization

This article describes a mixed constrained image filter design with fault tolerance using particle swarm optimization (PSO) on a reconfigurable processing array. There may be some faulty configurable logic blocks (CLBs) in a reconfigurable processing array. The proposed method with PSO autonomously synthesizes a filter fitted to the reconfigurable device with some faults in order to optimize the complexity and power of the circuit, and the signal delay in both the CLBs and the wires. An image filter for noise reduction is experimentally synthesized to verify the validity of our method. By evolution, the quality of the optimized image filter on a reconfigurable device with a few faults is almost same as that on a device with no faults.