Hardware Faults Research Articles

Hardware automatic test scheme and intelligent analyze application based on machine learning model

Abstract Hardware testing has always been the core of hardware development, and improving the performance and efficiency of hardware testing is very important for hardware development. Because hardware quality management is insufficient, many large hardware tools were developed using manual workshop technology in the past and could hardly be maintained. This can lead to the cancellation of the project, causing major personnel and property losses. Improving hardware quality and ensuring security are very complex problems. Hardware testing is usually conducted through manual and automatic testing, and the limitations of manual testing are increasingly obvious. So hardware automatic testing technology has attracted people’s attention in recent years. It has become an important research direction in the field hardware testing and can overcome many problems of traditional testing methods. Strict test rules, based on standards and scores, provide a fully automated test process. With the continuous improvement of network technology, the functions and scope of hardware are constantly enriched and expanded. With the acceleration of hardware updates and development, this has brought a heavy burden to the previous hardware testing work. The purpose of this article was to study the application of machine learning technology in the field of hardware automatic testing and provide an appropriate theoretical basis for optimizing testing methods. This article introduced the research methods of hardware automatic testing technology, introduced three automatic testing framework models, and summarized the application of machine learning in hardware testing. It included hardware security and reliability analysis, hardware defect prediction, and source-based research. Then, this article studied the defect prediction model and machine learning algorithm and constructed a hardware defect prediction model based on machine learning based on the theory. First, the data were preprocessed, and then, the Stacking method was used to build a comprehensive prediction model, and four prediction results evaluation indicators were established. In the experiment part, the defect prediction results of the hardware automatic test model were studied. The results showed that the hardware defect prediction model based on machine learning had higher accuracy, recall rate, F_measure and area under curve. Compared with other models, the average accuracy of the hardware defect prediction model in this article was 0.092 higher, which was more suitable for automatic hardware testing and analysis.

Few‐shot cross‐receiver radio frequency fingerprinting identification based on feature separation

AbstractRadio frequency fingerprint identification (RFFI) is a widely used technique for authenticating equipment. It identifies transmitters by extracting hardware defects found in the RF front end. Recent research has focused on the impact of transmitters and wireless channels on radio frequency fingerprint (RFF). Most work is based on the same receiver assumption, while the influence of the receiver on RFF remains unresolved. This paper focuses on the impact of receiver hardware characteristics on RFF and proposes a few‐shot cross‐receiver RFFI method based on feature separation. Data augmentation with noise addition and simulated channels addresses sparse sample issues and enhances the model's robustness to channel variations. Simultaneously, feature separation is realized by reducing the correlation between transmitter and receiver features through classification loss and similarity loss. We evaluate the proposed approaches using a large‐scale WiFi dataset. It is shown that when a trained transmitter classifier is deployed on new receivers with only 30 samples per trained transmitter, the average identification accuracy of the proposed method is 83.6%. This accuracy is 9.45% higher than the baseline method without considering transmitter hardware influence. After fine‐tuning, the average identification accuracy can reach 98.25%.

Hardware Failure Prediction Modes Powered by Artificial Intelligence

With the increase of the system scale and complexity of modern computer systems and electronic equipment, the physical components (hardware) in computer or electronic equipment are damaged, the performance is reduced or the normal operation of computer and electronic systems is greatly increased due to various reasons. Detecting and predicting hardware faults in time is the key to ensure system stability and reliability. Hardware failure prediction technology based on artificial intelligence (AI) can effectively predict potential hardware failures by analyzing historical data, monitoring equipment operating status in real time, and reducing system downtime and maintenance costs. This paper reviews the current hardware fault prediction methods based on artificial intelligence, discusses the common algorithms, technical challenges, and application scenarios, and looks forward to the future development direction of this field.

Position-Based ANN Impedance Control for A Three-Fingered Robot Hand

A feedforward ANN was previously developed for recognition of two objects i.e. a spongy ball and a plastic bottle but was verified through simulation only. In this work, the feasibility of the ANN model is tested by applying it to the robot’s impedance control which takes the exerted force at the finger as input while resulting in an output for the selection rule of the impedance stiffness parameter, named 𝐾𝑑. From the results, the different object textures can be distinguished by the ANN where the absolute peak values of measured rate force during contact with the ball reached 0.15 N and a slightly higher value of 0.32 N for the bottle. 𝐾𝑑 values were found to switch between 1000 and 250 based on the ANN outputs for the ball and bottle, respectively, thus affecting the dynamics of the fingertip through modified position reference of the fingertip. However, it is also observed that the object was incorrectly classified in some moments when the exerted force was not sufficient due to the weak grasp of the object. This shows that the nonlinear factor from the hardware defects needs to be considered when refining the 𝐾𝑑 selection rule in future studies.

ALPRI-FI: A Framework for Early Assessment of Hardware Fault Resiliency of DNN Accelerators

ALPRI-FI: A Framework for Early Assessment of Hardware Fault Resiliency of DNN Accelerators

Resource allocation for practical phase shift STAR-RIS enabled MISO-NOMA wireless network with non ideal hardware

This study investigates the sum secrecy rate SRsum of a simultaneous transmission and reflection reconfigurable intelligent surface (STAR-RIS)-enabled multiple input single-output (MISO) non-orthogonal multiple access (NOMA) downlink network with non-ideal hardware defects (HWDs) at the transceivers. Earlier STAR-RIS studies assumed an ideal phase shift model, with each element reflect and transmit the signal without regard to its phase shift. The proposed practical phase shift model accounts for the phase-dependent amplitude variation in the reflection and transmission (RAT) coefficients. The goal is to maximize the SRsum through an alternating optimization (AO) iterative algorithm, leverages a classical semidefinite relaxation (SDR) for beamformer vector design (BVD), and employs an interior point method (IPM) to calculate NOMA power allocation factors αt,αr. The analysis focuses on the evaluation of the SRsum in scenarios with eavesdroppers, under the consideration of both ideal and practical phase shift cases. The study examines the impact of different non-ideal HWDs on the SRsum of the system and provides insights into vulnerabilities and limitations arising from these effects.

Use of a correction factor for the pulsecal subroutine used for pulse width calibration and identifying a hardware fault causing pulsecal to fail

Stroboscopic nutation has proved to be invaluable for pulse width calibration (P. S. C. Wu and G. Otting, Rapid pulse length determination in high-resolution NMR, J. Magn. Reson. 2005, 176, 115–119), though it is not without its issues. Herein it is proposed that a correction factor be applied to correct for the inaccuracy of the method which is dependent on the NMR system including the probe, observed nucleus, sample type set (solvent, concentration, ionic strength, etc.), temperature, etc. Poor performance of the stroboscopic nutation experiment was also found to be a harbinger of a serious hardware problem.

Techniques for detecting and masking faults in semantic segmentation applications

Semantic segmentation of images is essential for many applications including autonomous driving and modern DNNs now achieve high accuracy. Automotive systems are safety critical systems and in turn they must comply with safety standards, requiring at least hardware fault detection capability. Small embedded applications also require some level of fault tolerance, while operating with a tight power budget. In this paper, we first present a detailed analysis of the effects of faults using Google’s DeepLabV3+ network processing an industrial data-set. Further to that, two techniques to mitigate hardware faults are proposed. The first one is a symptom-based fault detection algorithm shown to detect >99% of critical faults with zero false positives and a compute overhead of 0.2%. The second one is a simpler technique, using a clipped ReLU activation function, to quickly mask over 99% of the critical faults in the activation values.

Enhanced Compiler Technology for Software-based Hardware Fault Detection

Software-Implemented Hardware Fault Tolerance (SIHFT) is a modern approach for tackling random hardware faults of dependable systems employing solely software solutions. This work extends an automatic compiler-based SIHFT hardening tool called ASPIS, enhancing it with novel protection mechanisms and overhead-reduction techniques, also providing an extensive analysis of its compliance with the non-trivial workload of the open-source Real-Time Operating System FreeRTOS. A thorough experimental fault-injection campaign on an STM32 board shows how the system achieves remarkably high tolerance to single-event upsets and a comparison between the SIHFT mechanisms implemented summarises the trade-off between the overhead introduced and the detection capabilities of the various solutions.

Finite-Time Fault-Tolerant Formation Control for Distributed Multi-Vehicle Networks With Bearing Measurements

This paper addresses a bearing-only formation tracking problem in robotic networks by considering exogenous disturbances and actuator faults. In contrast to traditional position-based coordination strategies, the bearing-only coordinated movements of the unmanned vehicles only rely on the neighboring bearing information. This feature can be utilized to reduce the sensing requirements in the hardware implementation. A gradient-descent protocol is first developed to achieve the desired coordination within a prespecified settling time, where the unknown disturbances are considered in the vehicle dynamics, then the bound of formation tracking error is guaranteed by the Lyapunov approach. In case of damage to the actuators (e.g., motors) in some of the vehicles during the task, fault-tolerant analysis of the proposed controller is provided to ensure the success of the task in extreme environments. Furthermore, the proposed bearing-based method is extended to deal with general linear systems, which can be applied to a wider range of robotic platforms. Finally, numerical simulations and lab-based experiments using unmanned ground vehicles are conducted to validate the effectiveness of the proposed strategy. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Note to Practitioners</i> —The aim of this paper is to develop and design a practical bearing-only formation control approach for multi-vehicle systems. Many real-world complex tasks can be solved by multiple unmanned aerial and ground vehicles being connected by a communication network. This paper has proposed a formation tracking scheme for networked multi-vehicle systems that only relies on the relative bearing information of the neighboring vehicles. Closed-loop stability of the scheme and finite-time convergence of the tracking error have been established using the Lyapunov stability approach. The proposed method ensures the robustness and fault-tolerance of the multi-vehicle system against hardware faults or exogenous disturbances. A systematic set of guidelines on how to apply the proposed strategy in practice is also provided for the control practitioners in the form of an algorithm. In order to demonstrate the feasibility and usefulness of the proposed coordination scheme, numerical simulations and lab-based hardware experiments were conducted. Potential applications of the proposed scheme include search and rescue, security surveillance and cooperative exploration.

Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators

General Matrix Multiplication (GEMM) is a computationally expensive operation that is used in many applications such as machine learning. Hardware accelerators are increasingly popular for speeding up GEMM computation, with Tiled Matrix Multiplication (TMUL) in recent Intel processors being an example. Unfortunately, the TMUL hardware is susceptible to errors, necessitating online error detection. The Algorithm-based Error Detection (ABED) technique is a powerful technique to detect errors in matrix multiplications. In this article, we consider implementation of an ABED technique that integrates seamlessly with the TMUL hardware to minimize performance overhead. Unfortunately, rounding errors introduced by floating-point operations do not allow a straightforward implementation of ABED in TMUL. Previously an error bound was considered for addressing rounding errors in ABED. If the error detection threshold is set too low, it will a trigger false alarm, while a loose bound will allow errors to escape detection. In this article, we propose an adaptive error threshold that takes into account the TMUL input values to address the problem of false triggers and error escapes and provide a taxonomy of various error classes. This threshold is obtained from theoretical error analysis but is not easy to implement in hardware. Consequently, we relax the threshold such that it can be easily computed in hardware. While ABED ensures error-free computation, it does not guarantee full coverage of all hardware faults. To address this problem, we propose an algorithmic pattern generation technique to ensure full coverage for all hardware faults. To evaluate the benefits of our proposed solution, we conducted fault injection experiments and show that our approach does not produce any false alarms or detection escapes for observable errors. We conducted additional fault injection experiments on a Deep Neural Network (DNN) model and find that if a fault is not detected, it does not cause any misclassification.

Investigating the impact of transient hardware faults on deep learning neural network inference

SummarySafety‐critical applications, such as autonomous vehicles, healthcare, and space applications, have witnessed widespread deployment of deep neural networks (DNNs). Inherent algorithmic inaccuracies have consistently been a prevalent cause of misclassifications, even in modern DNNs. Simultaneously, with an ongoing effort to minimize the footprint of contemporary chip design, there is a continual rise in the likelihood of transient hardware faults in deployed DNN models. Consequently, researchers have wondered the extent to which these faults contribute to DNN misclassifications compared to algorithmic inaccuracies. This article delves into the impact of DNN misclassifications caused by transient hardware faults and intrinsic algorithmic inaccuracies in safety‐critical applications. Initially, we enhance a cutting‐edge fault injector, TensorFI, for TensorFlow applications to facilitate fault injections on modern DNN non‐sequential models in a scalable manner. Subsequently, we analyse the DNN‐inferred outcomes based on our defined safety‐critical metrics. Finally, we conduct extensive fault injection experiments and a comprehensive analysis to achieve the following objectives: (1) investigate the impact of different target class groupings on DNN failures and (2) pinpoint the most vulnerable bit locations within tensors, as well as DNN layers accountable for the majority of safety‐critical misclassifications. Our findings regarding different grouping formations reveal that failures induced by transient hardware faults can have a substantially greater impact (with a probability up to 4 higher) on safety‐critical applications compared to those resulting from algorithmic inaccuracies. Additionally, our investigation demonstrates that higher order bit positions in tensors, as well as initial and final layers of DNNs, necessitate prioritized protection compared to other regions.

Exploring Hardware Fault Impacts on Different Real Number Representations of the Structural Resilience of TCUs in GPUs

The most recent generations of graphics processing units (GPUs) boost the execution of convolutional operations required by machine learning applications by resorting to specialized and efficient in-chip accelerators (Tensor Core Units or TCUs) that operate on matrix multiplication tiles. Unfortunately, modern cutting-edge semiconductor technologies are increasingly prone to hardware defects, and the trend to highly stress TCUs during the execution of safety-critical and high-performance computing (HPC) applications increases the likelihood of TCUs producing different kinds of failures. In fact, the intrinsic resiliency to hardware faults of arithmetic units plays a crucial role in safety-critical applications using GPUs (e.g., in automotive, space, and autonomous robotics). Recently, new arithmetic formats have been proposed, particularly those suited to neural network execution. However, the reliability characterization of TCUs supporting different arithmetic formats was still lacking. In this work, we quantitatively assessed the impact of hardware faults in TCU structures while employing two distinct formats (floating-point and posit) and using two different configurations (16 and 32 bits) to represent real numbers. For the experimental evaluation, we resorted to an architectural description of a TCU core (PyOpenTCU) and performed 120 fault simulation campaigns, injecting around 200,000 faults per campaign and requiring around 32 days of computation. Our results demonstrate that the posit format of TCUs is less affected by faults than the floating-point one (by up to three orders of magnitude for 16 bits and up to twenty orders for 32 bits). We also identified the most sensible fault locations (i.e., those that produce the largest errors), thus paving the way to adopting smart hardening solutions.

Adaptable and Interpretable Framework for Anomaly Detection in SCADA-based industrial systems

In this paper, we introduce an Adaptable and Interpretable Framework for Anomaly Detection (AID) designed for industrial systems utilizing IoT data streams on top of well-established SCADA systems. AID leverages dynamic conditional probability distribution modeling to capture the normal operation of dynamic systems and isolate the root causes of anomalies at the level of individual inputs. The self-supervised framework dynamically updates parameters of underlying model, allowing it to adapt to non-stationarity. AID interprets anomalies as significant deviations from conditional probability, encompassing interactions as well as both spatial and temporal irregularities by exposing them as features. Crucially, AID provides dynamic operating limits to integrate with existing alarm handling mechanisms in SCADA-based IoT systems. Two industrial-scale case studies demonstrate AID’s capabilities. The first study showcases AID’s effectiveness on energy storage system, adapting to changes, setting context-aware limits for SCADA, and ability to leverage a physics-based model. The second study monitors battery module temperatures, where AID identifies hardware faults, emphasizing its relevance to energy storage safety. A benchmark evaluation on real data shows that AID delivers comparable performance to other self-learning adaptable anomaly detection methods, with the significant advancement in diagnostic capabilities for improved system reliability and performance.

Fine-Grained Radio Frequency Fingerprint Recognition Network Based on Attention Mechanism.

With the rapid development of the internet of things (IoT), hundreds of millions of IoT devices, such as smart home appliances, intelligent-connected vehicles, and wearable devices, have been connected to the network. The open nature of IoT makes it vulnerable to cybersecurity threats. Traditional cryptography-based encryption methods are not suitable for IoT due to their complexity and high communication overhead requirements. By contrast, RF-fingerprint-based recognition is promising because it is rooted in the inherent non-reproducible hardware defects of the transmitter. However, it still faces the challenges of low inter-class variation and large intra-class variation among RF fingerprints. Inspired by fine-grained recognition in computer vision, we propose a fine-grained RF fingerprint recognition network (FGRFNet) in this article. The network consists of a top-down feature pathway hierarchy to generate pyramidal features, attention modules to locate discriminative regions, and a fusion module to adaptively integrate features from different scales. Experiments demonstrate that the proposed FGRFNet achieves recognition accuracies of 89.8% on 100 ADS-B devices, 99.5% on 54 Zigbee devices, and 83.0% on 25 LoRa devices.

Computer Hardware Fault Detection based on Machine Learning

In order to solve the computer fault detection problem of machine learning, the author proposes a computer hardware fault detection problem based on machine learning. The method combines mutual information and class separability to analyze their relationship, which improves classification accuracy. This study presents an adaptive machine learning technique for the adaptive fusion of data from multiple sources. In addition, the mCRC algorithm seeks for the optimal feature subset using the enhanced forward floating search method, thereby overcoming the limitation that the mRMR algorithm does not specify how to determine the final feature subset. The classification accuracy of the mCRC algorithm is approximately 1% better than that of the mRMR algorithm, and the size of the final feature subset of the mCRC algorithm is 22% smaller than that of the final subset of the mRMR algorithm. Conclusion: the ReMAE algorithm has a higher rate of accurate failure prediction.

Lightning: Leveraging DVFS-induced Transient Fault Injection to Attack Deep Learning Accelerator of GPUs

Graphics Processing Units (GPU) are widely used as deep learning accelerators because of its high performance and low power consumption. Additionally, it remains secure against hardware-induced transient fault injection attacks, a classic type of attacks that have been developed on other computing platforms. In this work, we demonstrate that well-trained machine learning models are robust against hardware fault injection attacks when the faults are generated randomly. However, we discover that these models have components, which we refer to as sensitive targets, that are vulnerable to faults. By exploiting this vulnerability, we propose the Lightning attack, which precisely strikes the model’s sensitive targets with hardware-induced transient faults based on the Dynamic Voltage and Frequency Scaling (DVFS). We design a sensitive targets search algorithm to find the most critical processing units of Deep Neural Network (DNN) models determining the inference results, and develop a genetic algorithm to automatically optimize the attack parameters for DVFS to induce faults. Experiments on three commodity Nvidia GPUs for four widely-used DNN models show that the proposed Lightning attack can reduce the inference accuracy by 69.1% on average for non-targeted attacks, and, more interestingly, achieve a success rate of 67.9% for targeted attacks.

Super-resolution non-line-of-sight imaging based on temporal encoding.

Non-line-of-sight (NLOS) imaging techniques have the ability to reconstruct objects beyond line-of-sight view, which would be useful in a variety of applications. In transient NLOS techniques, a fundamental problem is that the time resolution of imaging depends on the single-photon timing resolution (SPTR) of a detector. In this paper, a temporal super-resolution method named temporal encoding non-line-of-sight (TE-NLOS) is proposed. Specifically, by exploiting the spatial-temporal correlation among transient images, high-resolution transient images can be reconstructed through modulator encoding. We have demonstrated that the proposed method is capable of reconstructing transient images with a time resolution of 20 picoseconds from a detector with a limited SPTR of approximately nanoseconds. In systems with low time jitter, this method exhibits superior accuracy in reconstructing objects compared to direct detection, and it also demonstrates robustness against miscoding. Utilizing high-frequency modulation, our framework can reconstruct accurate objects with coarse-SPTR detectors, which provides an enlightening reference for solving the problem of hardware defects.

Ring artifacts correction for computed tomography image using unsupervised contrastive learning

Objective. Computed tomography (CT) is a widely employed imaging technology for disease detection. However, CT images often suffer from ring artifacts, which may result from hardware defects and other factors. These artifacts compromise image quality and impede diagnosis. To address this challenge, we propose a novel method based on dual contrast learning image style transformation network model (DCLGAN) that effectively eliminates ring artifacts from CT images while preserving texture details. Approach. Our method involves simulating ring artifacts on real CT data to generate the uncorrected CT (uCT) data and transforming them into strip artifacts. Subsequently, the DCLGAN synthetic network is applied in the polar coordinate system to remove the strip artifacts and generate a synthetic CT (sCT). We compare the uCT and sCT images to obtain a residual image, which is then filtered to extract the strip artifacts. An inverse polar transformation is performed to obtain the ring artifacts, which are subtracted from the original CT image to produce a corrected image. Main results. To validate the effectiveness of our approach, we tested it using real CT data, simulated data, and cone beam computed tomography images of the patient’s brain. The corrected CT images showed a reduction in mean absolute error by 12.36 Hounsfield units (HU), a decrease in root mean square error by 18.94 HU, an increase in peak signal-to-noise ratio by 3.53 decibels (dB), and an improvement in structural similarity index by 9.24%. Significance. These results demonstrate the efficacy of our method in eliminating ring artifacts and preserving image details, making it a valuable tool for CT imaging.

Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories

Low Density Parity Check (LDPC) codes are used in 5G systems for traffic channels due to their excellent error correction capability for long sequences, and the Min-Sum algorithm is widely applied in practical implementations of LDPC decoders due to its low complexity. If the decoder is implemented on a SRAM-based field-programmable gate array (SRAM-FPGA), the radiation-induced single-event upsets (SEUs) can affect the operation of the LDPC decoder by corrupting the configuration memory, which can change the circuit functionality and will not be corrected unless the FPGA is reconfigured. Therefore, protection of LDPC decoders with low overhead is an important problem, especially for resource-limited on-board space systems. In this paper, an efficient Duplicate With Comparison (DWC) protection scheme is proposed based on the different distribution of the parity check sum of the LDPC decoder in the error-free case and the faulty case. In particular, the check sum accumulation number and threshold are optimized to achieve high detection probability with short delay. FPGA based implementation and hardware fault injection experiments are conducted to evaluate the performance of the proposed schemes. Experimental results show that, the effect of SEUs on the LDPC decoder can be completely eliminated by the proposed scheme with 2 times computational overhead and 1.69 times power consumption overhead compared to the unprotected decoder.