Faults In Combinational Logic Research Articles

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic

This paper presents a new recovery scheme for dealing with short-to-long duration transient faults in combinational logic. The new scheme takes earlier into account results of concurrent error detection (CED) mechanisms, and then it is able to perform shorter recovery latencies than existing similar strategy. The proposed scheme also requires less memory resources to save input contexts of combinational logic blocks. In addition, this work also proposes a taxonomy of CED techniques. It allows pointing out which are the necessary recovery resources as well as identifying which are the types of CED mechanisms that can be used with the new recovery scheme of this paper. The effectiveness of the proposed scheme was evaluated through electrical-level simulations. For all short-to-long duration transient-fault injections, it was never slower than state-of-art similar strategy, and indeed its recovery latency was faster for 34 % of the simulated faulty scenarios.

Random pattern testability of memory address logic

An analytical method is described for determining the random pattern testability of faults in combinational logic feeding the address inputs of embedded memories. Difference information from replicated copies of embedding logic is used to determine the probability of detecting any fault in the upstream of either a read or write port address decoder. The method can be used with minor extensions to existing detection probability tools such as the cutting algorithm.

Fault diagnosis assistant : Edward T. Purcell. IEEE Circuits Devices Mag., 47 (January 1988)

This article describes a first implementation of a knowledge-based system for interactive support of test engineers in gate-level troubleshooting offaulty VLSZ chips, by offering advice on the next-best internal probe point for an electron-beam test probe system. The current OPS83 production system implementation of the fault diagnosis assistant (FDA) recommends an efficient sequence of probes at internal nodes that progressively localizes and identifies single stuck-at faults in combinational logic or combinational partitions within setlscan logic. Unlike the system-specific approaches implemented by most fault diagnosis expert systems, FDA implements the strategically correct (but more challenging) first-principles approach to fault diagnosis. This model-based diagnostic methodology is based primarily on using model knowledge of the system's structure (connectivity file) and function (normal, design-prescribed behavior) of the system's primitive components. The model-based approach has the potential to offer excellent fault coverage for large classes of custom design systems, although it can be difficult to implement because of the need to reason with accurate fault-free system simulation data. The prototype version of FDA has been exercised over several simulated examples of single stuck-at faults in simple test combinational circuits. This initial diagnostic capability is the foundation for future versions of FDA whose objectives will include coverage of multiple, nonclassical faults in sequential VLSI circuits.

Fault diagnosis assistant (VLSI chips)

A description is given of a first implementation of a knowledge-based system for interactive support of test engineers in gate-level troubleshooting of faulty VLSI chips. The fault diagnosis assistant (FDA) offers advice on the next-best internal probe point for an electron-beam test probe system. The current OPS83 production system implementation of FDA recommends an efficient sequence of probes at internal nodes that progressively localizes and identified single stuck-at faults in combinational logic or combinational partitions within set/scan logic. Its model-based diagnostic methodology is based primarily on using model knowledge of the system's structure (connectivity file) and function (normal, design-prescribed behavior) of the system's primitive components. Some FDA implementation details and pattern-matching efficiency considerations, initial FDA timing experiments, and future extensions to FDA are considered.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Testability-Driven Random Test-Pattern Generation

This paper presents ESPRIT, an automatic test pattern generation (ATPG) system for testing single stuck-at faults in combinational logic. ESPRIT generates test patterns by performing fault simulation on random patterns derived from nonuniformly distributed input signal probabilities. The system computes input signal probabilities that minimize a testability cost function. Using ESPRIT, we have observed orders-of-magnitude reduction in the number of random trials required to obtain a given fault coverage.