Fault-tolerant Multistage Interconnection Networks Research Articles

Design of Fault Tolerant Shuffle Exchange Gamma Interconnection Network Layouts

Advancement in technology has resulted in increased computing power with the use of multiple processors within a system. These multiple processors need to communicate with each other and with memory modules. Multistage Interconnection Networks (MINs) provide a communication medium in such multi-processor systems by interconnecting a number of processors and memory modules. Besides, MINs also provide a cost effective substitute to costly crossbars in parallel computers and switching systems in telephone industry. This paper introduces two new fault-tolerant MINs named as Shuffle Exchange Gamma Interconnection Networks (SEGIN-1 and SEGIN-2). SEGIN-1 and SEGIN-2 can be obtained by altering Shuffle Exchange Network with one extra stage (SEN+) and provide two disjoint paths similar to it. Performance of SEGIN-1 and SEGIN-2 has been evaluated in terms of alternative paths, disjoint paths, reliability and hardware cost, and is compared with some very famous MINs like Shuffle Exchange Network (SEN), Shuffle Exchange Network with one extra stage (SEN+), Shuffle Exchange Network with two extra stage (SEN+2), Extra Stage Cube (ESC) and Gamma Interconnection Network (GIN). Results suggest that SEGINs surpass all the compared networks; hence, the proposed designs seem to be suitable for implementing practical interconnection networks.

4DGIN-3: A new design layout of 4-disjoint gamma interconnection network

Various multistage interconnection networks have been proposed in the literature and utilized in commercial projects. But there exists a further scope of improvement and the need for new fault tolerant multistage interconnection networks, which can withstand multiple switch or link failures. Recently, design layouts of four disjoint paths gamma interconnection networks have been proposed and named as 4DGIN-1 and 4DGIN-2, respectively. These proposed design layouts of 4DGINs produce different number of alternative paths ranging from five to seven for different tag values. In this paper, a new variant, viz., 4DGIN-3 is introduced, which generates four disjoint paths similar to 4DGIN-1 and 4DGIN-2 but with a total of six number of alternative paths for every tag value. This feature of the proposed design, in turn, results in same reliability for each tag value at various assumed reliability of switching elements despite having the similar topology and hardware cost as that of the earlier 4DGINs. A comparison of the proposed design with the existing 4DGINs has also been provided in this paper.

Fault Tolerant Interconnection Network Design

ABSTRACTAdvances in parallel and distributed computing have made interconnection networks a potential networking alternative to meet the growing demands of high-performance computing. Multiple processors need to communicate with each other and with memory modules. Multi-stage interconnection networks (MINs) provide a communication medium in multi-processor system as they interconnect a number of processors and memory modules. Design of MIN has to meet ever better performance by providing more disjoint paths, low hardware cost, higher reliability, and rerouting capabilities tolerating any switch/link failures. New architecture of fault tolerant multistage interconnection network layout is proposed. Proposed layout is a multipath MIN providing four disjoint paths for all the source and destination pairs. It has full access and dynamic rerouting property under any switch/link failures. Collision problems are effectively handled by this dynamic rerouting capability by automatically changing their routing path during any switch/link faults. Proposed network design is highly reliable with higher fault-tolerant capability than other interconnection networks topologies. Evaluated terminal pair reliability for new layout is found to be higher than other MINs.

Evaluating failure rate of fault-tolerant multistage interconnection networks using Weibull life distribution

Fault-tolerant multistage interconnection networks (MINs) play a vital role in the performance of multiprocessor systems where reliability evaluation becomes one of the main concerns in analyzing these networks properly. In many cases, the primary objective in system reliability analysis is to compute a failure distribution of the entire system according to that of its components. However, since the problem is known to be NP-hard, in none of the previous efforts, the precise evaluation of the system failure rate has been performed. Therefore, our goal is to investigate this parameter for different fault-tolerant MINs using Weibull life distribution that is one of the most commonly used distributions in reliability. In this paper, four important groups of fault-tolerant MINs will be examined to find the best fault-tolerance techniques in terms of failure rate; (1) Extra-stage MINs, (2) Parallel MINs, (3) Rearrangeable non-blocking MINs, and (4) Replicated MINs. This paper comprehensively analyzes all perspectives of the reliability (terminal, broadcast, and network reliability). Moreover, in this study, all reliability equations are calculated for different network sizes.

Fault Tolerant Routing in Irregular ModifiedShuffle Network

Interconnection networks (IN) play very important role in various parallel processing applications. The connectivity pattern used in interconnection networks greatly determines the performance of the system. Multistage Interconnection Network is also an IN. The interconnection pattern used also determines the fault tolerance of the network. This paper introduces a new irregular fault tolerant multistage interconnection network named Irregular Modified Shuffle Network (IMSN). IMSN is analyzed in terms of fault tolerance and it has been observed that IMSN provides more alternate paths than existing networks such as Improved Four Tree Network (IFTN), Modified Alpha Network (MALN) and New Irregular Augmented Shuffle Network (NIASN).

Pars network: A multistage interconnection network with fault-tolerance capability

Interconnection networks are used for communication between nodes in multi-processor systems as well as super-systems. These systems require effective communication between the processor and memory blocks and therefore, interconnection networks are considered as the heart of the parallel processing and multi-processor systems. Multistage interconnection networks (MINs) are the main option for use in supercomputer environments that consist of thousands of processing elements. In this paper, a regular class of fault-tolerant MINs named Pars network along with its routing algorithm are presented. Analytical results demonstrate that the Pars network outperforms known regular networks, namely ABN, ASEN, EGN, and IEGN in terms of cost, fault-tolerance, terminal reliability, mean time to failure, and permutation capability.

Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection Networks

Multistage interconnection networks (MINs) are widely used for reliable data communication in a tightly coupled large-scale multiprocessor system. High reliability of MINs can be achieved using fault tolerance techniques. The fault tolerance is generally achieved by disjoint paths available through multiple connectivity options. The gamma interconnection network (GIN) is a class of fault tolerant MINs providing alternate paths for source---destination node pairs. Various 2-disjoint and 3-disjoint GIN architectures have been presented in the literature. In this paper, two new designs of 4-disjoint paths multistage interconnection networks, called 4-disjoint gamma interconnection networks (4DGIN-1 and 4DGIN-2) are proposed. The proposed 4DGINs provide four disjoint paths for each source---destination pair and can tolerate three switches/link failures in intermediate interconnection layers. Proposed designs are highly reliable GIN with higher fault-tolerant capability than other gamma networks at low cost. Terminal pair reliabilities of proposed designs and various other 2-disjoint and 3-disjoint GINs are evaluated, analyzed and compared. Reliability values of proposed designs are found higher.

Improved extra group network: a new fault-tolerant multistage interconnection network

Supersystems are shown to provide enough computational power to solve complex problems on a real-time basis. In all these systems, the computational parallelism is obtained from multiple processors. Multistage interconnection networks (MINs) play a vital role on the performance of these multiprocessor systems. This paper introduces a new fault-tolerant MIN named as improved extra group network (IEGN). IEGN is designed by existing extra group (EGN) network, which is a regular multipath network with limited fault tolerance. IEGN provides four times more paths between any source---destination pairs compared with EGN. The performance of IEGN has been evaluated in terms of permutation capability, fault tolerance, reliability, path length, and cost. It has also been proved that the IEGN can achieve better results in terms of fault tolerance, reliability, path length and cost-effectiveness, in comparison to known networks, namely, EGN, augmented baseline network, augmented shuffle-exchange network, fault-tolerant double tree, Benes network, and Replicated MIN.

Improved Meta-Flattened Butterfly Multistage Interconnection Network

processing is efficient form of information processing which means to implement high performance computing systems. A communication network that links processors and memory modules determines the efficiency of these parallel systems. To provide the required connectivity and performance at reasonable cost, an interconnection network is used. Hence, multistage interconnection networks are a good way for providing communication in these systems. This paper includes two major contributions. Firstly, it describes the flaws of existing Meta- flattened Network (MFN). Secondly, a new Fault-tolerant multistage interconnection network named as Improved Meta- Flattened Butterfly Network (IMFN) is proposed that can improve the routing problems of Meta-flattened Network. Performance of the proposed network is analyzed in terms of cost and permutation possibility. The performance comparison of the IMFN with MFN shows that the proposed network IMFN gives much better performance in terms of permutation.

Evaluation of Two Terminal Reliability of Fault-tolerant Multistage Interconnection Networks

This paper iOntroduces a new method based on multi-decomposition for predicting the two terminal reliability of fault-tolerant multistage interconnection networks. The method is well supported by an efficient algorithm which runs polynomially. The method is well illustrated by taking a network consists of eight nodes and twelve links as an example. The proposed method is found to be simple, general and efficient and thus is as such applicable to all types of fault-tolerant multistage interconnection networks. The results show this method provides a greater accurate probability when applied on fault-tolerant multistage interconnection networks. Reliability of two important MINs are evaluated by using the proposed method.

Modified Fault Tolerant Double Tree Network-2

Interconnection networks are constructed to provide interprocess communication. These Networks are compared on the basis of Fault tolerance, Reliability, Path length and cost effectiveness. An irregular class of Fault Tolerant Multistage Interconnection Network (MIN) called Modified Four Double Tree Network-2 (MFDOT-2) is proposed.MFDOT-2 is constructed on the basis of FDOT-2 [1]. The Reliability, Path length and cost effectiveness of some popular irregular class of Multistage Interconnection Networks along with proposed MFDOT-2 is also analyzed.

Design and Reliability Analysis of a Class of Irregular Fault-Tolerant Multistage Interconnection Networks

llel processing can be used to design high performance computing systems. In a parallel computer inter-connecting processors and linking them efficiently to the memory modules is not an easy task. Therefore, there is a requirement of an interconnection network that provides the desired connectivity and performance at minimum cost. Multistage interconnection networks (MINs) provide cost-effective, high- bandwidth communication between processors and/or memory modules in comparison to bus and crossbar interconnection networks. In this paper a new irregular MIN named IFTN (Improved Four Tree Network) has been proposed. The performance of IFTN has been measured in terms of reliability and cost. It has been proved that the proposed network IFTN provides much better fault-tolerance and reliability at lesser cost In Comparison To Four Trees.

A Routing Scheme for a New Irregular Baseline Multistage Interconnection Network

Parallel processing is an efficient form of information processing system, which emphasizes the exploitation of concurrent events in the computing process. To achieve parallel processing it’s required to develop more capable and cost-effective systems. In order to operate more efficiently a network is required to handle large amount of traffic. Multi-stage Interconnection Network plays a vital role on the performance of these multiprocessor systems. In this paper an attempt has been made to analyze the characteristics of new class of Irregular Fault-Tolerant Multistage Interconnection network named as Irregular Modified Baseline Multistage Interconnection network IMABN and an efficient routing procedure has been defined to study the fault-tolerance of the network. Fault-Tolerance in an interconnection network is very important for its continuous operation over a relatively long period of time. Fault-Tolerance is an ability of the network to operate in presence of multiple faults. The behavior of the Proposed IMABN has been analyzed and compared with regular network MABN under fault free conditions and in presence of faults. In IMABN there are six possible paths between source and destinations where as MABN has only four. Thus the proposed IMABN is more Fault-tolerant than existing regular Modified Augmented Baseline multistage interconnection network (MABN).

Fast Interconnections: A Case Tool for Developing Fault-tolerant Multi-stage Interconnection Networks

Multi–stage interconnection networks (MIN) can be designed to achieve fault tolerance and collision solving by providing a set of disjoint paths. In this paper, we have discussed a tool designed for developing fault-tolerant MIN. The designed tool is one of its own kind and will help the user in developing 2 and 3-disjoint path networks. The 1–Fault tolerant MIN provides two disjoint paths to solve collision situation. The java technology has been used to design the tool and have been tested on different software platform.

Design and Reliability Analysis of New Fault-Tolerant Irregular Multistage Interconnection Network

Parallel processing is an efficient form of information processing system,which emphasizes the exploitation of concurrent events in the computing process. To achieve parallel processing it’s required to develop more capable and cost-effective systems.In order to operate more efficiently a network is required to handle large amount of traffic. Multi-stage Interconnection Network plays a vital role on the performance of these multiprocessor systems.In this paper an attempt has been made to analyze the characteristics of a new class of irregular fault-tolerant multistage interconnection network named as irregular modified augmented baseline network (IMABN). IMABN can provide ‘Full access’ capability in presence of multiple faults. The reliability of interconnection networks and their ability to continue operating despite failures are major concerns in determining the overall system performance. In this paper reliability of the proposed IMABN have been calculated and compared in terms of the Upper and Lower bounds of mean time to failure (MTTF). Reliability and Cost study shows that IMABNs achieve a significant improvement over Modified Augmented Baseline Network (MABN).

Reliability and path length analysis of irregular fault tolerant multistage interconnection network

In this paper reliability and path length analysis of irregular Multistage Interconnection Networks have been presented. We have examined FT(Four Tree)[8],MFT(Modified Four Tree)[2],NFT(New Four Tree)[4],IFT(improved Four Tree)[5],IASN(Irregular Augmented Shuffle)[14] and IIASN(Improved Irregular Augmented Shuffle)[3] networks in which the number of switches in each stage are different in numbers and also have express links[11]. Using upper and lower bounds[7][13][15] for larger networks, the reliability[9] in terms of mean time to failure of all these networks are evaluated and compared with each other. Each source is connected to destination with one or multiple paths with varying path lengths in a network. The path length analysis of all these networks is also analyzed in this paper. A path length[8] algorithm for IIASN network is also propose

The deflection self-routing Delta network: a dynamically fault-tolerant high-radix multistage interconnection network

High-radix multistage interconnection networks are popular interconnection technologies for parallel supercomputers and cluster computers. In this paper, we presented a new dynamically fault-tolerant high-radix multistage interconnection network using a fully-adaptive self-routing. To devise the fully-adaptive self-routing for recovering the misrouting around link faults in such network, we introduce an abstract algebraic analysis of the topological structure of the high-radix Delta network. The presented interconnection network provides multiple paths by using all the links of all the stages of the network. We also present a mathematical analysis of the reliability of the interconnection network for quantitative comparison against other networks. The MTTF of 64×64 network proposed is 2.2 times greater than that of the cyclic Banyan network. The hardware cost of the proposed network is half that of the cyclic Banyan network and the 2D ring-Banyan network.

Irregular Class of Multistage Interconnection Network in Parallel Processing

A major problem in designing a large-scale parallel and distributed system was the construction of an Interconnection Network (IN) to provide inter-processor communication. One of the biggest issues in the development of such a system was the development of an effective architecture and algorithms that have high reliability, give good performance (even in the presence of faults), low cost, low average path length, higher number of passes of request and a simple control. In this study, a new class of Irregular Fault Tolerant Multistage Interconnection Network (MIN) called Improved Four Tree (IFT) is introduced. Algorithms for computing the cost and permutations passable in the presence and absence of fault are developed for the analysis of various networks with proposed network.

Designing a New Class of Fault Tolerant Multistage Interconnection Networks

This paper proposes a technique to modify a Multistage Interconnection Network (MIN) to augment it with fault tolerant capabilities. The augmented MIN is referred to as Enhanced MIN (E-MIN). The technique employed for construction of E-MIN is compared with the two known physical fault tolerance techniques, namely, extra staging and chaining. EMINs are found to be more generic than extra staged networks and less expensive than chained networks. The EMIN realizes all the permutations realizable by the original MIN. The routing strategies under faulty and fault free conditions are shown to be very simple in the case of E-MINs.

Modeling and analysis of fault tolerant multistage interconnection networks

Performance and reliability are two of the most crucial issues in today's high-performance instrumentation and measurement systems. High speed and compact density multistage interconnection networks (MINs) are widely-used subsystems in different applications. New performance models are proposed to evaluate a novel fault tolerant MIN arrangement, thereby assuring performance and reliability with high confidence level. A concurrent fault detection and recovery scheme for MINs is considered by rerouting over redundant interconnection links under stringent real-time constraints for digital instrumentation such as sensor networks. A switch architecture for concurrent testing and diagnosis is proposed. New performance models are developed and used to evaluate the compound effect of fault tolerant operation (inclusive of testing, diagnosis, and recovery) on the overall throughput and delay. Results are shown for single transient and permanent stuck-at faults on links and storage units in the switching elements. It is shown that performance degradation due to fault tolerance is graceful while performance degradation without fault recovery is unacceptable.