Fault-tolerant Logical Gates Research Articles

Cross-Cap Defects and Fault-Tolerant Logical Gates in the Surface Code and the Honeycomb Floquet Code

We consider the Z2 toric code, surface code, and Floquet code defined on a nonorientable surface, which can be considered as families of codes extending Shor’s nine-qubit code. We investigate the fault-tolerant logical gates of the Z2 toric code in this setup, which corresponds to e↔m exchanging symmetry of the underlying Z2 gauge theory. We find that nonorientable geometry provides a new way for the emergent symmetry to act on the code space, and discover the new realization of the fault-tolerant Hadamard gate of the two-dimensional surface code with a single cross cap connecting the vertices nonlocally along a slit, dubbed a nonorientable surface code. This Hadamard gate can be realized by a constant-depth local unitary circuit modulo nonlocality caused by a cross cap. Via folding, the nonorientable surface code can be turned into a bilayer local quantum code, where the folded cross cap is equivalent to a bilayer twist terminated on a gapped boundary and the logical Hadamard only contains local gates with intralayer couplings when being away from the cross cap, as opposed to the interlayer couplings on each site needed in the case of the folded surface code. We further obtain the complete logical Clifford gate set for a stack of nonorientable surface codes and similarly for codes defined on Klein-bottle geometries. We then construct the honeycomb Floquet code in the presence of a single cross cap, and find that the period of the sequential Pauli measurements acts as a HZ logical gate on the single logical qubit, where the cross cap enriches the dynamics compared with the orientable case. We find that the dynamics of the honeycomb Floquet code is precisely described by a condensation operator of the Z2 gauge theory, and illustrate the exotic dynamics of our code in terms of a condensation operator supported at a nonorientable surface. Published by the American Physical Society 2024

Topological Order, Quantum Codes, and Quantum Computation on Fractal Geometries

We investigate topological order on fractal geometries embedded in $n$ dimensions. In particular, we diagnose the existence of the topological order through the lens of quantum information and geometry, i.e., via its equivalence to a quantum error-correcting code with a macroscopic code distance or the presence of macroscopic systoles in systolic geometry. We first prove a no-go theorem that $\mathbb{Z}_N$ topological order cannot survive on any fractal embedded in 2D. For fractal lattice models embedded in 3D or higher spatial dimensions, $\mathbb{Z}_N$ topological order survives if the boundaries of the interior holes condense only loop or membrane excitations. Moreover, for a class of models containing only loop or membrane excitations, and are hence self-correcting on an $n$-dimensional manifold, we prove that topological order survives on a large class of fractal geometries independent of the type of hole boundaries. We further construct fault-tolerant logical gates using their connection to global and higher-form topological symmetries. In particular, we have discovered a logical CCZ gate corresponding to a global symmetry in a class of fractal codes embedded in 3D with Hausdorff dimension asymptotically approaching $D_H=2+\epsilon$ for arbitrarily small $\epsilon$, which hence only requires a space-overhead $\Omega(d^{2+\epsilon})$ with $d$ being the code distance. This in turn leads to the surprising discovery of certain exotic gapped boundaries that only condense the combination of loop excitations and gapped domain walls. We further obtain logical $\text{C}^{p}\text{Z}$ gates with $p\le n-1$ on fractal codes embedded in $n$D. In particular, for the logical $\text{C}^{n-1}\text{Z}$ in the $n^\text{th}$ level of Clifford hierarchy, we can reduce the space overhead to $\Omega(d^{n-1+\epsilon})$. Mathematically, our findings correspond to macroscopic relative systoles in fractals.

Universal fault-tolerant quantum computing with stabilizer codes

The quantum logic gates used in the design of a quantum computer should be both universal, meaning arbitrary quantum computations can be performed, and fault-tolerant, meaning the gates keep errors from cascading out of control. A number of no-go theorems constrain the ways in which a set of fault-tolerant logic gates can be universal. These theorems are very restrictive, and conventional wisdom holds that a universal fault-tolerant logic gate set cannot be implemented natively, requiring us to use costly distillation procedures for quantum computation. Here, we present a general framework for universal fault-tolerant logic with stabiliser codes, together with a no-go theorem that reveals the very broad conditions constraining such gate sets. Our theorem applies to a wide range of stabiliser code families, including concatenated codes and conventional topological stabiliser codes such as the surface code. The broad applicability of our no-go theorem provides a new perspective on how the constraints on universal fault-tolerant gate sets can be overcome. In particular, we show how non-unitary implementations of logic gates provide a general approach to circumvent the no-go theorem, and we present a rich landscape of constructions for logic gate sets that are both universal and fault-tolerant. That is, rather than restricting what is possible, our no-go theorem provides a signpost to guide us to new, efficient architectures for fault-tolerant quantum computing.

Decoder for the Triangular Color Code by Matching on a Möbius Strip

The color code is remarkable for its ability to perform fault-tolerant logic gates. This motivates the design of practical decoders that minimise the resource cost of color-code quantum computation. Here we propose a decoder for the planar color code with a triangular boundary where we match syndrome defects on a nontrivial manifold that has the topology of a M\"{o}bius strip. A basic implementation of our decoder used on the color code with hexagonal lattice geometry demonstrates a logical failure rate that is competitive with the optimal performance of the surface code, $\sim p^{\alpha \sqrt{n}}$, with $\alpha \approx 6 / 7 \sqrt{3} \approx 0.5$, error rate $p$, and $n$ the code length. Furthermore, by exhaustively testing over five billion error configurations, we find that a modification of our decoder that manually compares inequivalent recovery operators can correct all errors of weight $\le (d-1) /2$ for codes with distance $d \le 13$. Our decoder is derived using relations among the stabilizers that preserve global conservation laws at the lattice boundary. We present generalisations of our method to depolarising noise and fault-tolerant error correction, as well as to Majorana surface codes, higher-dimensional color codes and single-shot error correction.

Finding the disjointness of stabilizer codes is NP-complete

The disjointness of a stabilizer code is a quantity used to constrain the level of the logical Clifford hierarchy attainable by transversal gates and constant-depth quantum circuits. We show that for any positive integer constant $c$, the problem of calculating the $c$-disjointness, or even approximating it to within a constant multiplicative factor, is NP-complete. We provide bounds on the disjointness for various code families, including the Calderbank-Shor-Steane codes, concatenated codes, and hypergraph product codes. We also describe numerical methods of finding the disjointness, which can be readily used to rule out the existence of any transversal gate implementing some non-Clifford logical operation in small stabilizer codes. Our results indicate that finding fault-tolerant logical gates for generic quantum error-correcting codes is a computationally challenging task.

Error rates and resource overheads of repetition cat qubits

We estimate and analyze the error rates and the resource overheads of the repetition cat qubit approach to universal and fault-tolerant quantum computation. The cat qubits stabilized by two-photon dissipation exhibit an extremely biased noise where the bit-flip error rate is exponentially suppressed with the mean number of photons. In a recent work, we suggested that the remaining phase-flip error channel could be suppressed using a 1D repetition code. Indeed, using only bias-preserving gates on the cat-qubits, it is possible to build a universal set of fault-tolerant logical gates at the level of the repetition cat qubit. In this paper, we perform Monte-Carlo simulations of all the circuits implementing the protected logical gates, using a circuit-level error model. Furthermore, we analyze two different approaches to implement a fault-tolerant Toffoli gate on repetition cat qubits. These numerical simulations indicate that very low logical error rates could be achieved with a reasonable resource overhead, and with parameters that are within the reach of near-term circuit QED experiments.

Instantaneous braids and Dehn twists in topologically ordered states

A defining feature of topologically ordered states of matter is the existence of locally indistinguishable states on spaces with non-trivial topology. These degenerate states form a representation of the mapping class group (MCG) of the space, which is generated by braids of defects or anyons, and by Dehn twists along non-contractible cycles. These operations can be viewed as fault-tolerant logical gates in the context of topological quantum error correcting codes and topological quantum computation. Here we show that braids and Dehn twists can in general be implemented by a constant depth quantum circuit, with a depth that is independent of code distance $d$ and system size. The circuit consists of a constant depth local quantum circuit (LQC) implementing a local geometry deformation of the quantum state, followed by a permutation on (relabelling of) the qubits. The permutation requires permuting qubits that are separated by a distance of order $d$; it can be implemented by collective classical motion of mobile qubits or as a constant depth circuit using long-range SWAP operations (with a range set by $d$) on immobile qubits. Applying these results to certain non-Abelian quantum error correcting codes demonstrates how universal logical gate sets can be implemented on encoded qubits using only constant depth unitary circuits.

Triangular color codes on trivalent graphs with flag qubits

The color code is a topological quantum error-correcting code supporting a variety of valuable fault-tolerant logical gates. Its two-dimensional version, the triangular color code, may soon be realized with currently available superconducting hardware despite constrained qubit connectivity. To guide this experimental effort, we study the storage threshold of the triangular color code against circuit-level depolarizing noise. First, we adapt the Restriction Decoder to the setting of the triangular color code and to phenomenological noise. Then, we propose a fault-tolerant implementation of the stabilizer measurement circuits, which incorporates flag qubits. We show how information from flag qubits can be used in an efficient and scalable way with the Restriction Decoder to maintain the effective distance of the code. We numerically estimate the threshold of the triangular color code to be 0.2%, which is competitive with the thresholds of other topological quantum codes. We also prove that 1-flag stabilizer measurement circuits are sufficient to preserve the full code distance, which may be used to find simpler syndrome extraction circuits of the color code.

Fault-tolerant magic state preparation with flag qubits

Magic state distillation is one of the leading candidates for implementing universal fault-tolerant logical gates. However, the distillation circuits themselves are not fault-tolerant, so there is additional cost to first implement encoded Clifford gates with negligible error. In this paper we present a scheme to fault-tolerantly and directly prepare magic states using flag qubits. One of these schemes requires only three ancilla qubits, even with noisy Clifford gates. We compare the physical qubit and gate cost of our scheme to the magic state distillation protocol of Meier, Eastin, and Knill (MEK), which is efficient and uses a small stabilizer circuit. For low enough noise rates, we show that in some regimes the overhead can be improved by several orders of magnitude compared to the MEK scheme which uses Clifford operations encoded in the codes considered in this work.

Fault-tolerant gates via homological product codes

A method for the implementation of a universal set of fault-tolerant logical gates is presented using homological product codes. In particular, it is shown that one can fault-tolerantly map between different encoded representations of a given logical state, enabling the application of different classes of transversal gates belonging to the underlying quantum codes. This allows for the circumvention of no-go results pertaining to universal sets of transversal gates and provides a general scheme for fault-tolerant computation while keeping the stabilizer generators of the code sparse.

Low overhead Clifford gates from joint measurements in surface, color, and hyperbolic codes

One of the most promising routes towards fault-tolerant quantum computation utilizes topological quantum error correcting codes, such as the $\mathbb{Z}_2$ surface code. Logical qubits can be encoded in a variety of ways in the surface code, based on either boundary defects, holes, or bulk twist defects. However proposed fault-tolerant implementations of the Clifford group in these schemes are limited and often require unnecessary overhead. For example, the Clifford phase gate in certain planar and hole encodings has been proposed to be implemented using costly state injection and distillation protocols. In this paper, we show that within any encoding scheme for the logical qubits, we can fault-tolerantly implement the full Clifford group by using joint measurements involving a single appropriately encoded logical ancilla. This allows us to provide new low overhead implementations of the full Clifford group in surface and color codes. It also provides the first proposed implementations of the full Clifford group in hyperbolic codes. We further use our methods to propose state-of-the art encoding schemes for small numbers of logical qubits; for example, for code distances $d = 3,5,7$, we propose a scheme using $60, 160, 308$ (respectively) physical data qubits, which allow for the full logical Clifford group to be implemented on two logical qubits. To our knowledge, this is the optimal proposal to date, and thus may be useful for demonstration of fault-tolerant logical gates in small near-term quantum computers.

Disjointness of Stabilizer Codes and Limitations on Fault-Tolerant Logical Gates

Stabilizer codes are a simple and successful class of quantum error-correcting codes. Yet this success comes in spite of some harsh limitations on the ability of these codes to fault-tolerantly compute. Here we introduce a new metric for these codes, the disjointness, which, roughly speaking, is the number of mostly non-overlapping representatives of any given non-trivial logical Pauli operator. We use the disjointness to prove that transversal gates on error-detecting stabilizer codes are necessarily in a finite level of the Clifford hierarchy. We also apply our techniques to topological code families to find similar bounds on the level of the hierarchy attainable by constant depth circuits, regardless of their geometric locality. For instance, we can show that symmetric 2D surface codes cannot have non-local constant depth circuits for non-Clifford gates.

Gapped boundaries, group cohomology and fault-tolerant logical gates

This paper attempts to establish the connection among classifications of gapped boundaries in topological phases of matter, bosonic symmetry-protected topological (SPT) phases and fault-tolerantly implementable logical gates in quantum error-correcting codes. We begin by presenting constructions of gapped boundaries for the d-dimensional quantum double model by using d-cocycles functions (d≥2). We point out that the system supports m-dimensional excitations (m<d), which we shall call fluctuating charges, that are superpositions of point-like electric charges characterized by m-dimensional bosonic SPT wavefunctions. There exist gapped boundaries where electric charges or magnetic fluxes may not condense by themselves, but may condense only when accompanied by fluctuating charges. Magnetic fluxes and codimension-2 fluctuating charges exhibit non-trivial multi-excitation braiding statistics, involving more than two excitations. The statistical angle can be computed by taking slant products of underlying cocycle functions sequentially. We find that excitations that may condense into a gapped boundary can be characterized by trivial multi-excitation braiding statistics, generalizing the notion of the Lagrangian subgroup. As an application, we construct fault-tolerantly implementable logical gates for the d-dimensional quantum double model by using d-cocycle functions. Namely, corresponding logical gates belong to the dth level of the Clifford hierarchy, but are outside of the (d−1)th level, if cocycle functions have non-trivial sequences of slant products.

Universal Fault-Tolerant Gates on Concatenated Stabilizer Codes

It is an oft-cited fact that no quantum code can support a set of fault-tolerant logical gates that is both universal and transversal. This no-go theorem is generally responsible for the interest in alternative universality constructions including magic state distillation. Widely overlooked, however, is the possibility of non-transversal, yet still fault-tolerant, gates that work directly on small quantum codes. Here we demonstrate precisely the existence of such gates. In particular, we show how the limits of non-transversality can be overcome by performing rounds of intermediate error-correction to create logical gates on stabilizer codes that use no ancillas other than those required for syndrome measurement. Moreover, the logical gates we construct, the most prominent examples being Toffoli and controlled-controlled-Z, often complete universal gate sets on their codes. We detail such universal constructions for the smallest quantum codes, the 5-qubit and 7-qubit codes, and then proceed to generalize the approach. One remarkable result of this generalization is that any nondegenerate stabilizer code with a complete set of fault-tolerant single-qubit Clifford gates has a universal set of fault-tolerant gates. Another is the interaction of logical qubits across different stabilizer codes, which, for instance, implies a broadly applicable method of code switching.

Topological phases with generalized global symmetries

We present simple lattice realizations of symmetry-protected topological phases with $q$-form global symmetries where charged excitations have $q$ spatial dimensions. Specifically, we construct $d$ space-dimensional models supported on a $(d+1)$-colorable graph by using a family of unitary phase gates, known as multiqubit control-$Z$ gates in quantum information community. In our construction, charged excitations of different dimensionality may coexist and form a short-range entangled state which is protected by symmetry operators of different dimensionality. Nontriviality of proposed models, in a sense of quantum circuit complexity, is confirmed by studying protected boundary modes, gauged models, and corresponding gapped domain walls. We also comment on applications of our construction to quantum error-correcting codes, and discuss corresponding fault-tolerant logical gates.

Topological color code and symmetry-protected topological phases

We study $(d-1)$-dimensional excitations in the $d$-dimensional color code that are created by transversal application of the $R_{d}$ phase operators on connected subregions of qubits. We find that such excitations are superpositions of electric charges and can be characterized by fixed-point wavefunctions of $(d-1)$-dimensional bosonic SPT phases with $(\mathbb{Z}_{2})^{\otimes d}$ symmetry. While these SPT excitations are localized on $(d-1)$-dimensional boundaries, their creation requires operations acting on all qubits inside the boundaries, reflecting the non-triviality of emerging SPT wavefunctions. Moreover, these SPT-excitations can be physically realized as transparent gapped domain walls which exchange excitations in the color code. Namely, in the three-dimensional color code, the domain wall, associated with the transversal $R_{3}$ operator, exchanges a magnetic flux and a composite of a magnetic flux and loop-like SPT excitation, revealing rich possibilities of boundaries in higher-dimensional TQFTs. We also find that magnetic fluxes and loop-like SPT excitations exhibit non-trivial three-loop braiding statistics in three dimensions as a result of the fact that the $R_{3}$ phase operator belongs to the third-level of the Clifford hierarchy. We believe that the connection between SPT excitations, fault-tolerant logical gates and gapped domain walls, established in this paper, can be generalized to a large class of topological quantum codes and TQFTs.

The Design of Reliable Circuits Using Logic Redundancy

With the increasing demand for more durable products, the necessity of designing more resilient products is evident. When it comes to electronic systems, many strategies have been applied to enhance the durability and performance of the operating circuits. For a long time, the main focus was to develop increasingly reliable components, however, yield enhancement techniques may not be sufficient for future technologies. As a solution to this, redundancy strategies are being introduced in order to regain reliability of circuits even if the individual components are not as reliable as desired. The use of logic redundancy and series or parallel association of transistors is proposed as a strategy in the design of fault tolerant logic gates (that are the basic elements of many complex computing structures), such as NAND and NOR. Fault injection simulations show that the reliability of these gates in the presence of random stuck-at faults may be increased by our design approach and that the strategy is extensible to more elaborate circuits.

Polynomial-Time T-Depth Optimization of Clifford+T Circuits Via Matroid Partitioning

Most work in quantum circuit optimization has been performed in isolation from the results of quantum fault-tolerance. Here we present a polynomial-time algorithm for optimizing quantum circuits that takes the actual implementation of fault-tolerant logical gates into consideration. Our algorithm resynthesizes quantum circuits composed of Clifford group and T gates, the latter being typically the most costly gate in fault-tolerant models, e.g., those based on the Steane or surface codes, with the purpose of minimizing both T-count and T-depth. A major feature of the algorithm is the ability to resynthesize circuits with ancillae at effectively no additional cost, allowing space-time trade-offs to be easily explored. The tested benchmarks show up to 65.7% reduction in T-count and up to 87.6% reduction in T-depth without ancillae, or 99.7% reduction in T-depth using ancillae.

Scope of Reversible Engineering at Gate-Level : Fault - Tolerant Combinational Adders

Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.

New Design for Quantum Dots Cellular Automata to obtain Fault Tolerant Logic Gates

In this paper, we analyze fault tolerance properties of the Majority Gate, as the main logic gate for implementation with Quantum dots Cellular Automata (QCA), in terms of fabrication defect. Our results demonstrate the poor fault tolerance properties of the conventional design of Majority Gate and thus the difficulty in its practical application. We propose a new approach to the design of QCA-based Majority Gate by considering two-dimensional arrays of QCA cells rather than a single cell for the design of such a gate. We analyze fault tolerance properties of such Block Majority Gates in terms of inputs misalignment and irregularity and defect (missing cells) in assembly of the array. We present simulation results based on semiconductor implementation of QCA with an intermediate dimensional dot of about 5 nm in size as opposed to magnetic dots of greater than 100 nm or molecular dots of 2–5A. Our results clearly demonstrate the superior fault tolerance properties of the Block Majority Gate and its greater potential for a practical realization. We also show the possibility of designing fault tolerant QCA circuits by using Block Majority Gates.