Fault-tolerant Computer Systems Research Articles

Hybrid reliability modeling of fault-tolerant computer systems : Kishor Trivedi, Joanne Bechta Dugan, Robert Geist and Mark Smotherman. Comput. Electrical Engng11 (2/3), 87 (1984)

Hybrid reliability modeling of fault-tolerant computer systems : Kishor Trivedi, Joanne Bechta Dugan, Robert Geist and Mark Smotherman. Comput. Electrical Engng11 (2/3), 87 (1984)

The development of fault tolerant computer systems using dual processing techniques

The paper discusses ways of building a dual processed computer system to provide a highly reliable fault tolerant configuration. The need and justification for fault tolerant systems is discussed and the comparative availability that can be expected from single and dual configurations is calculated. Based on systems implemented by CAP, two of the most important types of dual processing systems are discussed: namely load sharing and continuous processing systems. The load sharing approach to fault tolerance is particularly important for transaction processing applications because it offers the opportunity to build a fault tolerant system for a cost close to that of a conventional single-computer system. An example based on CAP's system for the Durham Constabulary on Perkin-Elmer equipment is discussed. The continuous processing system described is based on CAPTEC, CAFs operating system for Digital Equipment Corporation computers, which provides a continuous processing system where the system continues uninterrupted on a single failure.

A Fault-Tolerant Multimicroprocessor-Based Computer System for Space-Based Signal Processing

Ensuring the reliability of processing modules on board a satellite would mean a significant reduction in communication bandwidth. The FASP system incorporates a number of software and hardware levels in a fault-tolerantdesign for high-performance applications.

Hybrid reliability modeling of fault-tolerant computer systems

Current technology allows sufficient redundancy in fault-tolerant computer systems to insure that the failure probability due to exhaustion of spares is low. Consequently, the major cause of failure is the inability to correctly detect, isolate, and reconfigure when faults are present. Reliability estimation tools must be flexible enough to accurately model this critical fault-handling behavior and yet remain computationally tractable. This paper discusses reliability modeling techniques based on a behavioral decomposition that provides tractability by separating the reliability model along temporal lines into nearly disjoint fault-occurrence and fault-handling submodels. An Extended Stochastic Petri Net (ESPN) model provides the needed flexibility for representing the fault-handling behavior, while a nonhomogeneous Markov chain accounts for the possibly non-Poisson fault-occurrence behavior. Since the submodels are separate, the ESPN submodel, in which all time constants are of the same order of magnitude, can be simulated. The nonhomogeneous Markov chain is solved analytically, and the result is a hybrid model. The method of coverage factors, used to combine the submodels, is generalized to more accurately reflect the fault-handling effectiveness within the fault-occurrence model. However, due to approximations made in the aggregation of the two submodels and inaccurate estimation of component failure rates and other model parameters, errors can still arise in the subsequent reliability predictions. The accuracy of the model predictions is evaluated analytically, and error bounds on the system reliability are produced. These modeling techniques have been implemented in the HARP (Hybrid Automated Reliability Predictor) program.

Virtual resource ring: Technique for decentralised resource management in fault-tolerant distributed computer systems

The paper first identifies design objectives for resource management in distributed computer systems. A resource-management mechanism that meets these objectives, the virtual resource ring (VRR), is then proposed and an implementation of the VRR on an actual distributed multiprocessor computer system is described. Finally, the proposed scheme is evaluated against the previously defined design objectives.

Fail-safe rapid-transit engineering ensures reliability, passenger safety : Gary A. Kravetz. Electronics 152 (17 May, 1984)

A new fail-safe computer system - the Fail-Safe 86 - will soon be installed in 45 stations of the Bay Area Rapid Transit (BART) District, in the San Francisco Bay area. The new system architecture - which uses standard, proven industrial components combined with a versatile real-time operating system - is fault-tolerant and combines modularity with reliability. The new Fail Safe 86 microcomputer software architecture and the Integrated Control System (ICS) are described.

Architecture Optimization of Aerospace Computing Systems

Simultaneous consideration of both performance and reliability issues is important in the choice of computer architectures for real-time aerospace applications. One of the requirements for such a fault-tolerant computer system is the characteristic of graceful degradation. A shared and replicated resources computing system represents such an architecture. In this paper, a combinatorial model is used for the evaluation of the instruction execution rate of a degradable, replicated resources computing system such as a modular multiprocessor system. Next, a method is presented to evaluate the computation reliability of such a system utilizing a reliability graph model and the instruction execution rate. Finally, this computation reliability measure, which simultaneously describes both performance and reliability, is applied as a constraint in an architecture optimization model for such computing systems.

A heuristic procedure for allocating tasks in fault‐tolerant distributed computer systems

AbstractOne way of achieving the increased levels of system reliability and availability demanded by critical computer‐based control systems is through the use of fault‐tolerant distributed computer systems. This article addresses the problem of allocating a set of m tasks among a set of n processors in a manner that will satisfy various task assignment, system capacity, and task scheduling constraints while balancing the workload across processors. We discuss problem background, problem formulation, and a known heuristic procedure for the problem. A new solution‐improving heuristic procedure is introduced, and computational experience with the heuristics is presented. With only a modest increase in the amount of computational effort, the new procedure is demonstrated to improve dramatically solution quality as well as obtain near‐optimal solutions to the test problems.

A Tree Structured Architecture for semantic gap reduction

The article proposes a new Tree-Structured-Architecture (TSA). The TSA is object-oriented, implements the notions of capability-based-addressing and the single-level-store, and it is particularly designed to narrow the semantic gap. It encourages modular programming and directly supports the concepts of tasks and inter-task communication, making it particularly suitable for multiprocessing and multiprogramming implementation.The TSA is implemented on a multi-resource, distributed, matrix-structured, reconfigurable, fault-tolerant computing system, proposed in this article. The system implements some ideas of the dynamic and the flexible architecture. The system possesses a high degree of regularity by implementing large amounts of identical units. The hardware is modular, permitting the addition or removal of groups of units, without a change in the system's software.

Parallel/series dependency and equivalence in generalized Markov's chains

In this paper the analytical solutions to generalized Parallel and Series Markov's Chains are presented. The states dependencies are derived and the condition of equivalence is considered. The results are analyzed with respect to fault tolerant computing system applications.

Availability modelling of multiprocessors

A model is developed for availability related computation of performance figures in multiprocessors. The paper explains how queueing networks can be used to give a flexible yet clear description of a system. An example based on the PRIME fault-tolerant computer system is also presented as an illustration.

Programmable Control of a Chemical Reactor Using a Fault Tolerant Computer

This paper discusses the operation of a chemical reactor and particularly the need for highly reliable instrumentation and control for critical processes. It describes the use of fault tolerance for the computer control to provide a level of reliability previously unachievable with standard computer control systems. The provision of highly reliable interface equipment to the reactor itself is described and approaches are presented for solving the problem of faults in the sensors and actuators. The paper discusses a specific example chemical reactor and the benefits that are achievable using a fault tolerant control computer system.

Fail-safe computer grows modularly: James B. Brinton. Electronics 167 (3 November 1981)

Fail-safe computer grows modularly: James B. Brinton. Electronics 167 (3 November 1981)

Highly Reliable Software for Use in Fail-Safe Control

This paper describes the practical development of highly reliable software used in a Fail-Safe Computer Control System. The research and development project undertaken requires not only that the final system should be fault-tolerant, but also that any erroneous condition should not result in incorrect outputs. The hardware system uses classical Triple-Modular Redundancy techniques but, as is well known, the design of the system software presents many new problems.The Software techniques adopted include the following:∙A strict block structure in which the Real-time execution of each block is always defined - regardless of the various internal branches which may be followed.∙The total Run-time of the complete program is strictly controlled. Any deviation is detected by hardware.∙All non-deterministic events are eliminated by polling.∙Whilst identical programs are executed in each of the TMR processors, a de-synchronising technique is adopted so as to eliminate common-mode fail ures.∙Program divergence is avoided by a constant cross-checking of internal state information.The structure developed brings together many software reliability concepts and has yielded a software system which is not only simple to test, but highly maintainable and highly reliable.

Phased-Mission Analysis for Evaluating the Effectiveness of Aerospace Computing-Systems

Effectiveness evaluation of aerospace fault-tolerant computing systems used in a phased-mission environment is rather tricky and difficult because of the interaction of its several degraded performance levels with the multiple objectives of the mission and the use environment. Part I uses an approach based on multiobjective phased-mission analysis to evaluate the effectiveness of a distributed avionics architecture used in a transport aircraft. Part II views the computing system as a multistate s-coherent structure. Lower bounds on the probabilities of accomplishing various levels of performance are evaluated.

On issues in fault-tolerant computer design

Fault-tolerant computer systems tend to be unique creations based on practical experience. Any new designer will probably be baffled by the diversity of the concepts and designs which can be found in literature and/or in practice since criteria for selecting an approach have not been clearly established. In this paper we have examined some general concepts of fault-tolerant computing to identify common characteristics in an attempt to define the valid domains of these concepts. Emphasis is on the proper identification and careful study of system objectives which can help the designers in selecting the appropriate redundancy structures and thus to achieve less diverse designs.

Fault-tolerant computer systems

The paper reviews the methods by which reliable processing and control can be achieved using fault-tolerant digital computers. The motivation for employing such systems is discussed, together with an indication of current and potential areas of application. The features of fault-tolerant computers are described in general terms, together with a system design procedure specific to the development of a reliable computer. The adherence to a well structured design methodology is particularly important in a fault-tolerant computer to ensure an initially fault-free system. In order to follow this design procedure an intimate knowledge of the following subject areas is required: fault classification, redundancy techniques and their relative merits and reliability modelling and analysis. These topics are covered in the paper, with particular emphasis being placed upon the implementation of hardware, software, data and time-redundancy techniques. Examples of fault-tolerant computers proposed and produced in the last decade are described. The availability of large scale integrated circuits (LSI) and in particular microprocessors will have a profound effect on the development and application of fault-tolerant computers. The implications of using LSI in this area are therefore discussed including a brief description of two fundamentally different approaches to the realisation of a fault tolerant microcomputer.

Availability analysis of a fault-tolerant computer system: Mario Dal Cin. IEEE Trans. Reliab.R-29 (3), 265 (August 1980)

Availability analysis of a fault-tolerant computer system: Mario Dal Cin. IEEE Trans. Reliab.R-29 (3), 265 (August 1980)

Availability Analysis of a Fault-Tolerant Computer System

Queueing network theory is applied in order to determine the availability of a fault-tolerant multiprocessor computer system. Mean repair times and utilizations of system units are computed. Subsystem availabilities are obtained by the decomposition technique of queueing network theory.

Fault-tolerant computing concepts for aerospace applications—a survey

A fault-tolerant computing system performs its intended functions irrespective of the occurrence of certain failures. As the system becomes more and more reliable with built-in fault-tolerance, its analysis, validation and comparison with another system become formidable tasks. Such a study involves issues such as fault classification, figures of merit, fault-tolerant architectures, coverage estimation and automated methods of reliability evaluation. This paper provides a comprehensive survey of all these topics. The new concept of performability, which combines both the performance and the reliability of a system, and the configuration optimisation of a gracefully degradable computing system are also discussed.