Fault-tolerant Architecture Research Articles

A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs

Regular and redundant through-silicon via (TSV) interconnects are used in fault tolerance techniques of 3-D IC. However, the fabrication process of TSVs results in defects that reduce the yield and reliability of TSVs. On the other hand, each TSV is associated with a significant amount of on-chip area overhead. Therefore, unlike the state-of-the-art fault tolerance architectures, here we propose the time division multiplexing access (TDMA)-based fault tolerance technique without using any redundant TSVs, which reduces the area overhead and enhances the yield. In the proposed technique, by means of TDMA, we reroute the signal through defect-free TSV. Subsequently, an architecture based on the proposed technique has been designed, evaluated, and validated on logic-on-logic 3-D IWLS’05 benchmark circuits using 130-nm technology node. The proposed technique is found to reduce the area overhead by 28.70%-40.60%, compared to the state-of-the-art architectures and results in a yield of 98.9%–99.8%.

Flexible Interconnection of Scalable Systems Integrated Using Optical Networks (FISSION) Data-Center—Concepts and Demonstration

With Internet traffic doubling almost every other year, data-center (DC) scalability is destined to play a critical role in enabling future communications. While many DC architectures are proposed to tackle this issue by leveraging optics in DCs, most fail to scale efficiently. We demonstrate flexible interconnection of scalable systems integrated using optical networks (FISSION), which is a scalable, fault-tolerant DC architecture based on a switchless optical-bus backplane and carrier-class switches. The FISSION DC can scale to a large number of servers (even up to 1 million servers) using off-the-shelf optics and commodity electronics. Its backplane comprises multiple, concentric bus-based fiber rings to create a switch-less core. Sectors, which constitute top-of-the-rack switches along with server interconnection pods, are connected to this switchless backplane in a unique opto-electronic architectural framework to handle contention. The FISSION protocol uses segment-routing paradigms for use within the DC as well as an SDN-based standardized carrier-class protocol. In this paper, we highlight, through three use cases, a FISSION test-bed, and show its feasibility in a realistic setting. These use cases include communication within the FISSION DC, in situ addition deletion of servers at scale and equal-cost multipath (ECMP) provisioning.

Design of a Modified Carry Select Adder with Single Fault Tolerant Architecture

Design of a Modified Carry Select Adder with Single Fault Tolerant Architecture

Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM

This paper presents a silicon-proven fault tolerant FPGA architecture that can repair a wide range of hardware faults. The proposed architecture does not require fine-grained fault location, and the error map is stored in non-volatile resistive memory that is monolithically integrated on top of the CMOS circuit. Redundancy operations are fully self-contained and do not affect data streaming in and out of the FPGA. The power gating scheme is implemented to save idle leakage power and fix hardware faults in the power network. Significant yield enhancement is expected using this architecture. The architecture has been verified in a test chip fabricated in 28nm technology. Redundancy operation is solely controlled by on chip fault locators which are HfO2-based resistive memories monolithically integrated after CMOS process. The maximum shift in performance is about 2 percent when the redundancy is engaged, and the power footprint is unaffected.

Fault‐tolerant control of non‐linear systems based on adaptive virtual actuator

A new adaptive fault-tolerant control architecture for Lipschitz non-linear systems is developed. Specifically, the proposed approach involves a novel adaptive virtual actuator which is inserted between the faulty plant and the nominal controller to hide faults and disturbances from the nominal controller. The envisaged adaptive virtual actuator does not require any information about the nominal controller nor does it require a separate fault detection, isolation and identification unit. Moreover, it can tackle loss of effectiveness and time-varying additive actuator faults as well as an external disturbance, and in addition to the stability of the closed-loop system, it also guarantees that the difference between the states of the nominal and the faulty systems tend to zero. Simulation results corresponding to the lateral directional dynamics of an aircraft demonstrate and illustrate the effectiveness of the proposed adaptive virtual actuator.

Encoding qubits into oscillators with atomic ensembles and squeezed light

The Gottesman-Kitaev-Preskill (GKP) encoding of a qubit within an oscillator provides a number of advantages when used in a fault-tolerant architecture for quantum computing, most notably that Gaussian operations suffice to implement all single- and two-qubit Clifford gates. The main drawback of the encoding is that the logical states themselves are challenging to produce. Here we present a method for generating optical GKP-encoded qubits by coupling an atomic ensemble to a squeezed state of light. Particular outcomes of a subsequent spin measurement of the ensemble herald successful generation of the resource state in the optical mode. We analyze the method in terms of the resources required (total spin and amount of squeezing) and the probability of success. We propose a physical implementation using a Faraday-based quantum non-demolition interaction.

Demonstration of quantum advantage in machine learning

The main promise of quantum computing is to efficiently solve certain problems that are prohibitively expensive for a classical computer. Most problems with a proven quantum advantage involve the repeated use of a black box, or oracle, whose structure encodes the solution. One measure of the algorithmic performance is the query complexity, i.e., the scaling of the number of oracle calls needed to find the solution with a given probability. Few-qubit demonstrations of quantum algorithms, such as Deutsch–Jozsa and Grover, have been implemented across diverse physical systems such as nuclear magnetic resonance, trapped ions, optical systems, and superconducting circuits. However, at the small scale, these problems can already be solved classically with a few oracle queries, limiting the obtained advantage. Here we solve an oracle-based problem, known as learning parity with noise, on a five-qubit superconducting processor. Executing classical and quantum algorithms using the same oracle, we observe a large gap in query count in favor of quantum processing. We find that this gap grows by orders of magnitude as a function of the error rates and the problem size. This result demonstrates that, while complex fault-tolerant architectures will be required for universal quantum computing, a significant quantum advantage already emerges in existing noisy systems.

A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

Fault detection and fault-tolerant control of actuators and sensors in distributed parameter systems

This paper proposes the architecture for fault detection and fault-tolerant control for distributed parameter systems with control actuators and measurement sensors. In the development of this architecture, it is assumed that the system contains multiple actuators and sensors with only one actuator and partial sensors are activated while keeping the remaining actuators and sensors dormant. For the approximate finite-dimensional model, a detection observer with a time-varying threshold is proposed to ensure the actuator faults can be detected. An actuator switching policy is used to arrange switching from faulty actuators to healthy ones based on performance enhancement arguments. To facilitate actuator fault diagnosis, an adaptive observer that accommodates actuator fault is designed. Residuals are defined so as to detect the sensor fault. Then, an integrated fault detection and fault-tolerant control architecture of actuators and sensors is taken into account in the implementation of the infinite-dimensional system on the basis of the singular perturbation formulation. Finally, the proposed theoretical results are verified through an example of chemical reaction.

Reliability-aware design for programmable QCA logic with scalable clocking circuit

The limitations of complementary metal---oxide---semiconductor (CMOS) technology on the nanoscale will prevent continuation of the current scaling trends in very large-scale integration (VLSI). Quantum-dot cellular automata (QCA) are one of the emerging nanotechnologies, conceived as a viable alternative to CMOS circuits, offering exceptionally high integration density, impressive switching frequency, and remarkably low power characteristics. However, fabrication issues and susceptibility to high error rates have raised many questions regarding this technology, leading to the search for efficient and scalable methods for design of QCA circuits. In this regard, this work targets a generic, reliable and programmable (RP) architecture for QCA with hybrid cell orientation. An efficient, easily manufacturable, and scalable clocking scheme is proposed towards the design of fault-tolerant QCA architectures. The functionality and defect tolerance of a five-input majority voter with RP structure (RMV) are investigated under cell deposition defects. Simulation results demonstrate that the proposed RP structure is more reliable than the conventional design. Besides reliability, the most striking characteristic of this logic is that it is completely programmable to perform various logic functions, reducing the requirement for disparate logic for large circuits. Comprehensive analysis of its programmable feature is applied to achieve a full adder, which extends its reliability to circuit level. The design of the QCA layout, as well as functional verification of the proposed design, is performed using QCADesigner.

Design of a Fault Tolerant Architecture for Private Cloud Computing Infrastructure

Objectives: Cloud computing has emerged as a cost-effective technology providing services to business-enterprise and IT industry. In this paper, we discuss a novel fault-tolerant scheme from an administration point of view that corresponds to implementation of Redundant Array of Independent Nodes (RAIN) model based architecture for ensuring fault-tolerance in a private cloud infrastructure setup. Methods: After exploring various combinations of Redundant Array of Independent Disks (RAID) and Logical Volume Manager (LVM) techniques, we propose a novel idea of having a fault-tolerant architecture for cloud infrastructure. Findings: As an alternative to the existing cloud fault-tolerant techniques which use expensive and specialized shared storage system, local server disk pool will be used for storing VM images. This architecture provides a robust infrastructure built over Internet Small Computer System Interface (iSCSI) targets and software RAID. Application: This RAIN based model can be deployed over the existing cloud infrastructure. This storage model can be used by cloud toolkits to provide fault tolerant backend for storage.

A low-overhead soft–hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems

The Network-on-Chip (NoC) paradigm has been proposed as a favorable solution to handle the strict communication requirements between the increasingly large number of cores on a single chip. However, NoC systems are exposed to the aggressive scaling down of transistors, low operating voltages, and high integration and power densities, making them vulnerable to permanent (hard) faults and transient (soft) errors. A hard fault in a NoC can lead to external blocking, causing congestion across the whole network. A soft error is more challenging because of its silent data corruption, which leads to a large area of erroneous data due to error propagation, packet re-transmission, and deadlock. In this paper, we present the architecture and design of a comprehensive soft error and hard fault-tolerant 3D-NoC system, named 3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC (3D-FETO). With the aid of efficient mechanisms and algorithms, 3D-FETO is capable of detecting and recovering from soft errors which occur in the routing pipeline stages and leverages reconfigurable components to handle permanent faults in links, input buffers, and crossbars. In-depth evaluation results show that the 3D-FETO system is able to work around different kinds of hard faults and soft errors, ensuring graceful performance degradation, while minimizing additional hardware complexity and remaining power efficient.

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art reliability estimation methods makes this exploration un-scalable with the design complexity. In this paper we introduce a low-cost reliability analysis methodology that helps taking this key decision with less computational effort and orders of magnitude faster. Based on this methodology we also propose a selective hardening technique using a hybrid fault tolerant architecture that allows meeting the soft-error rate constraints within a given design cost-budget and vice versa. Our experimental validation shows that the methodology offers huge gain (1200 ×) in terms of computational effort in comparison with fault injection-based reliability estimation method and produces results within acceptable error limits.

SEUs Mitigation on Program Counter of the LEON3 Soft Processor

Analyzing and evaluating the sensitivity of embedded systems to soft-errors have always been a challenge for aerospace or safety equipment designer. Different automated fault-injection methods have been developed for evaluating the sensitivity of integrated circuit. Also many techniques have been developed to get a fault tolerant architecture in order to mask and mitigate fault injection in a circuit. Fault injection mitigation and repair techniques are applied together on LEON3 processor in goal to study the reliability of a soft-core. The so-called NETlist Fault Injection (NETFI+) tool is a fault injection techniques used in this paper. The prediction of Single Event Upset (SEU) error-rates between radiation ground testing and FPGA implementation have been done with good and accurate result. But no functional simulations have been performed. A Triple Modular Redundancy (TMR) is used in this paper as a repair technique versus fault injection. This paper analyses the effectiveness of fault tolerant method on LEON3 soft-core running a benchmark. It starts by evaluating the behavior of LEON3’s program counter against Single Event Upset error-rate accuracy between the functional simulation and the FPGA emulation and an analysis of the LEON3 reliability in presence of fault tolerant technique. The objective is to offer, through the new version of NETFI+ with introducing a fault tolerant technique, the possibility to designers to evaluate the benefits of SEUs mitigation for the LEON3 processor on the program counter.

A new fault-tolerant architecture based on DASH for adaptive streaming video

A new fault-tolerant architecture based on DASH for adaptive streaming video

Fail silence mechanism for dependable vehicular communications

This paper presents a fault-tolerant architecture to improve the dependability of infrastructure-based vehicular networks. For that purpose, a fail silence enforcement mechanism for road-side units (RSUs) was designed, implemented and tested. Vehicular communications based on IEEE 802.11p are inherently non-deterministic. The presence of RSUs and a backhauling network, adds a degree of determinism that is useful to enforce real-time and dependability, both by providing global knowledge and by supporting the operation of collision-free deterministic MAC protocols. One of such protocols is V-FTT, for which the proposed mechanism was designed as a case study. Notice, however that this mechanism is protocol independent and can be adapted to any wireless communications system. The proposed technique is capable of validating a frame for transmission by identifying faults both in value and time domains. Experimental results show that the fail silence enforcement mechanism has low latency and consumes few FPGA resources.

A new fault-tolerant architecture based on DASH for adaptive streaming video

The standard dynamic adaptive streaming over HTTP (DASH) has been proposed to guarantee a quality of video under varying bandwidth. DASH enables adaptation of the media bit-rate to varying throughput conditions by offering multiple representations of the same content. However, the Moving Picture Experts Group (MPEG) DASH specification only defines the media presentation description (MPD) and the segment formats. In order to take advantages of DASH, we propose a fairness architecture, called dynamic adaptive streaming over HTTP distributed multimedia systems (DASH-DMS). DASH-DMS combines both 2-tiers and 3-tiers architectures in order to guarantee a quality of service (QoS) under changing conditions. Moreover, we propose replication algorithms to enable load balancing video servers and improve the global QoS. Furthermore, in order to improve the availability of our system, we use a fault tolerance policy. To this purpose, we have conduct simulations throughout the paper using the simulator developed by our team.

Nonfragile Fault-Tolerant Fuzzy Observer-Based Controller Design for Nonlinear Systems

The problem of actuator fault estimation and fault-tolerant control for a class of uncertain nonlinear systems using Takagi–Sugeno fuzzy models is investigated. A design procedure for nonfragile proportional-integral (PI) observer is proposed to estimate the states of the nonlinear system and reconstruct the abrupt (modeled as step-like faults) and incipient fault signals. Subsequently, a nonfragile fault-tolerant controller is constructed, which is informed by the PI observer. Sufficient conditions of the existence of the PI observer and the fault-tolerant controller are provided in the form of linear matrix inequalities. The proposed fault-tolerant control architecture is tested on two numerical examples.

A fault tolerant architecture for data fusion: A real application of Kalman filters for mobile robot localization

Multisensor perception has an important role in robotics and autonomous systems, providing inputs for critical functions including obstacle detection and localization. It is starting to appear in critical applications such as drones and ADASs (Advanced Driver Assistance Systems). However, this kind of complex system is difficult to validate comprehensively. In this paper we look at multisensor perception systems in relation to an alternative dependability method, namely fault tolerance. We propose an approach for tolerating faults in multisensor data fusion that is based on the more traditional method of duplication–comparison, and that offers detection and recovery services. We detail an example implementation using Kalman filter data fusion for mobile robot localization. We demonstrate its effectiveness in this case study using real data and fault injection.

On the Unprecedented Scalability of the FISSION (Flexible Interconnection of Scalable Systems Integrated Using Optical Networks) Datacenter

Internet traffic is doubling almost every other year which implies that datacenter (DC) scalability will play a critical role in enabling future communications. In this paper, we propose FISSION (Flexible Interconnection of Scalable Systems Integrated using Optical Networks)—a scalable, fault-tolerant DC architecture based on a switchless optical-bus backplane and carrier-class switches, and its supporting protocol. The FISSION DC enables unprecedented scalability using affordable optics and standardized electrical switches. It is architecturally bifurcated into sectors that internally have a nonblocking carrier-class switching interconnection structure. Sectors are connected in the switchless backplane using optical buses. Each sector can receive traffic on all wavelengths (achieved through optical-bus property without any switch reconfiguration) and across all fibers, but a sector transmits on only a group of wavelengths and only in one of the fiber rings in the backplane. The switches function based on an SDN methodology that facilitate mapping of complex protocols and addresses to DC-specific addressing that is scalable and easier to use. We present an analysis to optimize the FISSION architecture. A simulation model is proposed that (1) compares the FISSION approach to other contemporary designs; (2) provides scalability analysis and protocol performance measurement; and, (3) provides optical layer modeling to validate working of the FISSION framework at high line-rates. Our architecture, which provides 100% bisection bandwidth, is validated by simulation results exhibiting negligible packet loss and low end-to-end latency.