Fault Phase Selection Research Articles

Design and Testing of a Multi-Microprocessor Travelling Wave Relay

This paper describes the design and testing of a digital ultra high speed (UHS) travelling wave based protective relay. It shows how a prototype has been realized by a simple and fairly low cost (a few hundred dollars for parts) dedicated multi-microprocessor system. The paper presents also the results of the tests carried out on the prototype by using a microprocessor based complex waveform signal generator (CWSG) which displays the output of a mainframe computer-based electromagnetic transients program (EMTP) in real time. The relay showed good practical behaviour, especially with regard to the UHS feature and faulted phase selection and fault classification capability.

Development of switching principles and phase comparison techniques for distance protective schemes

The paper represents further work on phase comparison techniques by the same author. Two techniques are reported here. The first one describes a new principle of operation employed for the main functions of starting elements for fault detection and selection of phase(s). The principle is based on a process of phase comparison accomplished between comparison quantities derived from the three symmetrical components of line current relative to only one phase of the protected line section. Fault detection and phase selection are achieved by delivering nine distinct orders from the starting element corresponding to the nine cases of asymmetrical faults. The starting element based on this principle reduces the switching time to 3.33 ms. The second technique is concerned with phase comparison techniques to improve the security and reliability of the high-speed comparator described previously by the same author. The modus operandi consists of continuously monitoring the coincidence of compared comparison periods derived from the two relaying signals and simultaneously the non-coincidence of another set of compared comparison periods derived from the same relaying signals. Fault detection is achieved by delivering a trigger output from the comparator corresponding to non-coincidence of the first set and coincidence of the second set of comparison periods.