Fault Latency Research Articles

Diagnosis of Power Switch Faults in Three-Phase Permanent Magnet Synchronous Motors via Current-Signature Technique

The paper deals with the development of a model-based current-signature algorithm for the detection and isolation of power switch faults in three-phase Permanent Magnet Synchronous Motors (PMSMs). The algorithm, by elaborating the motor currents feedbacks, reconstructs the current phasor trajectories in the Clarke plane through elliptical fittings, up to detecting and isolating the fault depending on the characteristics of the signature deviation from the nominal one. As a rough approximation, as typically proposed in the literature, the fault of one out of six power switches implies that, at constant speed operation, the phasor trajectory deviates from the nominal circular path up to a semi-circular “D-shape” signature, the inclination of which depends on the failed converter leg. However, this evolution can significantly deviate in practical cases, due to the dynamics related to the transition of motor phase connections from failed to active switches. The study demonstrates that an online ellipse fitting of the current signature can be effective for diagnosis, through correlating the ellipse centre to the location of the failed switch. The performances of the proposed monitoring technique are here assessed via the nonlinear simulation of a PMSM employed for the propulsion of a lightweight fixed-wing Unmanned Aerial Vehicle (UAV), by quantifying the fault latencies and the related transients.

Reliability improvement of automotive electronics based on environmental stress screen methodology

The effectiveness of ESS method for detecting early failure was verified using semiconductor sample with fault latency. Analysis for field failure data based on Kaplan–Meier estimation and fault tree analysis revealed that the failure of semiconductor devices occurred in the early failure period. In order to carry out ESS experiment, artificially fault injected specimen, which had physical damages but performed main function, were prepared. Even though a thermal cycling test was performed to detect fault latency, it was concluded that fault latency was not screened out using the standard ESS method.

E-D2HCP: enhanced distributed dynamic host configuration protocol

Mobile Ad Hoc Networks (MANETs) consist of mobile nodes equipped with wireless devices. They do not need any kind of pre-existent infrastructure and are about self-managed networks. MANETs enable communication between mobile nodes without direct links and across multihop paths. To ensure correct operation of the routing protocols, MANETs, have to assign unique IP addresses to the MANET devices. Furthermore, the address assignment is an important issue when dealing with MANET networks because the traditional approaches are not applicable without some changes, having to provide new protocols for the address auto-configuration. These schemes must take into account the properties of MANETs such as dynamic topology, limited resources or lack of infrastructure. In this paper, we propose a stateful scheme for dynamic allocation of IP addresses in MANETs entitled Extended Distributed Dynamic Host Configuration Protocol because it is based on a previous piece of work (D2CHP). This extension includes the network merging not covered by its predecessor. Simulation results show that the new protocol also improves D2HCP functionality in areas such as fault tolerance, concurrency and latency.

SEU Recovery Mechanism for SRAM-Based FPGAs

The application of SRAM-based field-programmable gate arrays (FPGAs) in mission-critical systems requires error-mitigation and recovery techniques to protect them from the errors caused by high-energy radiation, also known as single event upsets (SEUs). For this, modular redundancy and runtime partial reconfiguration are commonly employed techniques. However, the reported solutions feature different tradeoffs in the area overhead and the fault latency. In this paper, we propose a low area-overhead SEU recovery mechanism and describe its application in different self-recoverable architectures, which are experimentally evaluated using a specially designed fault-emulation environment. The environment enables the user to inject faults at selected locations of the configuration memory and experimentally evaluate the reliability of the developed solutions.

Replacement and swapping strategy to improve read performance of portable consumer devices using compressed file systems

Compressed file systems are suitable for portable consumer devices with small capacity of storage systems because the contents of files are stored as a compressed form to save the space of storage. The portable consumer devices also exploit demand paging mechanism to cut down their cost and size. However, if the portable consumer devices use the compressed file systems, there are large computational and I/O overheads. When data are requested, the data should be decompressed before they are accessed by application programs. This is the computational overhead of compressed file systems. And also, to decompress only one byte data, several data should be copied to the main memory from the secondary storage. That is the I/O overhead. To overcome these overheads, this work proposes a new replacement and swapping strategy for the portable consumer devices using the compressed file systems, which keeps the frequently accessed data in the main memory as long as possible and stores the uncompressed data of compressed file systems in the swap space so that serves them directly from the swap space. This strategy increases the page hit ratio, and reduces several copying operations and a decompressing operation of compressed file systems. As a result, it could improve the read performance of portable consumer devices. Trace-driven simulations with real traces show that the proposed replacement and swapping strategy performs better than existing replacement and swapping mechanism in terms of the total read I/O performance, page fault ratio, and page fault latency.

Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor

This paper presents a detailed analysis of the behavior of a novel fault-tolerant 32-bit embedded CPU as compared to a default (non-fault-tolerant) implementation of the same processor during a fault injection campaign of single and double faults. The fault-tolerant processor tested is characterized by per-cycle voting of microarchitectural and the flop-based architectural states, redundancy at the pipeline level, and a distributed voting scheme. Its fault-tolerant behavior is characterized for three different workloads from the automotive application domain. The study proposes statistical methods for both the single and dual fault injection campaigns and demonstrates the fault-tolerant capability of both processors in terms of fault latencies, the probability of fault manifestation, and the behavior of latent faults.

SWL

As mobile phones become increasingly multifunctional, the number and size of applications installed in phones are rapidly increasing. Consequently, mobile phones require more hardware resources such as NOR/NAND flash memory and DRAM, and their production cost is accordingly becoming higher. One candidate solution to reduce production cost is demand paging using MMU. However, demand paging causes unpredictably long page fault latency, and as such mobile phone manufacturers are reluctant to deploy this scheme. In this paper, we present a method that reduces the long latency of page faults by performing page fault handling in a parallelized manner, considering the characteristics of NAND-Type flash memory. We also discuss how to modify the existing page cache replacement policies so that they can exploit the benefits of the parallelized page fault handler. Experimental results show that the parallelized page fault handler improves the worst case latency of page faults significantly, by up to roughly 20%, and that the modified page cache replacement policies improve both the average and worst instruction fetch time.

Monitoring and predictive maintenance: Modeling and analyse of fault latency

This paper presents an effective way of modeling complex systems through identified functioning modes. In the proposed approach, the integration of monitoring in the manufacturing system is facilitated by the development of a generic model. The aim is to propose a monitoring system able of absorbing internal degradation of any variables and ensuring the continuity of the service. The outline of the optimization of the fault latency method is based on two steps is proposed. The first step is the evaluation of fault latency and the second one is the performance evaluation of monitoring process. Timed automata are the modeling tool used for these two steps. The proposed method can be applied to various kinds of processes and gives good results. Indeed, the simulation results, including a serial manufacturing line, substantiate the feasibility of the proposed method and provide a promising potential to spin-off applications in industrial manufacturing system.

Early warning of fault conditions of an over-current protection module in dependable communication applications

Abstract This article describes the implementation of early warning feature in an over-current protection module designed for limiting the surge-current in communication applications. The early warning signal is generated by a surge-current sensor and a temperature sensor mounted on the protection module. Described solution decreases fault latency and consequently improves the efficiency of the on-line fault detection mechanism. It can be used for diagnostic on-line monitoring in dependable adaptive computing systems.

Introspection

We report a register transfer level technique for concurrent error detection and diagnosis in data dominated designs called Introspection . Introspection uses idle computation cyles in the data path and idle data transfer cycles in the interconnection network in a synergistic fashion for concurrent error detection and diagnosis (CEDD). The resulting on-chip fault latencies are one ten-thousandth (10 -4 ) of previously reported system level concurrent error detection and diagnosis latencies. The associated area overhead and performance penalty are negligible. We derive a cost function that considers introspection constraints such as (i) executing an operation on three disjoint function units for diagnosis and (ii) promoting function units to participate in at least one CEDD operation. We formulate integration of introspection constraints into the operation-to-operator binding phase of high-level synthesis as a weighted bipartite matching problem. The effectiveness of introspection and its implementation are illustrated on numerous industrial strength benchmarks.

Reliability evaluations of a database recovery with archive copies for fault latency

This paper examines the reliability of the database recovery mechanism by using archive copies for fault latency. An evaluation model for the recovery is proposed to derive the recovery overhead for a latent fault and the availability for a cycle. The results of numerical calculations show the impacts of model parameters considered. It is concluded that, for the total system availability in normal situations, an archive recovery scheme should be determined taking account of only nonlatent faults and the maintenance costs of multiple copy generations, whether the effect of fault latency is great or not. On the other hand, if the system puts restrictions on the recovery time, the archive copy interval and the number of copy generations should be considered to determine the recovery scheme.

Generalized evaluation model with file recovery mechanism for fault latency

Generalized evaluation model with file recovery mechanism for fault latency

Testing embedded memories in telecommunication systems

Extensive system testing is mandatory nowadays to achieve high product quality. Telecommunication systems are particularly sensitive to such a requirement; to maintain market competitiveness, manufacturers need to combine reduced costs, shorter life cycles, advanced technologies, and high quality. Moreover, strict reliability constraints usually impose very low fault latencies and a high degree of fault detection for both permanent and transient faults. This article analyzes major problems related to testing complex telecommunication systems, with particular emphasis on their memory modules, often so critical from the reliability point of view. In particular, advanced BIST-based solutions are analyzed, and two significant industrial case studies presented.

Generalized evaluation model with file recovery mechanism for fault latency

Generalized evaluation model with file recovery mechanism for fault latency

OPTIMAL ARCHIVE COPY INTERVAL FOR A FILE RECOVERY WITH GENERAL FAULT LATENCY TIME

This paper considers the stochastic model of a file recovery mechanism: archive copies with n available generations are created periodically at constant time T. When failures have been detected, the consistent state is restored at the time just before fault occurrence by archive copies. The recovery overhead and its mean time are obtained when the fault latency time has a general distribution and a failure is detected uniformly during the copy interval. An optimal interval T* of archive copies is discussed analytically. Numerical examples are given when the fault latency time has exponential and gamma distributions.

Optimal Fault-Secure Scheduling

We consider here two basic fault-secure scheduling problems for multiprocessor systems. First, given the number of processors in the system and a set of computational tasks of unit length expressed as a complete binary tree, a scheduling algorithm is proposed such that the total execution time is a minimum and no undetected single error result will be delivered. Second, given a deadline and a computation tree, another algorithm is given which generates a fault-secure scheduling using a minimum number of processors. We show that two previous approaches are special cases of these algorithms. We also discuss the way to modify our scheduling to ensure a given fault latency requirement. Finally, extensions that cover multiple errors, non-unit length tasks and computation graphs of arbitrary binary trees are discussed.

Hardware fault latency: Problem formulation and solution

A fault does not necessarily cause an immediately effective error, thereby leading to a system failure. Many experiments have shown that most hardware faults do not cause immediately detectable errors. In fact, it has been found that a significant proportion of the faults injected during the experiments remained latent, i.e. went undetected. In this paper we call this phenomenon the latency problem. An analytical model is developed in the paper to study the effects of the latency problem on fault-tolerant computer systems. Some of the results of our sensitivity analysis are presented and discussed.

System dependability evaluation via a fault list generation algorithm

The size and complexity of modern dependable computing systems has significantly compromised the ability to accurately measure system dependability attributes such as fault coverage and fault latency. Fault injection is one approach for the evaluation of dependability metrics. Unfortunately, fault injection techniques are difficult to apply because the size of the fault set is essentially infinite. Current techniques select faults randomly resulting in many fault injection experiments which do not yield any useful information. This research effort has developed a new deterministic, automated dependability evaluation technique using fault injection. The primary objective of this research effort was the development and implementation of algorithms which generate a fault set which fully exercises the fault detection and fault processing aspects of the system. The theory supporting the developed algorithms is presented first. Next, a conceptual overview of the developed algorithms is followed by the implementation details of the algorithms. The last section of this paper presents experimental results gathered via simulation-based fault injection of an Interlocking Control System (ICS). The end result is a deterministic, automated method for accurately evaluating complex dependable computing systems using fault injection.

Accurate computation of field reject ratio based on fault latency

It is shown that the known methods of field reject ratio prediction are not accurate since they fail to realistically model the process of testing. The authors model the detection of a fault by an input test vector as a random event. However, the detection of a fault may be delayed for various reasons: the fault may be detectable only by application of a sequence of vectors or it may not have been targeted until later. In the statistical model, a fault is characterized by two parameters: a per-vector detection probability and an integer-valued latency. Irrespective of the detection probability, the fault cannot be detected by a vector sequence shorter than its latency. The circuit is characterized by the joint distribution of latency and detection probability over all faults. This distribution, obtained by applying the Bayes' rule to the actual test data, allows computations the field reject ratio. The sensitivity of this approach to variations in the measured parameters is also investigated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Measurement and analysis of workload effects on fault latency in real-time systems

The authors demonstrate the need to address fault latency in highly reliable real-time control computer systems. It is noted that the effectiveness of all known recovery mechanisms is greatly reduced in the presence of multiple latent faults. The presence of multiple latent faults increases the possibility of multiple errors, which could result in coverage failure. The authors present experimental evidence indicating that the duration of fault latency is dependent on workload. A synthetic work generator is used to vary the workload, and a hardware fault injector is applied to inject transient faults of varying durations. This method makes it possible to derive the distribution of fault latency duration. Experimental results obtained from the fault-tolerant multiprocessor at the NASA Airlab are presented and discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>