Fault Injection Techniques Research Articles

A framework for disturbance analysis in smart grids by fault injection

With growing complexity of electric power systems, a total number of disturbances is expected to increase. Analyzing these disturbances and understanding grid's behavior, when under a disturbance, is a prerequisite for designing methods for boosting grid's stability. The main obstacle to the analysis is a lack of relevant data that are publicly available. In this paper, we present a design and implementation of a framework for emulation of grid disturbances by employing simulation and fault-injection techniques. We also present a case study on generating voltage sag related data. A foreseen usage of the framework considers mainly prototyping, root-cause analysis as well as design and comparison of methods for disturbance detection and prediction.

A Survey of Fault-Injection Methodologies for Soft Error Rate Modeling in Systems-on-Chips

The development of process technology has increased system performance, but the system failure probability has also significantly increased. It is important to consider the system reliability in addition to the cost, performance, and power consumption. In this paper, we describe the types of faults that occur in a system and where these faults originate. Then, fault-injection techniques, which are used to characterize the fault rate of a system-on-chip (SoC), are investigated to provide a guideline to SoC designers for the realization of resilient SoCs.

A Methodology for Continuous Evaluation of Cloud Resiliency

With the growth of cloud computing, resiliency of cloud is critical for enterprises’ business. However, the continuous-changing of cloud makes evaluation of cloud resiliency more difficult. In this study, we design a methodology for automatic and continuous evaluation of cloud resiliency and implement it in a tool called CRGauge. The Continuous Evaluation Model methodology leverages fault injection techniques to inject faults and an open-source library to set up synthetic workloads for the test campaign. Our experiment results on OpenStack cloud platform show that resiliency of OpenStack is needed to be improved especially in heavy workloads.

Special issue on High Assurance Systems Engineering

As software-based systems become more pervasive, there is a need to construct systems that in addition to meeting their functional requirements also adhere to their non-functional requirements, specifically those requirements that impact reliability, safety and security. The stated requirements all make a strong case for High Assurance Systems Engineering. Both academia and industry continue to seek new techniques and tools to develop systems that ensure their systems meet the highest assurance standards. In this special issue on High Assurance Systems Engineering, seven papers are presented that investigate problems in the areas of reliability, safety and security. The first paper ‘‘An Empirical Exploration of Distortion in Fault Injection Experiments’’ by Erik van der Kouwe, Cristiano Giuffrida and Andrew S. Tanenbaum investigates whether fault injection experiments faithfully represents the fault model designed by the user. Most software researchers and practitioners accept the fact that there will always be bugs present in software, except for trivial programs; therefore the focus for highly reliable systems should also be on the mechanisms that contain faults and recover from them. This paper makes a case for carefully evaluating whether activated faults, when using a fault injection technique, match the user’s fault model of the software and identifying which parameters impact the activation of faults from the fault model. The second paper ‘‘Accelerating Temporal Verification of Simulink Diagrams Using Satisfiability Modulo Theories’’ by Petr Bauch, Vojtech Havel and Jiri Barnat explores the process of model checking for Simulink diagrams by developing a hybrid approach that involves the explicit and symbolic representations of sets. The approach takes into account

Fault-injection based backdoors in Pseudo Random Number Generators

The main aim of this paper is to present the concept of fault-injection backdoors in Random Number Generators. Backdoors can be activated by fault-injection techniques. Presented algorithms can be used in embedded systems like smart-cards and hardware security modules in order to implement subliminal channels in random number generators.

Closing the gap between speed and configurability of multi-bit fault emulation environments for security and safety–critical designs

Steadily decreasing transistor sizes and new multi beam laser attacks lead to an increasing amount of multi-bit fault occurrences, e.g., during fault attacks against cryptographic implementations. Therefore, multi-bit fault injection becomes more important during security and safety verification. Fault injection techniques which are applicable during the development cycle of a device are based on either software implementations, e.g. formal methods and simulations, or fault emulation environments in hardware. So far, simulations provide the best configurability whereas fault emulation environments provide the best performance in terms of run time. This contribution presents an FPGA-based emulation environment that combines the advantages of both simulation-based and emulation-based environments. To the best of our knowledge, we are the first to achieve this. Permanent and transient multi-bit faults are configurable at run time where the selection of a fault model, the configuration of the injection time and fault duration is supported without the need for re-synthesizing the design. We propose three measures for performance optimization allowing us to support all the fault configuration capabilities at run time without performance penalty. Experimental results are provided for a hardened 8051-like microprocessor showing that the presented emulation environment reaches the theoretical optimal performance for a wide range of fault configurations using our proposed optimizations.

Software Reliability Validation and Verification Using Fault Injection Techniques on a Fault Tolerant Processor

Due to the continuously increasing complexities of embedded electronic systems, there is a clear need for more sophisticated methods of testing and evaluating the performances and reliabilities of the embedded software. One such method is to simulate potentially dangerous events, while monitoring the system's response and stability. This paper presents a software simulation tool, which will be used for evaluating the mission critical software of the TRISAT mission. The software simulation tool simulates, on a per-cycle basis, the fault tolerant processor and its peripherals while also simulating the effects of the space environment on the simulated hardware. Using the simulation software, a dependability analysis was performed regarding the use of Error Correction and Detection Codes on the processor data memory as well as the rate of memory scrubbing, using two benchmark algorithms: matrix multiplication and quick sort.

Proof of retrievability with public verifiability resilient against related‐key attacks

Modern technologies such as cloud computing, grid computing and software as a service all require data to be stored by the third parties. A specific problem encountered in this context is to convince a verifier that a user's data are kept intact at the storage servers. An important approach to achieve this goal is called proof of retrievability, by which a storage server can assure a verifier via a concise proof that a user's file is available. However, for most publicly verifiable systems, existing proof of retrievability solutions do not take physical attacks into consideration, where an adversary can observe the outcome of the computation with methods like fault injection techniques. In fact, the authors find that giving the adversary the ability to obtain the information about the relations between the private keys, those systems are not secure anymore. Motivated by the need of preventing this kind of attacks, they present the security model for related-key attacks in publicly verifiable proofs of retrievability, where the adversary can subsequently observe the outcome of the publicly verifiable proof of retrievability under the modified key. After pointing out a linear related-key attack on an existing proof of retrievability system with public verifiability, they present a secure and efficient proof of retrievability with public verifiability, against related-key attacks.

On the Structural Robustness Assessment of Wireless Communication Systems for Intra-Satellite Applications

When a system has been designed to be robust against other phenomena different than ionizing radiation, it is possible that the robustness introduced by design in its structure may also make it tolerate some radiation effects. The present work explores how to exploit the self-correcting features that transmitter-receiver systems have for correcting channel-induced errors, in order to optimally design a radiation-tolerant wireless communications system for intra-satellite communication. A wireless transceiver is a good example of how to proceed to design a system that has some inherent robustness by itself, so fewer protections are needed when hardening it against radiation. The assessment is made using a fault injection technique, where the figure assessed is the transmission Frame Error Rate (FER) instead of the typical cycle-by-cycle comparison with a theoretical, or golden, bit sequence. This assessment allows the designer to optimally protect the transceiver, reducing mitigation area overhead with respect to full and selective Triple Modular Redundancy (TMR) schemas. The technique has been applied to the design of a wireless transmitter, reducing the area overhead required to harden it against Single Event Upsets (SEU), compared with traditional full and selective TMR schemes.

An AOP-Based Fault Injection Environment for Cryptographic SystemC Designs

The increasing complexity of cryptographic devices requires fast simulation environment in order to test their security against fault attacks. SystemC is one promising candidate in Electronic System Level that allows models to reach higher simulation speed. However in order to enable both fault injection and detection inside a SystemC cryptographic models, its code modification is mandatory. Aspect-Oriented Programming (AOP), which is a new programming paradigm, can be used to test the robustness of the cryptographic models without any code modifications. This may replace real cryptanalysis schemes. In this paper, we present a new methodology to simulate the security fault attacks of cryptographic systems at the Electronic System Level. A fault injection/detection environment is proposed to test the resistance of cryptographic SystemC models against fault injection attacks. The fault injection technique into cryptographic SystemC models is performed using weaving faults by AspectC++ as an AOP programming language. We validate our methodology with two scenarios applied to a SystemC Advanced Encryption Standard case study: the first is related to the impact of the AOP on fault detection capabilities, while the second refers to the impact of the AOP on simulation time and size of the executable files. Simulation results show that this methodology can evaluate perfectly the robustness of a cryptographic design against fault injection attacks. They show that the impact of AOP on simulation time is not significant.

Deployment and activation of faulty components at runtime for testing self-recovery mechanisms

The hypotheses on potential sources of error in an application can be specified in a fault model, which helps testing scenarios that are likely to be buggy. Based on a fault model, we developed custom fault detection mechanisms for providing self-recovery behavior in a component platform when third-party components behave inappropriately. In order to perform the tests for validating such mechanisms, it would be necessary to use a technique for fault injection so we could simulate faulty behavior. However such a technique may not be appropriate for a component-based approach. The behavior of systems tested with faults injected in the interface level (e.g., passing invalid parameters) would not represent actual application usage, thus significantly differing from cases where faults are injected in the component level (e.g. emulation of internal component errors). This paper presents our approach for testing self-adaptive mechanism, involving a general model for fault deployment and fault activation. Faulty components deployed at runtime represent faulty behaviors specified in the fault model. These faults are remotely activated through test probes that help testing the effectiveness of the platform's self-adaptive mechanisms that are fired upon the detection of the specified faulty behavior.

Exception handling analysis and transformation using fault injection: Study of resilience against unanticipated exceptions

ContextIn software, there are the error cases that are anticipated at specification and design time, those encountered at development and testing time, and those that were never anticipated before happening in production. Is it possible to learn from the anticipated errors during design to analyze and improve the resilience against the unanticipated ones in production? ObjectiveIn this paper, we aim at analyzing and improving how software handles unanticipated exceptions. The first objective is to set up contracts about exception handling and a way to assess them automatically. The second one is to improve the resilience capabilities of software by transforming the source code. MethodWe devise an algorithm, called short-circuit testing, which injects exceptions during test suite execution so as to simulate unanticipated errors. It is a kind of fault-injection techniques dedicated to exception-handling. This algorithm collects data that is used for verifying two formal contracts that capture two resilience properties w.r.t. exceptions: the source-independence and pure-resilience contracts. Then we propose a code modification technique, called “catch-stretching” which allows error-recovery code (of the form of catch blocks) to be more resilient. ResultsOur evaluation is performed on 9 open-source software applications and consists in analyzing 241 catch blocks executed during test suite execution. Our results show that 101/214 of them (47%) expose resilience properties as defined by our exception contracts and that 84/214 of them (39%) can be transformed to be more resilient. ConclusionOur work shows that it is possible to reason on software resilience by injecting exceptions during test suite execution. The collected information allows us to apply one source code transformation that improves the resilience against unanticipated exceptions. This works best if the test suite exercises the exceptional programming language constructs in many different scenarios.

Markov chain algorithms: a template for building future robust low-power systems.

Although computational systems are looking towards post CMOS devices in the pursuit of lower power, the expected inherent unreliability of such devices makes it difficult to design robust systems without additional power overheads for guaranteeing robustness. As such, algorithmic structures with inherent ability to tolerate computational errors are of significant interest. We propose to cast applications as stochastic algorithms based on Markov chains (MCs) as such algorithms are both sufficiently general and tolerant to transition errors. We show with four example applications--Boolean satisfiability, sorting, low-density parity-check decoding and clustering-how applications can be cast as MC algorithms. Using algorithmic fault injection techniques, we demonstrate the robustness of these implementations to transition errors with high error rates. Based on these results, we make a case for using MCs as an algorithmic template for future robust low-power systems.

Research on Gray-Box Testing Methods for Software Fault Injection

Because of various advantages of software, implemented system function is more and more through software. In order to ensure the system is running, the verification of fault-oriented processing function module need software fault injected techniques to support. The traditional software fault injection technique method mainly studies the injection achievement of various fault modes. In order to achieve better test coverage, it is necessary to analyze software fault related needs and structure. Therefore, this paper combined gray box testing methods and software fault injection technique, it is proposed gray-box testing technique oriented to software fault injection, and give fault injection process framework.

Tracing Fault Effects in FPGA Systems

Abstract The paper presents the extent of fault effects in FPGA based systems and concentrates on transient faults (induced by single event upsets - SEUs) within the configuration memory of FPGA. An original method of detailed analysis of fault effect propagation is presented. It is targeted at microprocessor based FPGA systems using the developed fault injection technique. The fault injection is performed at HDL description level of the microprocessor using special simulators and developed supplementary programs. The proposed methodology is illustrated for soft PicoBlaze microprocessor running 3 programs. The presented results reveal some problems with fault handling at the software level.

CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors

Reliability of the current microprocessor technology is seriously challenged by radiation-induced soft errors. Accurate Vulnerability Factor (VF) modeling of system components is crucial in designing cost-effective protection schemes in high-performance processors. Although Statistical Fault Injection (SFI) techniques can be used to provide relatively accurate VF estimations, they are often very time-consuming. Unlike SFI techniques, recently proposed analytical models can be used to compute VF in a timely fashion. However, VFs computed by such models are inaccurate as the system-level impact of soft errors is overlooked.In this paper, we propose a system-level analytical technique, called Component Error Derating And Read frequency (CEDAR) vulnerability model, combining the advantages of previously presented analytical models and the SFI techniques. The key idea behind CEDAR is to take into account component error derating and read frequency for data-path blocks in high-performance processors. To further investigate the impact of read frequency and component error derating on the system-level VF, we use Input-to-Output Derating (IOD) factor of system components in the proposed analytical model. As a case study, we study system-level vulnerability for cache memory by providing IOD analysis for different processor core configurations. Our experimental results reveal that processor core IOD can significantly affect the system-level vulnerability of cache memories. The experimental results show that CEDAR improves the accuracy of previous analytical VF estimation techniques up to 91% and 5% for write-through and write-back cache memories, respectively, while it speeds up estimation time up to 10× as compared to SFI techniques.

A fast, flexible, and easy-to-develop FPGA-based fault injection technique

By technology down scaling in nowadays digital circuits, their sensitivity to radiation effects increases, making the occurrence of soft errors more probable. As a consequence, soft error rate estimation of complex circuits such as processors is becoming an important issue in safety- and mission-critical applications. Fault injection is a well-known and widely used approach for soft error rate estimation. Development of previous FPGA-based fault injection techniques is very time consuming mainly because they do not adequately exploit supplementary FPGA tools. This paper proposes an easy-to-develop and flexible FPGA-based fault injection technique. This technique utilizes debugging facilities of Altera FPGAs in order to inject single event upset (SEU) and multiple bit upset (MBU) fault models in both flip-flops and memory units. As this technique uses FPGA built-in facilities, it imposes negligible performance and area overheads on the system. The experimental results show that the proposed technique is on average four orders of magnitude faster than a pure simulation-based fault injection. These features make the proposed technique applicable to industrial-scale circuits.

A method to assess the robustness of cryptographic circuits at the design stage

This paper proposes the use of an FPGA-based fault injection technique, AMUSE, to study the effect of malicious attacks on cryptographic circuits. Originally, AMUSE was devised to analyze the soft error effects (SEU and SET) in digital circuits. However, many of the fault-based attacks used in cryptanalysis produce faults that can be modeled as bit-flip in memory elements or transient pulses in combinational logic, as in faults due to radiation effects. Experimental results provide information that allows the cryptographic circuit designer to detect the weakest areas in order to implement countermeasures at design stage.

Fault Severity Evaluation and Improvement Design for Mechanical Systems Using the Fault Injection Technique and Gini Concordance Measure

A new fault injection and Gini concordance based method has been developed for fault severity analysis for multibody mechanical systems concerning their dynamic properties. The fault tree analysis (FTA) is employed to roughly identify the faults needed to be considered. According to constitution of the mechanical system, the dynamic properties can be achieved by solving the equations that include many types of faults which are injected by using the fault injection technique. Then, the Gini concordance is used to measure the correspondence between the performance with faults and under normal operation thereby providing useful hints of severity ranking in subsystems for reliability design. One numerical example and a series of experiments are provided to illustrate the application of the new method. The results indicate that the proposed method can accurately model the faults and receive the correct information of fault severity. Some strategies are also proposed for reliability improvement of the spacecraft solar array.

Robustness Analysis of Embedded Control Systems with Respect to Signal Perturbations: Finding Minimal Counterexamples Using Fault Injection

Fault-tolerance of embedded control systems is of great importance, given their wide usage in various domains such as aeronautics, automotive, medical, and so on. Signal perturbations such as small amounts of noise, shift, and spikes, can sometimes severely hamper the performance of the system, apart from complete failure of components and links. Finding minimal counterexamples (perturbations on the system leading to violation of fault-tolerance requirements) can be of great assistance to control system designers in understanding and adjusting the fault-tolerance behavior of the system. Fault injection is an effective method for dependability analysis of such systems. In this paper, we introduce the concept of dominating sets of perturbations, and define a minimal set of counterexamples called the basis. We propose effective methods using a simulation-based fault injection technique on Simulink models for finding the basis set at an early stage of design, given the fault specification and fault-tolerance requirements. Experimental results on two different control system examples from the Simulink automotive library demonstrate the efficacy of the proposed framework.