Fault Detection And Classification Research Articles

40‐3: Waveform Analysis System for GAN‐Based Anomaly Detection of Coater Pressure in Photolithography

With the advancement of manufacturing equipment and the development of sensing technology, the measurement cycle of data is becoming very short, and the characteristics of data observed at the same time are also diversifying. A Fault Detection and Classification (FDC) system is in operation to collect and analyze measurement data in real time in the display manufacturing factory. However, the anomaly detection function provided by the FDC system is based on a threshold comparison method for data in seconds, so there is a limit to accuracy in processing measurement data in milliseconds. In particular, if the process for one panel is divided into several steps and each of them shows various characteristics, it is difficult to manage because it takes a lot of airlift to set search conditions and thresholds for anomaly detection. To overcome this, a waveform analysis system is implemented to assist the FDC system. This system extracts waveforms from milliseconds of measurement data during the processing time of one panel in the equipment, and diagnoses whether the equipment processing is normal through GAN‐based waveform pattern analysis. Generative models are used in the anomaly detection process in consideration of the manufacturing environment in which the normal data is overwhelmingly larger than the abnormal data. The DCGAN‐based model that is excellent in image processing and the TadGAN‐based model that combines Auto encoder and GAN were implemented and used. In this paper, the anomaly detection performance of models is compared and evaluated for the display photo process Coater Pressure sensor using the waveform analysis system implemented in this way.

Detection and classification of photovoltaic module defects based on artificial intelligence

Photovoltaic (PV) system performance and reliability can be improved through the detection of defects in PV modules and the evaluation of their effects on system operation. In this paper, a novel system is proposed to detect and classify defects based on electroluminescence (EL) images. This system is called Fault Detection and Classification (FDC) and splits into four modules, which are (1) Image Preprocessing Module (IPM), (2) Feature Extraction Module (FEM), (3) Feature Selection Module (FSM), and (4) Classification Module (CM). In the first module (i.e., IPM), the EL images are preprocessed to enhance the quality of the images. Next, the two types of features in these images are extracted and fused together through FEM. Then, during FSM, the most important and informative features are extracted from these features using a new feature selection methodology, namely, Feature Selection-based Chaotic Map (FS-CM). FS-CM consists of two stages: filter stage using chi-square to initially select the most effective features and a modified selection stage using an enhanced version of Butterfly Optimization Algorithm (BOA). In fact, BOA is a popular swarm-based metaheuristic optimization algorithm that has only recently found success. While BOA has many benefits, it also has some drawbacks, including a smaller population and an increased likelihood of getting stuck in a local optimum. In this paper, a new methodology is proposed to improve the performance of BOA, called chaotic-based butterfly optimization algorithm. Finally, these selected features are used to feed the proposed classification model through CM. During CM, Hybrid Classification Model (HCM) is proposed. HCM consists of two stages, which are binary classification stage using Naïve Bayes (NB) and multi-class classification stage using enhanced multi-layer perceptron. According to the experimental results, the proposed system FDC outperforms the most recent methods. FDC introduced 98.2%, 89.23%, 87.2%, 87.9%, 87.55%, and 88.20% in terms of accuracy, precision, sensitivity, specificity, g-mean, and f-measure in the same order.

Explainable artificial intelligence-based evidential inferencing on process faults in plasma etching

The fault detection and classification (FDC) modeling proposed in this study is a research approach that is intended to improve the performance of plasma process models by leveraging optical emission spectroscopy (OES) data containing plasma information (PI) and enhancing model interpretability using explainable artificial intelligence (XAI) algorithms. Status variable identification data that included normal and abnormal states of bias power, pressure, SF6 gas flow, and O2 gas flow were collected during a silicon etching process with SF6, O2 gas plasma. Additional variables were derived from the OES data and included additional PI, such as O and F radicals, which were computed using actinometry, and electron temperature and electron density computed using the line ratio method. By building a high-performance FDC model and interpreting its results using XAI algorithms, we propose solutions to the limitations of the FDC model in semiconductor plasma processes.

Advanced Process Monitoring Through Fault Detection and Classification for the Process Development of Tantalum Nitride Thin-Film Resistors

This paper discusses the optimization of an advanced process monitoring scheme with interdicting fault detection and classification (FDC) capabilities that improved the control over the process development of Tantalum Nitride thin film resistors (TaN TFR). Its implementation in a high-volume manufacturing environment resulted in a reduction of misprocessed wafers, shorter equipment downtime, higher throughput, enhanced process visibility, and yield improvement. Along with optimizing FDC capabilities, implementing a short loop sampling plan reduced the turnaround time for early electrical characterization by a factor of four; this allowed for timely inline adjustments within the fabrication process to tighten the statistical process control (SPC) over the distribution of the process control monitor (PCM) TaN resistor value and improve thin film uniformity.

Integration of Artificial Intelligence for Real-Time Fault Detection in Semiconductor Packaging

Semiconductor manufacturing involves a complex sequence of unit processes, where even a minor error can disrupt the entire production chain. Present-day manufacturing setups rely on continuous data monitoring of equipment health, wafer measurements, and inspections to identify any abnormalities that could impact the quality and performance of the final chip. The primary aim is fault detection and classification (FDC), for which a range of techniques including statistical analysis and machine learning algorithms are commonly employed. In this study, we introduce an innovative approach utilizing an artificial immune system (AIS), inspired by biological mechanisms, for FDC in semiconductor equipment. The main culprits behind process failures are shifts caused by the aging of parts and modules over time. Our methodology integrates state variable identification (SVID) data, reflecting current equipment conditions, and optical emission spectroscopy (OES) data, capturing plasma process information under faulty scenarios induced by deliberate gas flow rate adjustments in semiconductor fabrication. Our results demonstrate a modeling prediction accuracy of 94.69% when incorporating selected SVID and OES data, and 93.68% accuracy using OES data alone. In conclusion, we suggest the potential application of AIS in semiconductor process decision-making, offering promising avenues for enhancing fault detection in semiconductor equipment.

Development of Fault Detection Systems: The Hadoop Ecosystem Implementation

Semiconductor manufacturing relies on a long and complex production line for wafer fabrication. In a modern semiconductor fabrication plant (fab), a wafer manufacturing line is composed of more than 1,000 manufacturing tools and an overhead hoist system for delivering wafer lots among the tools. Novel technologies, such as Internet of Things (IoT) and software engineering technologies, are adopted in semiconductor manufacturing such that large amounts of data can be collected from manufacturing tools. Also, these tools and the overhead hoist system should cooperate well with each other. Due to the data-processing capacity limitation in a current fault detection and classification (FDC) system, the diagnosis efficiency is limited such that some undesired events cannot be detected in time, leading to significant economic loss. With the booming development of big data technology, this work conducts a study on a new FDC framework based on a Hadoop ecosystem to deal with the data-processing limitation and improve diagnosis efficiency. Also, a migration path is presented such that the current FDC system can be smoothly migrated to a Hadoop ecosystem-based one without shutting down a wafer fabrication line. Experimental results show that the proposed FDC framework can run safely and stably.

Alleviating Class-Imbalance Data of Semiconductor Equipment Anomaly Detection Study

Plasma-based semiconductor processing is highly sensitive, thus even minor changes in the procedure can have serious consequences. The monitoring and classification of these equipment anomalies can be performed using fault detection and classification (FDC). However, class imbalance in semiconductor process data poses a significant obstacle to the introduction of FDC into semiconductor equipment. Overfitting can occur in machine learning due to the diversity and imbalance of datasets for normal and abnormal. In this study, we suggest a suitable preprocessing method to address the issue of class imbalance in semiconductor process data. We compare existing oversampling models to reduce class imbalance, and then we suggest an appropriate sampling strategy. In order to improve the FC performance of plasma-based semiconductor process data, it was confirmed that the SMOTE-based model using an undersampling technique such as Tomek link is effective. SMOTE-TOMEK, which removes multiple classes and makes the boundary clear, is suitable for FDC to classify minute changes in plasma-based semiconductor equipment data.

Attack and Defense: Adversarial Security of Data-Driven FDC Systems

In modern industries, data-driven fault detection and classification (FDC) systems can efficiently maintain industrial security and stability, while the security of the data-driven FDC system itself is rarely or even never considered. The security problem named adversarial vulnerability is the intrinsic of data-driven machine learning models, which will give incorrect predictions under the maliciously perturbed input data. This paper presents a work on this new security topic of the data-driven FDC systems, by 1) summarizing and comparing various recent and typical adversarial attack and defense methods for fault classifiers; 2) proposing novel attack and defense techniques for unsupervised fault detectors; 3) constructing a novel industrial adversarial security benchmark on FDC systems in the Tennessee-Eastman process (TEP) dataset; 4) exploring and discussing which attack is most potentially threatening for FDC systems and which defense technique is most applicable to mitigate attacks. The results reveal unique security properties of FDC systems, mainly including 1) for fault classifiers, black-box attack is close to the attack strength of white-box FGSM and the universal transferable attack is not significantly stronger than random noise; 2) weak adversarial training is excellent with high adversarial accuracy improvement and negligible clean accuracy decrease; 3) fault detectors are intrinsically more robust, and can be well protected by strong adversarial training. More intriguing properties and profound insights are demonstrated in the paper. This pioneering work could guide researchers and practitioners in discovering and navigating the field of FDC system adversarial robustness, outlining the research directions and open problems.

Intelligent Fault Detection and Classification Based on Hybrid Deep Learning Methods for Hardware-in-the-Loop Test of Automotive Software Systems.

Hardware-in-the-Loop (HIL) has been recommended by ISO 26262 as an essential test bench for determining the safety and reliability characteristics of automotive software systems (ASSs). However, due to the complexity and the huge amount of data recorded by the HIL platform during the testing process, the conventional data analysis methods used for detecting and classifying faults based on the human expert are not realizable. Therefore, the development of effective means based on the historical data set is required to analyze the records of the testing process in an efficient manner. Even though data-driven fault diagnosis is superior to other approaches, selecting the appropriate technique from the wide range of Deep Learning (DL) techniques is challenging. Moreover, the training data containing the automotive faults are rare and considered highly confidential by the automotive industry. Using hybrid DL techniques, this study proposes a novel intelligent fault detection and classification (FDC) model to be utilized during the V-cycle development process, i.e., the system integration testing phase. To this end, an HIL-based real-time fault injection framework is used to generate faulty data without altering the original system model. In addition, a combination of the Convolutional Neural Network (CNN) and Long Short-Term Memory (LSTM) is employed to build the model structure. In this study, eight types of sensor faults are considered to cover the most common potential faults in the signals of ASSs. As a case study, a gasoline engine system model is used to demonstrate the capabilities and advantages of the proposed method and to verify the performance of the model. The results prove that the proposed method shows better detection and classification performance compared to other standalone DL methods. Specifically, the overall detection accuracies of the proposed structure in terms of precision, recall and F1-score are 98.86%, 98.90% and 98.88%, respectively. For classification, the experimental results also demonstrate the superiority under unseen test data with an average accuracy of 98.8%.

Machine Learning-Based Process-Level Fault Detection and Part-Level Fault Classification in Semiconductor Etch Equipment

In the semiconductor manufacturing, which consists of significantly precise and diverse unit processes, minute defects can cause significantly large risk, which is directly related to the yield. Through fault detection and classification (FDC), the equipment status is monitored, and the potential causes of faults can be investigated. In the mass production process, unbalanced data problems are also important, including preprocessing methods for data analysis in real time. This study proposes a stepwise FDC method with a process fault detection (FD) and faulty equipment part classification. Fault detection (FD) is proposed using a one-class support vector machine (OC-SVM) to determine anomalies that occur during a process, and fault classification (FC) is followed by the importance between variables that determine whether a fault exists is extracted using extreme gradient boosting (XGBoost). Variables whose importance has been confirmed, are reclassified to a part-level based on the variable name, and defects are notified to the part-level level. An empirical study to validate the proposed data-based framework for fault detection and diagnosis was performed under the scenario of unexpected failure of two <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathbf {\mathrm {SF}}}_{\mathbf {6}}/{\mathbf {\mathrm {O}}}_{\mathbf {2}}$ </tex-math></inline-formula> mass flow controllers (MFCs). The experimental results confirmed that the application-oriented proposed framework performed well in FDC operations and showed that it can provide part-level notification to engineers.

Using fault detection and classification techniques for machine breakdown reduction of the HGA process caused by the slider loss defect

Fault Detection and Classification (FDC) based on Machine Learning (ML) approach was used to detect and classify mount head fault in the slider attachment process which causes the machine alarm 71 to occur which leads to 2% of machine downtime. This paper has focused on the use of classified pixel surface of mount head with fault difference conditions including Healthy, Fault I, Fault II, and Fault III to detect and diagnose mount head before a vacuum leak. The Artificial Neural Network (ANN) algorithm was a proposed classification model and has to be evaluated before using in the real processes. Three features of mount head surface pixel, i.e., inner, outer, and overall areas were investigated and used as model training data set. The experiment result indicates that the classification using the ANN model with three features performed with an accuracy of 94.3%. According to the result, it was found that the reliability of the production processes of FDC technique has increased as a result of the reduction of machine downtime by 1.886%.

Adaptive fault detection framework for recipe transition in semiconductor manufacturing

The fault detection and classification (FDC) model is a prediction model that utilizes the sensor data of equipment to predict whether each wafer is faulty or not in the future, which is important to achieve a high yield and reduce the cost. To construct a high-performance FDC model with deep learning, a large amount of labeled training data is required. However, in real-world semiconductor manufacturing processes, the transition of recipe leads to a change in the distribution of input sensor data, which causes performance degradation for the existing FDC model. Model retraining for the new recipe is required, but a large time period is required to acquire a large amount of labeled data for the new recipe. In this study, an adaptive fault detection framework is proposed to minimize the performance degradation caused by the transition of recipe. In this framework, immediately after the recipe transition occurs, unsupervised adaptation is employed to reduce the performance degradation. After inspection results for some new recipe wafers are acquired, semi-supervised adaptation is employed to quickly recover the performance with a small amount of labeled data. Through experiments using real-world data, we demonstrate that the proposed framework can adapt to the new recipe with a reduced performance degradation.

Chamber and Recipe-Independent FDC Indicator in High-Mix Semiconductor Manufacturing

This paper describes a chamber and recipe-independent fault detection and classification (FDC) indicator using the example of aluminum sputtering tools. We developed this indicator to detect abnormal discharge in an aluminum sputtering chamber when using a legacy FDC system. Abnormal discharge has several modes in the sputtering chamber, with abnormal discharge to a wafer commonly causing pattern defects. The indicator has been improved to detect only this problem, and to minimize the impact of false alarms that cause a loss of equipment productivity. The indicator can be readily extended to new chambers and the control limits are easily set for all recipes. This is because the equation for the indicator is very simple, and both the equation and the control limits are common to all sputtering chambers and recipes. It can therefore significantly reduce the setup work required of engineers, which is one of the biggest challenges in high-mix semiconductor manufacturing. The indicator is easily applied to newly installed tools at start of production and restrains the number of scrap wafers at minimum level. We also describe the mechanism of trace data changes in abnormal discharge modes using equivalent electrical circuits.

Artificial Immune System for Fault Detection and Classification of Semiconductor Equipment

Semiconductor manufacturing comprises hundreds of consecutive unit processes. A single misprocess could jeopardize the whole manufacturing process. In current manufacturing environments, data monitoring of equipment condition, wafer metrology, and inspection, etc., are used to probe any anomaly during the manufacturing process that could affect the final chip performance and quality. The purpose of investigation is fault detection and classification (FDC). Various methods, such as statistical or data mining methods with machine learning algorithms, have been employed for FDC. In this paper, we propose an artificial immune system (AIS), which is a biologically inspired computing algorithm, for FDC regarding semiconductor equipment. Process shifts caused by parts and modules aging over time are main processes of failure cause. We employ state variable identification (SVID) data, which contain current equipment operating condition, and optical emission spectroscopy (OES) data, which represent plasma process information obtained from faulty process scenario with intentional modification of the gas flow rate in a semiconductor fabrication process. We achieved a modeling prediction accuracy of modeling of 94.69% with selected SVID and OES and an accuracy of 93.68% with OES data alone. To conclude, the possibility of using an AIS in the field of semiconductor process decision making is proposed.

A Realizable Overlay Virtual Metrology System in Semiconductor Manufacturing: Proposal, Challenges and Future Perspective

Integrated circuits (IC) are fabricated on a wafer through stacked layers of circuit patterns. To ensure proper functionality, the overlay of each pattern layer must be within the tolerance. Inspecting each wafer’s overlay is unrealistic and impractical. Hence, wafers are selectively inspected at metrology stations through sampling strategies. With virtual metrology (VM), the metrology quality of the uninspected wafers can be estimated. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), a VM to estimate the overlay of the photolithography process is envisioned. Past researches on overlay VM leveraged fault detection and classification (FDC) data to estimate the overlay errors. As such, for fabs in the progress of completing their FDC development for photolithography equipment, a different modeling approach is required to realize an overlay VM that sustains the production line until FDC data can be leveraged for VM. With practical gaps that must be addressed in real fabs, this paper focuses on realizing an overlay VM for the photolithography process without leveraging FDC data. Therefore, the objectives of this paper are two folds: First, to identify the research challenges towards realizing the overlay VM. Second, to propose the future research perspectives of the envisioned overlay VM. Based on the future research perspectives, a two-steps overlay VM modeling approach utilizing data mining techniques is proposed toward realizing the envisioned overlay VM system. The proposed approach first classifies the process stability at the wafer lot level, and subsequently, performs overlay error estimations for wafers in the wafer lots classified with stable process. Linear regression models are proposed to perform overlay error estimations in this work to augment the interpretability of the overlay VM.

The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor Manufacturing

Virtual metrology (VM) is an enabling technology capable of performing virtual inspection on the metrology quality of wafers. Instead of physically acquiring the metrology measurements, VM applies conjecture models on the process data of wafers to estimate the measurements of the targeted metrology variables. Prior works on overlay VM system utilized fault detection and classification (FDC) data as the process data for the conjecture models. Hence, when FDC data are unavailable owing to FDC system enhancement works, FDC-based VM models would be rendered inefficacious. During such events, a competent VM system using a different modeling approach is required to sustain the production line until FDC data resumes availability and FDC-based VM reaches production state. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), a novel wafer lot-level modeling approach for overlay VM was proposed in our prior work. Using the proposed modeling, a smart sampling scheme was also designed in the same work. The smart sampling scheme consists of two conjecture tasks, with the first task classifies the overlay quality of the wafers, and the second task estimates the overlay errors of the wafers classified with normal overlay quality. The abnormal ones are diverted to the physical metrology station. In this paper, the implementation of a smart sampling system, C2O, using the designed scheme and its experimental results are presented. The experimental results showed that C2O is capable to achieve a true positive rate (TPR) of 71.34% for the classification task and mean absolute scaled error (MASE) of 9.59 for the regression task. The obtained results set the baseline to measure the efficacy of future enhancement works, which have been enlisted and underway to augment the performance of the system so that its competency meets the requirements of real fab.

Effective Maintenance by Reducing Failure-Cause Misdiagnosis in Semiconductor Industry (SI)

Increasing demand diversity and volume in semiconductor industry (SI) have resulted in shorter product life cycles. This competitive environment, with high-mix low-volume production,requires sustainable production capacities that can be achieved by reducing unscheduled equipment breakdowns. The fault detection and classification (FDC) is a well-known approach, used in the SI, to improve and stabilize the production capacities. This approach models equipment as a single unit and uses sensors data to identify equipment failures against product and process drifts. Besides its successful deployment for years, recent increase in unscheduled equipment breakdown needs an improved methodology to ensure sustainable capacities. The analysis on equipment utilization, using data collected from a world reputed semiconductor manufacturer, shows that failure durations as well as number of repair actions in each failure have significantly increased. This is an evidence of misdiagnosis in the identification of failures and prediction of its likely causes. In this paper, we propose two lines of defense against unstable and reducing production capacities. First, equipment should be stopped only if it is suspected as a source for product and process drifts whereas second defense line focuses on more accurate identification of failures and detection of associated causes. The objective is to facilitate maintenance engineers for more accurate decisions about failures and repair actions, upon an equipment stoppage. In the proposed methodology, these two lines of defense are modeled as Bayesian network (BN) with unsupervised learning of structure using data collected from the variables (classified as symptoms) across production, process, equipment and maintenance databases. The proofs of concept demonstrate that contextual or statistical information other than FDC sensor signals, used as symptoms, provide reliable information (posterior probabilities) to find the source of product/process quality drifts, a.k.a. failure modes (FM), as well as potential failure and causes. The reliability and learning curves concludes that modeling equipment at module level than equipment offers 45% more accurate diagnosis. The said approach contributes in reducing not only the failure durations but also the number of repair actions that has resulted in recent increase in unstable production capacities and unscheduled equipment breakdowns.

Data-Driven Approach for Fault Detection and Diagnostic in Semiconductor Manufacturing

Fault detection and classification (FDC) is important for semiconductor manufacturing to monitor equipment’s condition and examine the potential cause of the fault. Each equipment in the semiconductor manufacturing process is often accompanied by a large amount of sensor readings, also called status variable identification (SVID). Identifying the key SVIDs accurately can make it easier for engineers to monitor the process and maintain the stability of the process and wafer productive yields. This article proposes using the random forests algorithm to analyze the importance of SVIDs of equipment sensors, automatically filters the key SVID by using ${k}$ -means, and integrates various machine learning methods to verify the key SVIDs and identify key processing time and steps. Upon the key parameters are identified, the key processing time and steps are investigated subsequently. The ensemble models constructed on ${k}$ -nearest neighbors ( ${k}$ NNs) and naive Bayes classifiers are presented for classifying wafers as normal or abnormal. Data visualization of multidimensional key SVIDs is performed by using ${t}$ -distributed stochastic neighbor embedding ( ${t}$ -SNE) to create a graphical aid in FDC for the process engineer. An empirical study is conducted to validate the proposed data-driven framework for fault detection and diagnostic. The experimental results demonstrate that the proposed framework can detect abnormality effectively with highly imbalanced classes and also gain insightful information about the key SVIDs and corresponding key processing time and steps. Note to Practitioners —The challenges of equipment sensor data analytics in semiconductor manufacturing include building the classifier to detect wafer abnormality correctly, identification of key status variable identifications (SVIDs) and processing time and steps of abnormality, and data visualization of the abnormality in a high-dimensional feature space. This article proposes a data-driven framework for fault detection and classification (FDC) during the wafer fabrication process by incorporating several useful machine learning approaches. Experimental results demonstrate that the proposed data-driven framework can supply quality fault detection performances and provide valuable information regarding the critical SVIDs and associated key processing time for fault diagnostic. The engineers can utilize the extracted fault patterns to perform a prognosis of the aging effect on process tools or modules for health management.

A physics-informed Run-to-Run control framework for semiconductor manufacturing

For decades, Run-to-Run (R2R) controllers have been widely implemented in semiconductor manufacturing. They operate over key process parameters on the basis of the metrological measurements acquired from the process and their deviations from the target setpoints. Conventionally, R2R controllers have been implemented independently of the actual equipment condition, which is obviously affecting the process stability and performance. Therefore, both equipment signals and process states shall be considered to make the R2R controllers more robust to the equipment condition drifts. In this paper, we propose a novel physics-informed framework to integrate the real-time equipment condition, based on the Fault Detection and Classification (FDC) data, into the R2R controllers. By utilizing Dynamic Bayesian Networks (DBN), the implicit relationship structure between metrology measurements, FDC indicators, and R2R regulators can be learned and reviewed explicitly. The structure shall be further reviewed to valid with the existing relationships and expert knowledge. Infeasible causalities on the structure will be constrained via setting up the blacklist at the structure learning stage. The proposed framework consists of the offline modeling stage, which incorporates the process, equipment variables, and the expert knowledge in the structure learning, and the online control stage, which constructs the Structured R2R controller (SRC) based on the relationship structure. As a result, the model is consistent by design with empirically known relationships and fundamental physical laws. The proposed SRC not only optimizes the operation with respect to the target control values but also considers the equipment and process states simultaneously. The effectiveness of SRC and the derivative control strategy are validated through a real dataset of a Chemical-Mechanical Polishing (CMP) process, and two simulated studies.

SSDTW: Shape segment dynamic time warping

In order to increase the yield of a process, it is essential to establish a process control based on manufacturing data. Process management systems mainly consist of statistical process control (SPC), fault detection and classification (FDC), and advanced process control (APC), and are modeled using time series data. However, large amounts of time series data and various distributions are collected in the process; hence, preprocessing measures, such as length adjustment, are essential for modeling. Dynamic time warping (DTW) has been widely used as an algorithm that can measure the similarity between two different time series data and adjust their length. However, owing to the complex structure and time lag of processing time series data, there are limitations in applying the traditional DTW. Therefore, to solve this problem, we propose the shape segment dynamic time warping (SSDTW) algorithm that improves DTW in consideration of the structure information of time series data. By using the maximum overlap discrete wavelet transform (MODWT), the proposed method reflects the peripheral information of the time series data and divides the time series data interval to achieve a reasonable local alignment path. SSDTW attains more accurate alignment paths than DTW, derivative dynamic time warping (DDTW), and shapeDTW. Experiments conducted using semiconductor signal data and UCR time series data sets show that the proposed method is more effective than DTW, DDTW, and shapeDTW.