Fault Current Suppression Research Articles

Experimental analysis of a multi-phase resonance-based fault current limiter prototype under symmetrical and asymmetrical faults

Expansion of power systems and involving more distributed generation cause to increase in fault current levels. This paper presents a three-phase resonance-based solid-state fault current limiter (FCL) prototype that has series and parallel resonance modes developed to suppress fault currents of power systems. The laboratory-scaled prototype is located on a three-phase test circuit and has been examined with the fault types of three-phase, three phase-to-ground, two phase-to-ground, and phase-to-ground. The performance and effectiveness of the proposed series-parallel resonance-type fault current limiter (SPRFCL) are validated with the comparison of Matlab/Simulink simulations and experimental test results. Fault currents in different types of faults are limited to an allowable value at high rates and experimental results are considerably close to current values obtained from each fault simulation. Fault currents of faulted phases are restricted with the limiting rates ranging from 75 % to 85 % concerning prospective fault currents in the non-FCL situations. Short-circuit test results of the prototype of SPRFCL that is supplied from a 380 V grid revealed that it acts stable and successful operation regardless of fault type. Accordingly, it has a favorable circuit design for power system applications.

A combined regulation method of transient power angle stability control and fault current suppression for VSG

When a serious grid fault occurs, a virtual synchronous generator (VSG) tends to lose transient power angle stability (TPAS) and cause the fault current to exceed the limit. Most existing research usually neglects the inherent relationship between transient power angle instability (TPAI) and fault over-current (FOC), which leads to the two problems being solved separately rather than simultaneously. In this paper, the transient power angle and fault current characteristics of VSG are first studied, and the causes and influencing factors of TPAI and FOC are explored. Then, the TPAS analysis is carried out based on the phase portrait theory. A TPAS control method for VSG considering fault current suppression (FCS) is proposed. This method is fulfilled by the combined regulation of active power reference and reactive voltage regulation coefficient, in which the reference and coefficient can be adjusted adaptively according to different fault degrees and application scenarios. In addition, a quasi-static approximate (QSA)virtual inductance is introduced to limit the instantaneous inrush current (IIC). The proposed method achieves both the TPAS and FCS at the same time during the fault. Finally, simulations and experiments verify the correctness of the theoretical analysis and the proposed method.

Transient research on distribution networks incorporating superconducting cables utilizing field–circuit coupling method

High temperature superconducting (HTS) cable represents a promising solution for fulfilling the power demands of cities with large loads and high density. However, due to their connection to the distribution network, HTS cables are vulnerable to fault currents exceeding ten times their rated current, which poses a serious threat to both the safety of the cable and the operation of the grid. Considering the highly nonlinear nature of superconducting conductivity, this study develops a field–circuit coupling model to investigate the transient characteristics of distribution networks incorporating superconducting cables (DNSC). Firstly, a finite element model based on the two-dimensional H formulation was built to calculate the electrical and thermal parameters of the HTS cable. Subsequently, an equivalent circuit model of the distribution network was employed to estimate the short-circuit currents. Communicating via a co-simulation server, the superconducting cable current and distribution network impedance were updated in each step. Further, based on an actual DNSC system in Shenzhen, China, the highest quenching temperature of the cable and the maximum fault current of busbars were assessed. Finally, by integrating current limiters into the system, the withstand capability of the cable and busbars was determined, which indicates that the improved protection configuration can effectively suppress fault currents and ensure safe operation. Successfully applied to an actual distribution network, the co-simulation model utilizing the field–circuit coupling method addresses the challenges of solving highly nonlinear and time-varying systems, enabling transient analysis and protection research for the integration of superconducting devices into the conventional grid.

Three‐phase isolated power transformer based novel structure for power distribution system and new theoretical/practical judgement criteria in detecting high‐impedance earth faults

AbstractSingle phase‐earth faults are the most frequent faults likely to occur but hard to identify in distribution system, especially in a neutral un‐effectively grounded system. To address this issue, this paper innovatively proposes a typical distribution system structure, in which it only introduces one three‐phase isolated power transformer (PT)‐based subnetwork division mode that can effectively limit the zero‐sequence current flow from other sound lines. Second, following the qualitative discussions about the effect of the proposed structures on power supply reliability and probability of bushfires caused by high impedance earth faults (HIEFs), a novel detecting judgement criterion merely using vector‐based variation via pre‐fault and post‐fault zero‐sequence voltage is mathematically formulated. In general, the proposed structure takes into account the the fault current suppression while manifesting fault feature at the same time, and in contrast with current detecting methods, vectorized form can present a wider exploring space and a higher identifying sensitivity, especially in detecting HIEFs. Numerical simulations and field tests validate the effectiveness and adaptability of the proposed detecting approach towards single phase‐earth fault identification field.

Zero-sequence current suppression control for fault current damper based on model predictive control

In a multi-terminal direct current (MTdc) system based on a modular multilevel converter (MMC), high-speed and large interruption capability direct current circuit breakers (dc CBs) are required for dc fault interruption. However, commercializing these breakers is challenging, especially offshore, due to the large footprint of the surge arrester. Hence, a supplementary control is required to limit the rate of current rise along with the fault current limiter. Furthermore, the operation of the dc CB is not frequent. Thus, it can lead to delays in fault interruption. This study proposes the indirect model predictive control (MPC)-based zero-sequence current control. This control provides dc fault current suppression by continuously controlling the zero-sequence current component using circulating current suppression control (CCSC) and by providing feedback to the outer voltage loop and inner current loop of MMCs. The proposed control is simulated for pole-to-pole and pole-to-ground faults at the critical fault location of an MTdc system. The simulation is performed in Real Time Digital Simulator (RTDS) environment, which shows that the predictive control reduces the rate of rise of the fault current, providing an additional 3 ms after the dc fault occurrence to the dc CB to clear the fault. Besides, the energy absorbed by the dc CB’s surge arrester during the pole-to-pole and pole-to-ground fault remains the same with the proposed control.

Advanced Fault Tolerant 3×3-Phase PM Drive With Concentric Winding for EV Application

Fault tolerant machine drive is essential for EV application to ensure uninterrupted operation during fault event. Among various fault modes, inter-turn fault is the most challenging failure for the PM drive which requires special measures to suppress the excessive fault current. In this paper, a novel concentric winding (CW) is analyzed for a 3×3-phase PM drive to restrict the turn fault current. Compared with the conventional distributed winding (DW), the two sub-coils of each phase occupy the same space angle and both align with the phase axis, and the winding factor of each coil is 0.96 which is 4% lower than the DW. Owing to the two aspects, the coil flux linkages are more effectively nullified after applying winding terminal short circuit (TSC) which indicates lower fault current. The two machines’ healthy performance as well as various fault modes’ behaviors are investigated by detailed simulation and test investigation. The results prove the CW machine has the same healthy characteristics as the DW machine, and the maximum inter-turn fault current is up to 17% lower than the counterpart. In addition, the improved turn fault current suppression capability is achieved simply by re-arranging the coil layout without introducing any extra cost.

Fault current analysis and active current limiting strategy for hybrid cascaded LCC/MMC HVDC system

The hybrid cascaded LCC/MMC high voltage direct current (HC-HVDC) system is a prospective topology that can avoid the commutation failure problem of LCC-HVDC while ensuring bulk power transmission capability. However, the complex topology results in different DC fault characteristics at the receiving end, which brings challenges to fault detection and current limiting technology. As a result, it is of great theoretical importance to investigate the fault characteristics of the HC-HVDC system and propose the corresponding fault current limiting strategy. Firstly, this paper simplifies the equivalent discharging circuit of the hybrid cascaded LCC/MMC inverter into a first-order RL circuit by assuming the firing-advance angle is constant after fault, and proposes the fault current expressions by Laplace transform. Secondly, by changing the insertion sequence of submodules, an active fault current limiting strategy based on the submodule sorting algorithm (SMS-FCL) is proposed, which can accomplish fault current suppression, reactive power and DC voltage support, and energy loss reduction simultaneously. Moreover, the proposed SMS-FCL can cooperate with other FCLs to further suppress the fault current, and the cooperation prerequisites are analyzed. Finally, an LCC-LCC/MMC HVDC system is built in PSCAD/EMTDC to validate the accuracy of the proposed fault current expressions and the effectiveness of the current limiting strategy.

Development of cryogenic insulation supporter module for a 220 kV 2G-tape-based resistive fault current limiter

Resistive type superconducting fault current limiter (R-SFCL) is one of the most promising candidates to suppress fault currents in power grids. However, the violently boiled cryogen liquids, commonly liquid nitrogen, occurred due to fault currents, poses a crucial cryogenic insulation challenge for R-SFCL. Here we report the design and development of a Cryogenic Insulation Supporter Module (CISM) for a 220 kV R-SFCL. First, we present the design and test of the prototype Cryogenic Insulations Supporter (CIS). The developed CIS passed the high voltage tests under operating conditions. Following on this, we then present the design of CISM, which consists of 14 CISs, with the length and outer diameter of 12 m and 2.5 m, respectively.

DC fault current approximation and fault clearing methods for hybrid LCC-VSC HVDC networks

The DC-side fault analysis of Line commutated converter based high voltage direct current (LCC-HVDC) and Voltage source converter based high voltage direct current (VSC-HVDC) networks has been studied by most researchers and achieved fruitful results. However, the traditional fault analysis method does not consider in detail the change process of the trigger angle of the LCC converter station and the AC current feeding of the VSC converter station caused by the control strategy. Therefore, this paper proposes a new DC side fault transient analysis method suitable for hybrid multi-terminal HVDC transmission networks. In addition, considering the deficiency that the active fault current suppression method only relying on the control strategy cannot fundamentally clear the DC fault, this paper proposes a new Z-source current-limiting circuit (ZCLC) with reference to the topology of the Z-source dc circuit breaker (DCCB). Then, ZCLC will cooperate with DCCB to improve the fault clearing capacity of the whole system. Firstly, this paper establishes the equivalent Laplace transform model of the three-terminal LCC-VSC-VSC, and analyzes the short-circuit current expression on both sides. Then, the change process of trigger angle is approximately linearized by the least square method, which obtains a new expression of fault transient current on the LCC side. Similarly, the composition of AC current fed to DC side is deduced by using the commonly used inner-loop PI controller model, which also obtains a new expression of fault transient current on the VSC side. Secondly, referring to the traditional crossed-type Z-source DCCB, series-type Z-source DCCB, and parallel-type Z-source DCCB, this paper also proposes a new ZCLC and analyzes its working principle and parameter design. Then, the newly proposed ZCLC is combined with DCCB to be applied to the hybrid multi-terminal HVDC network. Finally, the simulation results based on Matlab/Simulink verify the effectiveness of the fault analysis and passive fault clearing methods, and the semi-physical experimental platform based on PLECS/RTbox verifies the superiority of the new ZCLC.

Fast DC Fault Current Suppression and Fault Ride-Through in Full-Bridge MMCs via Reverse SM Capacitor Discharge

In the event of a DC side fault in modular multilevel converters (MMCs), the fault current contributions are initially made by submodule (SM) capacitor discharge, which occurs before the fault is detected, followed by the AC side contribution to the DC side fault. While the AC side currents can be regulated using fault blocking SMs, the initial discharge of the SM capacitors results in high DC fault currents, which can take several milliseconds to be brought under control. This paper presents a method to actively control the rate of rise of the DC fault current by regulating the discharge of SM capacitors and accelerating the suppression of fault current oscillations during fault ride-through (FRT) in a full-bridge (FB)-MMC system. In the proposed method, the discharge direction of the FBSM capacitors is reversed following the detection of a DC side fault, which leads to a reversal in the fault current direction and a fast drop-off towards the zero-crossing. Immediately after the zero-crossing of the DC fault current, the DC fault is cleared by adjusting the arm voltage references and operating the MMC as a static synchronous compensator (STATCOM) to provide voltage support to the AC grid. The proposed control scheme provides faster fault current suppression, more effective SM capacitor voltage regulation, low AC side and MMC arm current transient peaks, and an overall superior DC-FRT performance compared to methods in which the conventional fault ride-through operation is initiated immediately upon DC fault detection.

Analysis of the influence factors of VSC–HVDC on AC three-phase short-circuit current level

PurposeThis paper aims to clarify voltage sourced converter’s (VSC’s) influence rules on the alternating current (AC) short-circuit current and identify the key factors, so as to propose the short-circuit current suppression strategy.Design/methodology/approachThis paper investigates the key factors which impact the short-circuit current supplied by the VSC based on the equivalent current source model. This study shows that the phase of the VSC equivalent current source is mainly affected by the type of fault, whereas the amplitude is mainly decided by the control mode, the amplitude limiter and the electrical distance. Based on the above influence mechanism, the dynamic limiter with short-circuit current limiting function is designed. The theoretical analysis is verified by simulations on PSCAD.FindingsThe short-circuit current feeding from VSC is closely related to the control mode and control parameters of the VSC, fault type at AC side and the electrical distance of the fault point. The proposed dynamic limiter can make VSC absorb more reactive power to suppress the short-circuit current.Research limitations/implicationsThe dynamic limiter proposed in this paper is limited to suppress three-phase short-circuit fault current. The future work will focus more on improving and extending the dynamic limiter to the fault current suppression application in other fault scenarios.Practical implicationsThe research results provide a reference for the design of protection system.Originality/valueThe key influence factors are conducive to put forward the measures to suppress the fault current, eliminate the risk of short-circuit current exceeding the standard and reduce the difficulty of protection design.

An adaptive‐impedance fault current limiter for accelerating fault current suppression in MMC‐HVDC systems

DC fault clearance is one of the critical issues for the modular-multilevel-converter-based high voltage direct current (MMC-HVDC) systems. Employing a hybrid DC circuit breaker (H-DCCB) to isolate the faulty line is a typical method to achieve fast fault clearance. However, the H-DCCB has to interrupt the fault current and absorb the energy up to tens of megawatts in several milliseconds. Through theoretical analysis of the interruption process using the H-DCCB, reducing the equivalent inductance of the fault circuit during the fault falling stage is recommended to accelerate the fault current suppression for the H-DCCBs. This paper proposes a novel adaptive-impedance fault current limiter (AFCL), which contains two coupled DC reactors and an energy absorption branch (EAB). The proposed AFCL can automatically limit the fault current during the current rising stage and works as a DC reactor with a fixed equivalent inductance through a two-state model analysis. Meanwhile, the AFCL contributes to accelerating the decline of the current by adaptively reducing the inductance of the discharge circuit. Consequently, the fault current suppression time and the energy absorbed by the H-DCCB are reduced. Simulation case studies and hardware experiments are carried out to verify the performance and practicality of the proposed AFCL.

Fault current calculation in MTDC grids considering MMC blocking

In this paper, a generic fault current calculation method based on coupled differential equations is proposed which is valid for both blocked and unblocked states of the MMC. The first part of the paper concerns the modeling aspects of MMCs in blocked and unblocked states, while the second part focusses on the representation of the DC grid. Overhead lines are modeled as lumped RL-elements, whereas cables are represented by an adapted π-model in order to consider the capacitor discharge. A simplified DC Circuit Breaker model is integrated into the set of coupled differential equations, which allows to estimate the energy absorption requirements during fault current suppression. The results of the method are compared to EMT simulation results and validated throughout different fault scenarios. The method enables the representation of temporary MMC blocking for a large timeframe of tens of milliseconds after fault occurrence and is convenient for the sizing of DC Circuit Breakers and DC reactors in MTDC grids.

Doubly Fed Induction Generator Low Voltage Ride Through Improvement Through Modular Multilevel Converter

This paper proposes a novel fault current suppression method for doubly fed induction generator (DFIG) low voltage ride through (LVRT) improvement employing modular multilevel converter (MMC). It is based on the inherent MMC arm impedance and the number of levels to provide transient damping of DFIG rotor and stator currents under severe grid faults, contributing effectively to maintaining the DFIG connection while ensuring controllability by avoiding the protection activation. Neither additional hardware nor control loops are necessary. DFIG dynamic equations under LVRT, including the contribution of the MMC, are presented, and a model is derived for control design. Performance assessment, including symmetrical and asymmetrical fault scenarios for MMC with 3, 21, 51, and 101 levels and comparison with existing and proposed controllers, highlighted that arm impedance and increased MMC level number contributed to DFIG stator and rotor fault current suppression, providing DFIG LVRT improvement under severe grid fault conditions.

Hybrid DC circuit breaker with fault current suppression capability

Hybrid DC circuit breaker with fault current suppression capability

A multiport superconducting fault‐current‐limiting circuit breaker for a flexible DC power grid

The fault current of the high-voltage and large-capacity flexible DC power grid has the characteristics of a fast rising rate, high peak value, and large influence area; therefore, fault current suppression equipment suitable for the flexible DC power grid has become a research hotspot. First, the fault mechanism and fault current calculation associated with the DC converter are analysed in this study; subsequently, a multiport superconducting fault-current-limiting circuit breaker (SFCLCB) suitable for a flexible DC power grid is designed. The circuit breaker adopts ground drainage to transfer the fault current. It only needs to be equipped with a single-way conduction power electronic switch group and the number of switches is not affected by the number of DC lines, considerably improving the cost effectiveness of the equipment. In addition, the workflow and current-limiting principle of SFCLCB are analysed, and the optimal matching method is determined with respect to the resistance of the superconducting current limiter and the power electronic devices of the main circuit breaker. Afterwards, the four-terminal flexible DC transmission simulation system is observed to exhibit high efficiency in suppressing the fault current and high cost effectiveness based on comparative simulations. Finally, its engineering applicability is verified by the digital physical and hybrid simulation platform.

Construction of a Digital and Physical Hybrid Simulation Platform for MMC-HVDC Grid With Fault Current Suppression Equipment

In order to fully study the working characteristics of large-scale power electronic devices in the field of renewable energy delivery, it is imperative to build digital and physical hybrid simulation platforms. A power interface algorithm based on damping impedance is proposed to improve the stability of DC power grid hybrid platforms. Firstly, according to the characteristics of the open-loop transfer function of the damping impedance method, the matching principle between damping impedance at the power interface and equivalent impedance of the physical simulation system is obtained. Secondly, the calculation method of the equivalent impedance of multi-type equipment on the physical side is proposed, and the impedance real-time matching under different working conditions is realized. In order to reduce the simulation error caused by interface delay, a DC voltage interface delay compensation method based on slope prediction is proposed, and a prediction compensation model is established. A digital and physical hybrid platform for a four-terminal flexible DC power grid with DC circuit breakers is built to verify the proposed interface algorithm. The simulation results show that the proposed interface algorithm can effectively compensate for the interface delay and ensure the stable operation of the platform under different conditions.

Fast recovery strategy for MMC-HVDC based on coordination of fault current suppression and adaptive restart

Abstract The rapid suppression of fault current flowing through overhead transmission lines and safe restart of the system are critical problems to be solved urgently to improve the stability of the DC grid. A novel adaptive restart strategy combined with fault current suppression is proposed, which suitable for full-bridge modular multilevel converter high voltage direct current system. The resistance-capacitance energy transfer branch is used to achieve a large reduction and rapid attenuation of the fault current amplitude at restart time. The transient fault and permanent fault can be discriminated in a short interval after restarting based on the frequency domain amplitude characteristics. The proposed scheme has both restart-current protection and fault property identification functions, overcoming the high cost and low component reusability of traditional single-function fault current limiting schemes. The simulation results show that the scheme has a significant fault current suppression effect and accurately discriminates the fault property to realize rapid recovery.

A novel solution for fault current suppression in transmission systems based on fault current splitters

To mitigate the threat from increasing fault current level in high-voltage transmission systems, a “dredging theory” based on the fault current splitter (FCS) was proposed to help the over-duty circuit breaker clear the fault. However, detailed practice of this theory is not fully studied. This paper investigates the feasibility of suppressing the fault current by FCSs from the perspectives of operation and planning. The operating scheme of FCSs is firstly qualitatively analyzed, and an iterative formula is derived to calculate the fault current in a system including multiple FCSs. Furthermore, the voltage sag caused by FCSs is evaluated by the Specified Computer Business Equipment Manufacturer Association (SCBEMA) curve and is minimized by the proposed optimization model considering maximum fault current limitation. A repeat-searching particle optimization (RSPSO) algorithm is developed to solve the model efficiently. This solution is validated to be effective and acceptable through two case studies.

A Mutual-Inductance-Type Fault Current Limiter in MMC-HVDC Systems

Faults on the dc line threaten the stability and reliability of the modular-multilevel-converter-based HVDC (MMC-HVDC) systems. Fault current limiting is one of the crucial steps to handle the dc line fault. In this paper, a mutual-inductance-type fault current limiter (MFCL) using coupled reactors and few power electronic switches is proposed. Compared with the conventional dc reactors, it can automatically limit the fault current during the current rising stage with an increased equivalent inductance and accelerate the decline of the current by reducing the inductance of the discharge circuit. Consequently, the fault current stress and the total capacity of required arresters are decreased. Compared with the existing power electronic-type fault current limiters, the proposed MFCL provides an inexpensive and potential solution to the suppression of dc fault current using simple fault current limiting topology with fewer power electronic switches. The simulation case study and hardware experiments are carried out to verify the performance and practicality of the proposed MFCL.