Fault Coverage Metrics Research Articles

A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks

With the continuous growth in technology, the role of nano-electronic systems is rapidly expanding in every facet of modern life. Subsequently, the demand of high performance computations and communications by many applications in order to interact with environment and users has become a compulsion. Traditional integrated circuit-based systems, e.g., bus-based systems-on-chip (SoCs), as a consequence are turned into networks- on-chips (NoCs) because of the communication bottleneck by the SoCs. Though, the NoCs visibly move the concern and meet the requirements by the applications but fabricating such NoCs without any defect in channels or logics has eventually evolved into a major challenge. Indeed, one of the major demand nowadays for such systems is to design a time-efficient mechanism for the pre- and post-manufacturing testing of NoC functional components, in order to guarantee outgoing quality while not sacrificing yield and reliability. This paper presents a cost effective and distributed on-line test mechanism that addresses channel-shorts in NoC-based systems. The proposed mechanism detects and diagnoses both intra- and inter-channel short faults. The test mechanism additionally targets transient and stuck-at faults in channels. A convenient test scheduling and energy model are presented. The scheduling scheme offers constant test time with little hardware area and performance overheads on the NoCs irrespective of their topologies and sizes. The proposed test solution is evaluated with fault injection campaign in channels of a set of NoC architectures. Fault simulation detects all modeled faults in channels resulting 100% test and fault coverage metrics. On-line evaluation of the proposed solution reveals insights of the effect of channel-shorts on various performance metrics at large amount of traffic. Furthermore, the proposed solution improves various quality metrics on the set of NoCs, for instance, the test area overhead is reduced up to 28% while the proposed model becomes 16 × faster. Also, improvement on the performance overhead is noticed. The packet latency for instance, is improved by 14.98---50.67% while packet flit energy consumption is reduced by 6.83---43.89%. Such improvements are found to grow with NoC size.

Energy-efficient Custom Topology Generation for Link-failure-aware Network-on-chip in Voltage-frequency Island Regime

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

I DDQ testing as a component of a test suite: The need for several fault coverage metrics

This article is concerned with the role of I DDQ testing, in conjunction with other types of tests, in achieving high quality. In particular, the argument is made that rather than use a single fault coverage, it is better to obtain a number of different coverages, for different types of faults. To demonstrate the need for increasingly stringent fault coverage requirements, an analysis is given of the relationship between quality, fault coverage and chip area. This analysis shows that as chip area increases, fault coverage must also increase to maintain constant quality levels. Data are then presented from a production part tested with Iddq scan, timing and functional tests. To realistically fault grade I DDQ tests, three different coverage metrics are considered. The data show differences in tester failures compared to these coverage metrics, depending on whether one uses total Iddq failures (parts which fail Iddq regardless of whether they fail other tests as well) or unique IDdq failures (parts which fail only Iddq). The relative effectiveness of the different components of the full test suite are analyzed and it is demonstrated that no component can be removed without suffering a reduction in quality.