Faster Design Convergence Research Articles

Γ (Gamma): A SaaS-enabled fast and accurate analog design System

With ever increasing demand for lower power consumption, lower cost, and higher performance, designing analog circuits to meet design specifications has become an increasing challenging task, Analog circuit designers must, on one hand, have intimate knowledge about the underlining silicon process technology׳s capability to achieve the desired specifications. They must, on the other hand, understand the impact of tweaking circuits to satisfy a given specification on all circuit performance parameters. Analog designers have traditionally learned to tackle design problems with numerous circuit simulations using accurate circuit simulators such as SPICE, and have increasingly relied on trial-and-error approaches to reach a converging point. However, the increased complexity with each generation of silicon technology and high dimensionality of searching for solutions, even for some simple analog circuits, have made the trial-and-error approach extremely inefficient, causing long design cycles and often missed deadlines. Novel rapid and accurate circuit evaluation methods that are tightly integrated with circuit search and optimization methods are needed to aid design productivity.Furthermore, the current design environment with fully distributed licensing and supporting structures is cumbersome at best to allow efficient and up-to-date support for design engineers. With increasing support and licensing costs, fewer and fewer design centers can afford it. Cloud-based software as a service (SaaS) model provides new opportunities for CAD applications. It enables immediate software delivery and update to customers at very low cost. SaaS tools benefit from fast feedback and sharing channels between users and developers and run on hardware resources tailored and provided for them by the software vendor. On the downside, web-based tools are expected to perform in a very short turn-around schedule and be always responsive.This paper presents a list of innovations that come together to a new class of analog design tools: 1). Lookup table-based approach (LUT) to model complex transistor behavior provides both the necessary accuracy and speed essential for repeated circuit evaluations. 2). The proposed system architecture tight integrate the novel LUT approach with novel system level functions to allow further significantly better accuracy/speed tradeoff and faster design convergence with designer׳s intent. 3). Incorporating use inputs at key junctures of the design process allows the tool to better capture designer׳s intent and improve design convergence. 4). The combination of high accuracy and faster evaluation time make it possible to incorporate SaaS features, such as short solution space navigation steps and crowdsourcing, into the tool. This allows sharing of server-side resources between many users. Instead of fully automating a signoff circuit optimization process, the proposed tool provides effective aid to analog circuit designers with a dash-board control of many important circuit parameters with several orders faster in computation time than SPICE simulations.

Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence

With the ever-increasing power demands of consumer electronics and portable devices, multi-supply voltage (MSV) technique is supposed as one of the direct and effective ways for power optimization in SoC designs. To realize MSV implementation, procedures such as voltage assignment, voltage island partitioning and level shifters (LSs) placement should be considered simultaneously during the floorplanning stage. Although many works addressed the MSV-driven design problem, few of them actually took account of LS placement, which makes the generated results may limit the potential applications. Furthermore, existing design frameworks are often very computationally expensive, and it is not beneficial to shorten the time to market. In this paper, we present an MSV-driven SoC floorplanning framework for fast design convergence. Several techniques are proposed and integrated into an efficient and flexible non-randomized floorplanning algorithm. Firstly, to reserve the desired deadspace for the placement of LSs, the netlist is modified by assigning virtual LSs in the nets. Secondly, a heuristic based voltage assignment method is presented for accuracy and execution time trade-off. Thirdly, different from previous works which do voltage assignment without physical information feedback, an inner loop is built between voltage assignment and LS placement under the constraints of both timing and physical layout. Experimental results on Gigascale Systems Research Center (GSRC) benchmark suites indicate the proposed approach can improve power saving by 12%, CPU time by 48% with 4% area increase.

An Entropic Method for Sequencing Discrete Design Decisions

This paper presents a mathematical model for quantifying uncertainty of a discrete design solution and to monitor it through the design process. In the presented entropic view, uncertainty is highest at the beginning of the process as little information is known about the solution. As additional information is acquired or generated, the solution becomes increasingly well-defined and uncertainty reduces, finally diminishing to zero at the end of the process when the design is fully defined. In previous research, three components of design complexity—size, coupling, and solvability—were identified. In this research, these metrics are used to model solution uncertainty based on the search spaces of the variables (size) and the compatibility between variable values (coupling). Solvability of the variables is assumed uniform for simplicity. Design decisions are modeled as choosing a value, or a reduced set of values, from the existing search space of a variable, thus, reducing its uncertainty. Coupling is measured as the reduction of a variable’s search space as an effect of reducing the search space of another variable. This model is then used to monitor uncertainty reduction through a design process, leading to three strategies that prescribe deciding the variables in the order of their uncertainty, number of dependents, or the influence of on other variables. Comparison between these strategies shows how size and coupling of variables in a design can be used to determine task sequencing strategy for fast design convergence.

Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model

Preventing silicon chips from negative, even disastrous thermal hazards has become increasingly challenging these days; considering thermal effects early in the design cycle is thus required. To achieve this, an accurate yet fast temperature model together with an early-stage, thermally optimized, design flow are needed. In this paper, we present an improved block-based compact thermal model (HotSpot 4.0) that automatically achieves good accuracy even under extreme conditions. The model has been extensively validated with detailed finite-element thermal simulation tools. We also show that properly modeling package components and applying the right boundary conditions are crucial to making full-chip thermal models like HotSpot accurately resemble what happens in the real world. Ignoring or over-simplifying package components can lead to inaccurate temperature estimations and potential thermal hazards that are costly to fix in later designs stages. Such a full-chip and package thermal model can then be incorporated into a thermally optimized design flow where it acts as an efficient communication medium among computer architects, circuit designers and package designers in early microprocessor design stages, to achieve early and accurate design decisions and also faster design convergence. For example, the temperature-leakage interaction can be readily analyzed within such a design flow to predict potential thermal hazards such as thermal runaway.

Efficient synthesis methodology for optimal inverter-based transimpedance amplifiers

In this paper, we present a new synthesis methodology that facilitates the design automation of maximum bandwidth transimpedance amplifier (TIA) for optical communications under the constraint of a specific bit error rate. Our synthesis methodology is based on newly developed models that characterize the input referred noise and bandwidth. Our technique provides the optimal parameters of the transimpedance amplifier for maximizing the bandwidth. These optimal parameters are mapped to equivalent circuit parameters to achieve the optimal sizing of the TIA. Our methodology is characterized by its very fast design convergence as well as better results compared to conventional design techniques. We applied our synthesis methodology in designing a TIA for optical interconnect systems using the 0.25?m and 0.18?m CMOS technologies.

Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics

In this paper, we describe a new via-configurable routing architecture which shows a much better throughput and performance than the previous structures. We demonstrate how to construct a single-via-mask fabric to reduce the mask cost further, and we analyze the penalties which it incurs. To solve the routability problem commonly existing in fabric-based designs, an efficient white-space allocation and an incremental cell movement scheme are suggested, which help to provide a fast design convergence and early prediction of circuit's mappability to a given fabric