Fast Transient Charge Trapping Research Articles

Reliability Instability Assessment with Interfacial Trapping Analysis for the Optimization of Al Composition in AlxGa1−xN/GaN High Electron Mobility Transistors

This study investigates the trapping characteristics present at the interface of AlxGa1−xN/GaN high electron mobility transistors (HEMTs) and explores the influence of the Al composition within the AlxGa1−xN barrier on the device's performance. Using a single pulse ID–VD characterization technique, the reliability instability is evaluated in two different AlxGa1−xN/GaN HEMTs: one with an Al composition of 25% (Al0.25Ga0.75N/GaN) and the other with an Al composition of 45% (Al0.45Ga0.55N/GaN). The results unveil a notable higher drain current degradation (ΔID) in Al0.45Ga0.55N/GaN devices, attributed to fast transient charge trapping. Conversely, the Al0.25Ga0.75N/GaN device exhibits a substantial 35% reduction in interface trap density (Dit) and an impressive 73% decrease in border trap density (Nbt), solidifying its reduced trapping behavior compared to Al0.45Ga0.55N/GaN due to the rougher barrier/channel interface of the latter device. Furthermore, load‐pull measurements unveiled a noteworthy 60% power‐added efficiency for the Al0.25Ga0.75N/GaN device, presenting a 10% performance improvement over the Al0.45Ga0.55N/GaN device. These findings provide valuable insights into the trapping phenomena within AlGaN/GaN HEMTs, paving the way for enhanced device design and performance optimization.

Oxygen vacancy related hole fast trapping in high mobility cubic-Ge/ZrO2 interface

Ge has the potential to replace Si as the future field-effect transistors channel material due to its superior hole mobility, and cubic zirconia with high dielectric constant and small lattice mismatch can be selected as its oxide layer. At present, the mechanism of charge trapping caused by defects in the Ge oxide layer interface and bulk of such device has not been accurately analyzed. In our work, we have constructed the cubic Ge/ZrO2 interface, and studied the electronic structure and hole trapping characteristics of the interface structure by first-principles hybrid-functional calculations with Marcus theory. According to research oxygen vacancies with the different distances (abbr. d O-int) away from the Ge substrate, we confirm that the oxygen vacancy can act as a fast trap center to capture the hole of the valence band maximum (VBM) from Ge, resulting in the ultrafast or fast transient charge trapping in the high-k gate dielectric. We found that, when a given range of applied electric field, the hole trap is ultrafast with capture time of 10−6–10−5 when d O-int is within the range of 2–7 , and there is a 2–3 order of magnitude increases in capture time as d O-int exceeds 7 with the maximum capture cross section reducing substantially. Here, our work provides a clear and reasonable description of the distance-dependent hole trapping process at the Ge/high-k dielectrics metal-oxide-semiconductor (MOS) devices and provides significant support for solving the reliability problem of microelectronic devices.

Efficient Suppression of Defects and Charge Trapping in High Density In-Sn-Zn-O Thin Film Transistor Prepared using Microwave-Assisted Sputter.

Amorphous oxide semiconductor-based thin film transistors (TFTs) have been considered as excellent switching elements for driving active-matrix organic light-emitting diodes (AMOLED) owing to their high mobility and process compatibility. However, oxide semiconductors have inherent defects, causing fast transient charge trapping and device instability. For the next-generation displays such as flexible, wearable, or transparent displays, an active semiconductor layer with ultrahigh mobility and high reliability at low deposition temperature is required. Therefore, we introduced high density plasma microwave-assisted (MWA) sputtering method as a promising deposition tool for the formation of high density and high-performance oxide semiconductor films. In this paper, we present the effect of the MWA sputtering method on the defects and fast charge trapping in In-Sn-Zn-O (ITZO) TFTs using various AC device characterization methodologies including fast I-V, pulsed I-V, transient current, low frequency noise, and discharge current analysis. Using these methods, we were able to analyze the charge trapping mechanism and intrinsic electrical characteristics, and extract the subgap density of the states of oxide TFTs quantitatively. In comparison to conventional sputtered ITZO, high density plasma MWA-sputtered ITZO exhibits outstanding electrical performance, negligible charge trapping characteristics and low subgap density of states. High-density plasma MWA sputtering method has high deposition rate even at low working pressure and control the ion bombardment energy, resulting in forming low defect generation in ITZO and presenting high performance ITZO TFT. We expect the proposed high density plasma sputtering method to be applicable to a wide range of oxide semiconductor device applications.

Fast and slow transient charging of Oxide Semiconductor Transistors

The comprehension of the governing mechanism which affects device instability is one of the most important requirements for the formation of reliable oxide-thin film transistors (TFTs). However, a quantitative analysis of the dominant mechanism of device instability, which stems from charge trapping induced by defects at the oxide semiconductor interface as well as in its bulk, has not yet been systematically performed. In this study, we examined subgap states, charge-transport dynamics, and various trap characteristics of oxide TFTs by multi-frequency C–V, pulse I–V, and transient current methods to achieve a comprehensive understanding of carrier transport and charge trapping mechanisms. We found that the charge trapping behavior of the tested amorphous InHfZnO (a-IHZO) TFT follows a multi-trapping mechanism, such as temperature-independent fast transient charge trapping by resonant drift of the injected electron and temperature-dependent slow transient charge trapping by charge transport from occupied to unoccupied traps. Understanding fast charging and slow charging described in this study can help to understand the root cause of device instability of oxide TFTs and ultimately improve stability and reliability characteristics.

Determination of intrinsic mobility of a bilayer oxide thin-film transistor by pulsed I–V method

Amorphous oxide semiconductor thin-film transistors (TFT) have been considered as outstanding switch devices owing to their high mobility. However, because of their amorphous channel material with a certain level of density of states, a fast transient charging effect in an oxide TFT occurs, leading to an underestimation of the mobility value. In this paper, the effects of the fast charging of high-performance bilayer oxide semiconductor TFTs on mobility are examined in order to determine an accurate mobility extraction method. In addition, an approach based on a pulse I D –V G measurement method is proposed to determine the intrinsic mobility value. Even with the short pulse I D –V G measurement, a certain level of fast transient charge trapping cannot be avoided as long as the charge-trap start time is shorter than the pulse rising time. Using a pulse-amplitude-dependent threshold voltage characterization method, we estimated a correction factor for the apparent mobility, thus allowing us to determine the intrinsic mobility.

The Pulsed Id-Vgmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-κ dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trapinduced threshold voltage shift (△VSUBt/SUB), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-κ gate dielectric devices.

Characterization of Transient Gate Oxide Trapping in SiC MOSFETs Using Fast $I$–$V$ Techniques

Threshold voltage and drain current instabilities in state-of-the-art 4H-SiC MOSFETs with thermal as-grown SiO2 and NO-annealed gate oxides have been studied using fast I-V measurements. These measurements reveal the full extent of the instability underestimated by dc measurements. Furthermore, fast measurements allow the separation of negative and positive bias stress effects. Postoxidation annealing in NO was found to passivate the oxide traps and dramatically reduce the instability. A physical model involving fast transient charge trapping and detrapping at and near the SiC/SiO2 interface is proposed.

The influence of HfO 2 film thickness on the interface state density and low field mobility of n channel HfO 2/TiN gate MOSFETs

The influence of HfO 2 thickness (1.6 to 3nm) on interface state density and low field mobility in HfO 2/TiN gate n channel MOSFETs have been studied by analyzing experimental data from charge pumping, split CV, DC I d- V g, pulsed I d- V g and Y-function methods. It is found that there is no HfO 2 thickness dependence on the interface state density, whereas there is continuous electron mobility degradation with HfO 2 thickness. The devices exhibited no detectable fast transient charge trapping, allowing the relative contributions of phonon and Coulomb scattering to be examined over temperature. The dependence of the low field mobility on temperature from 50 K to 400 K indicates HfO 2 remote phonon scattering as the dominant cause of the mobility degradation.

CMOS Device and Circuit Degradations Subject to $\hbox{HfO}_{2}$ Gate Breakdown and Transient Charge-Trapping Effect

The gate leakage current of HfO2 MOSFETs exhibits the power law characteristics after soft breakdown (BD) and the linear behavior after hard BD. Fast transient charge-trapping effect (FTCTE) shifts the inverter transfer characteristics but does not affect the high and low output voltages. The ring oscillator remains functional after gate BD. The BD position near the drain end of the n-channel transistor increases the noise figure (NF) significantly, whereas FTCTE has minor impact on the NF of the folded cascode low-noise amplifier