Fast Parallel Multipliers Research Articles

Fault–tolerant architecture for serial–parallel multipliers

An efficient fault–tolerant architecture for use in serial–parallel multipliers is proposed. This architecture uses a time redundancy method together with the technique of a fast serial–parallel multiplier to achieve both error detection and error location with small time and hardware overheads. The design is most suitable for use in VLSI circuits and digital signal processing applications where serial data is available.

Implementing of fast graphic functions in FPGA programmable logic

The paper deals with a possibility of using the FPGA architecture for implementing the fast simple 2D graphics with minimum of logic resources. The basis of that work was published in (Kasik, 2008) and since the time it has been extended with polar to rectangular coordinates computing for graphic 2D objects. The presented logic design shapes the graphics adapter, which is generally built of combinatorial logic without video-memory. The graphics adapter is designed for programmable FPGA devices and their specific logic resources, especially fast parallel multipliers.

Design and analysis of a compact fast parallel multiplier for high speed DSP applications using novel partial product generator and 4 : 2 compressor

Parallel multiplier is one of the most important building blocks in all the DSP processors, which needs faster computations. To reduce the total transistor count in a multiplier we have proposed two new approaches. The first approach is using a 26 transistor booth encoder and a 8-transistor/partial-product booth selector to generate partial products. The second approach proposes a new circuit for 4 : 2 compressors. The booth encoder and booth selector reported here are the smallest in transistor count, but comparable to the best delay with less power consumption. This paper describes a comparison of a compact 16 × 16 parallel multiplier using the new circuit components. This shows a transistor count advantage of 27% and 52% in partial product generation and partial product accumulation, respectively.

Architectural optimization of a digital optical multiplier

A computational model of estimation of the time complexity of logical circuits constructed from elements of an optical element base is investigated. A fast parallel multiplier is constructed.

Toward architecture-based test-vector generation for timing verification of fast parallel multipliers

Fast parallel multipliers that contain logarithmic partial-product reduction trees pose a challenge to simulation-based high-accuracy timing verification, since the reduction tree has many reconvergent signal branches. However, such a multiplier architecture also offers a clue as how to attack the test-vector generation problem. The timing-critical paths are intimately associated with long carry propagation. We introduce a multiplier test-vector generation method that has the ability to exercise such long carry propagation paths. Through extensive circuit simulation and static timing analysis, we evaluate the quality of the test vectors that result from the new method. Especially for fast multipliers with a pronounced carry propagation, the timing-critical vectors manage to stimulate a path, which has a delay that comes close to the true worst case delay. We investigate the complexity and run-time for the test-vector generation, and derive timing-critical vectors up to a factor word length of 54 bits.

실시간 멀티미디어 시스템을 위한 새로운 고속 병렬곱셈기

본 논문에서는 고속 병렬 곱셈기에서 속도향상을 위해 부분 곱을 가산하는 과정에 구성되는 CSA(Carry Select Adder) 트리에 새로운 압축기를 적용한 새로운 첫 번째 부분 곱가산(First Partial Product Addition : FPA)를 제안하여 기존의 전가산기를 이용한 병렬가산기보다 부분곱을 계산하는 속도를 약 20% 개선할 수 있게 했다. 새로운 회로는 새로운 FPA 구조를 사용하여 최종 합 CLA 비트를 N/2로 줄인다. 2.5v 0.25um CMOS 기술을 이용하여 제작된 16<TEX>${\times}$</TEX>16 곱셈기는 5.14nS의 곱셈 고속을 얻었다. 이 곱셈기의 구조는 파이프라인 설계에 용이하며 고성능을 낸다. In this paper, we proposed a new First Partial product Addition (FPA) architecture with new compressor (or parallel counter) to CSA tree built in the process of adding partial product for improving speed in the fast parallel multiplier to improve the speed of calculating partial product by about 20% compared with existing parallel counter using full Adder. The new circuit reduces the CLA bit finding final sum by N/2 using the novel FPA architecture. A 5.14nS of multiplication speed of the <TEX>$16{\times}16$</TEX> multiplier is obtained using <TEX>$0.25\mu\textrm{m}$</TEX> CMOS technology. The architecture of the multiplier is easily opted for pipeline design and demonstrates high speed performance.

On the inherent space complexity of fast parallel multipliers for GF(2/sup m/)

A lower bound to the number of AND gates used in parallel multipliers for GF(2/sup m/), under the condition that time complexity be minimum, is determined. In particular, the exact minimum number of AND gates for primitive normal bases and optimal normal bases of Type II multipliers is evaluated. This result indirectly suggests that space complexity is essentially a quadratic function of m when time complexity is kept minimum.

Efficient synthesiser for generation of fast parallel multipliers

An automatic generator is developed which can synthesise fixed-point multipliers of any bit accuracy with a speed performance comparable to other recently proposed full-custom results. This synthesiser performs global optimisation for the interconnection of compression elements to minimise the delay in the partial product summation tree (PPST). Also, the final adder following the PPST is carefully synthesised to reduce the cost without sacrificing the speed performance. Unlike the full-custom design method, our synthesiser is adaptable to any technology change. A significant improvement is achieved compared to the Synopsys synthesis results.

Parallel multiplication using fast sorting networks

A recent paper describes the use of Svoboda's binary counter in the construction of fast parallel multipliers. The resulting approach was shown to be faster than the conventional Dadda multiplier when the wordlength N was small. Unfortunately, the growth in the number of gates of that method was O(N/sup 3/) and the speed was O(N). In this paper, Batcher's bitonic sorting network and other efficient networks replace the Svoboda counter. The asymptotic growth rate in gates of these new methods is O(N/sup 2/ log/sup 2/ N), and the speed is O(log/sup 2/ N).

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture

A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RE number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RE number into the corresponding NE number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54/spl times/54-bit multiplier is designed with this architecture. It is fabricated by 0.5 /spl mu/m CMOS with triple level metal technology. The active area size is 3.0/spl times/3.08 mm/sup 2/ and the number of transistors is 78,800. This is the smallest number for all 54/spl times/54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54/spl times/54-bit multipliers with 0.5-/spl mu/m CMOS.

A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach

This paper presents a method and an algorithm for generation of a parallel multiplier, which is optimized for speed. This method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known. Most importantly, it is easy to incorporate this method in silicon compilation or logic synthesis tools. The parallel multiplier produced by the proposed method outperforms other schemes used for comparison in our experiment. It uses the minimal number of cells in the partial product reduction tree. These findings are tested on design examples simulated in 1 /spl mu/ CMOS ASIC technology.

Performance Study of The Modified Fast Serial Parallel Multiplier with RECO Technique.(Dept.E)

This p aper studies the sp eed and hardware performance of the modified fast serial-parallel (MFSP) multip lier with concurrent error detection (CED) by REcomputing with Circularly shifted Operands (RECO) technique. The MFSP multiplier has been proposed primarily to increase the sp eed of the fast serial parallel (FSP)multiplier by using fast parallel adder instead of the parallel ripple carry adder. This multiplier can be used for VLSI when the chip size is limited for high speed applications. By using RECO technique for CED applied to the MFSP multiplier, the copmromise between suitable error coverage, small error latency , suitable multiplication speed improvement and low hardware over-head as possible is exp ected. This multiplier is suitable for VLSI and can be used efficiently In digital signal processing (DSP) applications. Speed and hardware comparisons to the carry save-add shift (CSAS) multiplier with and without RECO technique are also made.

A fast 16 bit NMOS parallel multiplier

An architecture for a fast parallel array multiplier is described. Using a 3 /spl mu/m E/D NMOS process, a 16/spl times/16 bit trial circuit has been designed. A multiplication time of 120 ns has been achieved with a power dissipation of 200 mW and a silicon area of 5 mm/SUP 2/. This architecture concept greatly reduces the logical depth of the array by rearranging internal delays. It is applicable in principle to any MOS, CMOS, GaAs, or bipolar technology.

High-speed low-power silicon MESFET parallel multipliers

The design of fast low-power silicon LSI MESFET parallel multipliers is studied. The architecture of the multipliers and the designs of the functional blocks are discussed. The overall performance of the multipliers is estimated from the simulated performances of the functional blocks and from system simulations with a logic simulator. The actual performance of 8/spl times/8 and 10/spl times/10 bit TTL-compatible multipliers, fabricated with a 2.5 /spl mu/m silicon MESFET technology (1.5-2 /spl mu/m effective dimensions) is compared to the simulations.

Parallel Multiplicative Algorithms for Some Elementary Functions

This correspondence presents generalized higher radix algorithms for some elementary functions which use fast parallel m-bit multipliers where radix = 2m. These algorithms are extensions of those iterative schemes which are based on multiplications by (1 + 2-i) and the use of prestored values of ln (1 + 2-i) and tan-1(2-i). The particular functions under consideration are y/x, y/x1/2, y. exp (x), y + 1n (x), sin (x) and cos (x) [and hence tan (x)]. The extended algorithms rely on multiplication by (1 + d i r-k) where d i , 0 ≤ d i r, is an m-bit integer. Using a simple selection procedure for di, simulations show that p(radix r) digits of a function may be generated, on the average, in less than p + 1 iterations.

Suggestion for an i.c. fast parallel multiplier

A general method for handling partial products in a parallel multiplier is proposed. It leads to a network of AND gates and full adders, availables as i.c.s which can have an operation time of less than 10 ns per bit of the result.