Fast-locking Phase-locked Loop Research Articles

A 2–3 GHz Fast-Locking PLL Using Phase Error Compensator

A fast-locking phase-locked loop (PLL) using the proposed phase error compensator (PEC) is presented. The PEC compensates the accumulated phase error during the frequency acquisition process to enhance the settling time of this PLL. This PLL is fabricated in a 40-nm CMOS process. The output frequency of the PLL ranges from 2 to 3 GHz. When this PLL is switched from 2 GHz to 3 GHz, the measured settling time using the PEC is 0.6us which is around 30 reference clock cycles. The power consumption of the PLL is 4.6mW at 3 GHz for a supply of 1V. The integral root-mean-square jitter over 1 kHz to 100 MHz is 2.99ps.

A 33 MHz Fast-Locking PLL with Programmable VCO and Automatic Band Selection for Clock Generator Application

This paper presents a prototype of an auto-ranging phase-locked loop (PLL) with low jitter noise over a wide operating frequency range using the multiband programmable voltage-controlled oscillator (VCO) gain stage with automatic band selection. We successfully reduce the VCO gain (Kvco) and retain the desired frequency band. The proposed PLL comprises a prescaler, phase frequency detector (PFD), charge pump (CP), programmable VCO and automatic band selection circuit. The PLL prototype with all subblocks was implemented using the TSMC 0.18 μm 1P6M process. Contrary to conventional PLL architectures, the proposed architecture incorporates a real-time check and automatic band selection circuit in the secondary loop. A high-performance dual-loop PLL wide tuning range was realized using an ASIC digital control circuit. A suitable way to maintain the Kvco low is to use multiple discrete frequency bands to accommodate the required frequency range. To maintain a low Kvco and fast locking, the automatic frequency band selection circuit also has two indigenous, most probable voltage levels. The proposed architecture provides the flexibility of not only band hopping but also band twisting to obtain an optimized Kvco for the desired output range, with the minimum jitter and spurs. The proposed programmable VCO was designed using a voltage-to-current-converter circuit and current DAC followed by a four-stage differential ring oscillator with a cross-coupled pair. The VCO frequency output range is 150–400 MHz, while the input frequency is 25 MHz. A sequential phase detection loop with a negligible dead zone was designed to adjust fine phase errors between the reference and feedback clocks. All circuit blocks of the proposed PLL were simulated using the EDA tool HSPICE and layout generation by Laker. The simulation and measured results of the proposed PLL show high linearity, with a dead zone of less than 10 pV. The differential VCO was used to improve the linearity and phase noise of the PLL. The chip measured results show rms jitter of 19.10 ps. The PLL prototype also has an additional safety feature of a power down mode. The automatic band selection PLL has good immunity for possible frequency drifting due to temperature, process and supply voltage variations. The proposed PLL is designed for −40 to +85 °C, a wide temperature range.

Stability and nonlinear controller design of Fast-Lock Phase-Locked Loop in 0.18-µm CMOS

Stability and nonlinear controller design of Fast-Lock Phase-Locked Loop in 0.18-µm CMOS

Frequency presetting and phase error detection technique for fast-locking phase-locked loop

A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V.

A fast-locking PLL with all-digital locked-aid circuit

In this article, a fast-locking phase-locked loop (PLL) with an all-digital locked-aid circuit is proposed and analysed. The proposed topology is based on two tuning loops: frequency and phase detections. A frequency detection loop is used to accelerate frequency locking time, and a phase detection loop is used to adjust fine phase errors between the reference and feedback clocks. The proposed PLL circuit is designed based on the 0.35 µm CMOS process with a 3.3 V supply voltage. Experimental results show that the locking time of the proposed PLL achieves a 87.5% reduction from that of a PLL without the locked-aid circuit.

Random Pulsewidth Matching Frequency Synthesizer With Sub-Sampling Charge Pump

This paper presents a fast locking phase-locked loop (FLPLL) system with reference-spur reduction techniques exploiting random pulsewidth matching and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. The loop bandwidth of the system can be adjusted by the control voltage so as to reduce the locking time. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5 GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90-nm CMOS process. The proposed circuit can achieve a phase noise of -114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below -74 dBc.

A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-μm 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are 400 × 450 μm2 and 6 mW, respectively.

A phase-locked loop of the resistance and capacitance scaling scheme with multiple charge pumps

In this paper, a novel phase-locked loop (PLL) architecture with multiple charge pumps, which is used to design a fast-locking PLL and a low-phase-noise PLL, is proposed. The effective capacitance and resistance of the loop filter in terms of voltage is scaled up/down according to the locking status by controlling the magnitude and direction of the charge pump current. Two PLLs, one with a fast-locking characteristic and the other with a low-phase-noise characteristic, are designed and fabricated in a 0.35-μm CMOS process based on the proposed architecture. The fast-locking PLL has a locking time of less than 6 μs and a phase noise of ?90.45 dBc/Hz at 1 MHz offset. The low-phase-noise PLL has a locking time of 25 μs, a phase noise of ?105.37 dBc/Hz at 1 MHz offset, and a reference spur of ?50 dBc. Both PLLs have an 851.2 MHz output frequency.

A fast lock frequency synthesizer using an improved adaptive frequency calibration

An improved adaptive frequency calibration (AFC) has been employed to implement a fast lock phase-locked loop based frequency synthesizer in a 0.18 μm CMOS process. The AFC can work in two modes: the frequency calibration mode and the store/load mode. In the frequency calibration mode, a novel frequency-detector is used to reduce the frequency calibration time to 16 μs typically. In the store/load mode, the AFC makes the voltage-controlled oscillator (VCO) return to the calibrated frequency in about 1 μs by loading the calibration result stored after the frequency calibration. The experimental results show that the VCO tuning frequency range is about 620–920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is −82 dBc/Hz. The lock time is about 20 μs in frequency calibration mode and about 5 μs in store/load mode. The synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.

Self-tracking charge pump for fast-locking PLL

Presented is a self-tracking charge pump (ST-CP) that can deliver a non-constant current over the output voltage range for a fast-locking phase-locked loop (PLL). It features a simple self-bias self-tracking architecture that can reduce, simultaneously, the PLL locking time and the current mismatch in charge and discharge phases. Experimentally verified in a 0.18 ?m CMOS process, the proposed ST-CP achieves 72% reduction of PLL locking time compared with the conventional one. The core occupies 30 × 60 ?m and draws 10 ?A at 1.8 V.

Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting

Design of a fast-locking phase-locked loop (PLL) is one of the major challenges in today's wireless communications. A recently reported digitally controlled oscillator (DCO)-based all-digital PLL (ADPLL) can achieve an ultrashort settling time of 10 µs. This study describes a new DCO tuning word (OTW) presetting technique for the ADPLL to further reduce its settling time. Estimating the required OTW is the most crucial issue for presetting. Two methods are proposed here to estimate the required OTW. One method is using a foreground calibration block to eliminate the effect of DCO gain (KDCO) estimation error (ɛK) and then directly calculating the required OTW for the process/voltage/temperature calibration (PVT-calibration) mode of the ADPLL. The other method is using a new counter-based mode switching controller (CB-MSC) to estimate the required OTW for the acquisition mode and tracking mode. This method is based on the ADPLL's inherent characteristic of frequency toggling and is independent of loop parameters. Furthermore, our proposed presetting technique can be used with the dynamic loop bandwidth control technique together. The ADPLL with the proposed OTW estimating and presetting block is designed using very-high-speed integrated circuit hardware description language and simulated in ModelSim environment. Simulation results demonstrate that a minimum settling time of 2.9 µs is achieved and the improvement is about 40–50% on average compared with the ADPLL without our techniques.

A novel flash fast-locking digital phase-locked loop: design and simulations

A flash digital phase-locked loop (DPLL) is designed using 0.18 μm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz-2 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm similar to the algorithm employed in flash A/D converters, and (ii) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder which drives a multiple charge pump (CP)/lowpass filter (LPF) combination. Design considerations of the flash DPLL circuit components as well as implementation using Cadence design tools are presented. Spectre simulations were also performed and demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL. By increasing the number of frequency comparators, the lock time is expected to be always less than 100 ns in the above-mentioned frequency range.

Low-noise and fast-locking phase-locked loop

In this article, a phase-locked loop (PLL) is introduced. The proposed PLL, denoted by NPLL, is similar to the standard PLL except that it incorporates a nonlinear element and a low-pass filter in its loop. It is shown that by appropriate choices of these two components, the NPLL outperforms the standard PLL in three respects: (i) it has a large acquisition range, i.e., it can achieve locking in situations where the standard PLL cannot; (ii) it achieves locking fast; and (iii) it has low noise in its output phase. The role of the nonlinear element in enhancing the locking capabilities and noise characteristics of the NPLL is carefully examined. Many tests, results of three of which are reported in this article, show the superior performance of the NPLL.

A low-noise fast-lock phase-locked loop with adaptive bandwidth control

This paper presents a salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. Based on an analog recursive bandwidth control algorithm, the PLL achieves the phase and frequency lock in less than 30 clock cycles without pre-training, and maintains the cycle-to-cycle jitter within 20 ps (peak-to-peak) in the tracking mode. A feed forward-type duty-cycle corrector is designed to keep the 50% duty cycle ratio over all operating frequency range.