A phase-locked loop of the resistance and capacitance scaling scheme with multiple charge pumps

Abstract

In this paper, a novel phase-locked loop (PLL) architecture with multiple charge pumps, which is used to design a fast-locking PLL and a low-phase-noise PLL, is proposed. The effective capacitance and resistance of the loop filter in terms of voltage is scaled up/down according to the locking status by controlling the magnitude and direction of the charge pump current. Two PLLs, one with a fast-locking characteristic and the other with a low-phase-noise characteristic, are designed and fabricated in a 0.35-μm CMOS process based on the proposed architecture. The fast-locking PLL has a locking time of less than 6 μs and a phase noise of ?90.45 dBc/Hz at 1 MHz offset. The low-phase-noise PLL has a locking time of 25 μs, a phase noise of ?105.37 dBc/Hz at 1 MHz offset, and a reference spur of ?50 dBc. Both PLLs have an 851.2 MHz output frequency.