Fast IP Address Lookup Research Articles

TCAM-Based IP Address Lookup Using Longest Suffix Split

Ternary content addressable memory (TCAM) plays an important role in modern routers due to its capability of performing fast IP address lookup. However, it is expensive, space limited, and a major source of power consumption in a router. In addition, because TCAM only reports the first matching entry, updating TCAM entries would be slow due to necessary entry reordering. In this paper, we present a trie-based algorithm, longest suffix split, to reduce the number of TCAM entries for IP address lookup. The algorithm divides route prefixes into two portions, subprefix and suffix. The route prefixes with the same subprefix and similar suffix portions can then be represented by one TCAM entry and one SRAM entry. Each SRAM entry stores one of two succinct data structures, depending on the threshold number of similar suffixes. The experimental results show that our scheme can reduce 50% to 95% TCAM entries for the original routing tables. Our scheme also supports incremental updates. Because the drawbacks of TCAM are related to the number of required entries, our scheme significantly improves the feasibility of TCAM-based IP address lookup. While network virtualization may store multiple forwarding information bases in a router, the number of supported virtual routers can be increased by our scheme.

An IPv6 Address Lookup Algorithm Based on Multi-bit Trie and Prefix Hierarchy

The size of IPv6 routing table growing rapidly, fast ip address lookup is becoming critical in high-speed packet forwarding. However, most of the IPv4 routing algorithm is not suitable for IPv6, *measure the characteristics of IPv6 and the routing table address prefix hierarchical distribution. In this paper, a new fast IP address lookup algorithm based on multi-bit trie and prefix hierarchy is proposed. The proposed algorithm has good scalability and effectively reduces the depth of the search tree.

Efficient Searching with a TCAM-based Parallel Architecture

Ternary Content-Addressable Memory (TCAM) is a popular hardware device for fast IP address lookup. High link transmission speed of Internet backbone demands more powerful IP address lookup engine. Restricted by the memory access speed, the lookup engine for next-generation routers demands exploiting parallelism among multiple TCAM chips. How to design an efficient engine with high IP lookup speed and less update time while keeping low power consumption is a great challenge in building the next-generation routers. At present, no parallel schemes can make full use of TCAM chips’ capability. In this paper, we propose a fast lookup, efficient update and power-saving scheme which can basically make full use of TCAM chips’ capability. With N parallel TCAM chips, our proposed scheme can achieve a worst-case speedup factor of (N-1)*90% in cache-update state, and a worst-case speedup factor of N*90% in normal work state. Compared with previous works, our scheme can apparently improve IP lookup performance and update efficiency while keeps low power consumption.

Tree-Combined Trie: A Compressed Data Structure for Fast IP Address Lookup

For meeting the requirements of the high-speed Internet and satisfying the Internet users, building fast routers with high-speed IP address lookup engine is inevitable. Regarding the unpredictable variations occurred in the forwarding information during the time and space, the IP lookup algorithm should be able to customize itself with temporal and spatial conditions. This paper proposes a new dynamic data structure for fast IP address lookup. This novel data structure is a dynamic mixture of trees and tries which is called Tree-Combined Trie or simply TC-Trie. Binary sorted trees are more advantageous than tries for representing a sparse population while multibit tries have better performance than trees when a population is dense. TC-trie combines advantages of binary sorted trees and multibit tries to achieve maximum compression of the forwarding information. Dynamic reconfiguration of TC-trie, made it capable of customizing itself along the time and scaling to support more prefixes or longer IPv6 prefixes. TC-trie provides a smooth transition from current large IPv4 databases to the large IPv6 databases of the future Internet.

스마트 분배기를 이용한 효율적인 병렬 IP 주소 검색 구조

인터넷에서 초고속 서비스의 제공을 위해서, 라우터는 신속하게 IP 주소 검색을 수행해야 한다. 본 논문에서는 4 단계의 파이프라인으로 구성된 하이브리드 방식의 병렬 IP 주소 검색 구조를 제안한다. 단계 2의 다중 SRAM과 단계 3의 분할 TCAM을 사용하여 저렴한 비용으로 병렬화를 이루고, 파이프라이닝을 통해 처리율을 향상시켰다. 단계 1에서 스마트 분배기는 선행된 IP 주소와 동일한 주소를 다음 단계로 진입시키지 않고 선행의 검색 결과를 그대로 활용하게 한다. 이에 따라, 캐싱 효과에 의해 검색 처리율을 더욱 향상시키고, 단계 3인 TCAM bank로의 접근 충돌도 완화시킬 수 있다. 마지막 단계의 재정렬 버퍼는 처리된 IP 주소 순서를 입력 순서에 맞도록 재조정하는 기능을 수행한다. 또한, 실제 사용되는 라우팅 테이블과 Zipf 법칙에 따라 생성된 트래픽 분포를 사용하여, 병렬 파이프라인 IP 검색 구조의 성능을 기존의 하이브리드 구조와 비교하여 평가한다. Routers should perform fast IP address lookup for Internet to provide high-speed service. In this paper, we present a hybrid parallel IP address lookup structure composed of four-stage pipeline. It achieves parallelism at low cost by using multiple SRAMs in stage 2 and partitioned TCAMs in stage 3, and improves the performance through pipelining. The smart distributor in stage 1 does not transfer any IP address identical to previous one toward the next stage, but only uses the result of the previous lookup. So it improves throughput of lookup by caching effects, and decreases the access conflict to TCAM bank in stage 3 as well. In the last stage, the reorder buffer rearranges the completed IP addresses according to the input order. We evaluate the performance of our parallel pipelined IP lookup structure comparing with previous hybrid structure, using the real routing table and traffic distributions generated by Zipf's law.

EXPERIMENTAL EVALUATIONS OF ALGORITHMS FOR IP TABLE MINIMIZATION

Reducing the size of IP routing tables is one of the most compelling scaling problems affecting the Internet because of massive growth of routing table entries, increased traffic, and the migration to 128 bit IPv6 addresses. Various algorithms for IP table minimization have been proposed in the literature both for a single and for multiple tables, also with the possibility of performing address reassignments. In this paper we first introduce two new compression heuristics, the BFM and its evolution called BFM-Cluster, that exploit address reassignments for the minimization of multiple routing tables, and then we experimentally evaluate their performances together with the already existing techniques. Since a main problem posed by the growth of the routing tables sizes is the consequent general increase of the table lookup time during the routing of the IP packets, the aim is twofold: to measure and compare the compression ratios of the different algorithms, and to estimate the effects of the compression on the lookup times by measuring the induced improvement on the time of the main algorithms and data structures for the fast IP address lookup from the original tables to the compressed ones. Our point is that the existing techniques are efficient in different situations, with BFM-Cluster heuristic outperforming all other ones.

A Fast IP Address Lookup Algorithm Based on Search Space Reduction

This letter proposes a fast IP address lookup algorithm based on search space reduction. Prefixes are classified into three types according to the nesting relationship and a large forwarding table is partitioned into multiple small trees. As a result, the search space is reduced. The results of analyses and experiments show that the proposed method offers higher lookup and updating speeds along with reduced memory requirements.

On Designing Fast Nonuniformly Distributed IP Address Lookup Hashing Algorithms

Computer networks have continued to make substantial advances in the past couple of decades through better technologies and methodologies employed. As the usage of the networks continues to increase exponentially, high throughput of the networks has to be maintained with various performance-efficient network algorithms. IP address lookup is one of the processes, the performance of which dearly affects the overall network performance. Hashing has been widely used for fast IP address lookup due to its simplicity, but mostly assuming on hashing from an address set with uniformly distributed key values. Performance from these known hashing techniques is far from optimal due to the high nonuniformity in actual IP address distribution. In this paper, we propose a preprocessing method for the IP address databases to extract certain regularity to allow for design of more efficient hashing algorithms based on XOR operations. Simulation results show an improvement in performance ranging from 35% to 72% on randomly generated addresses and several sample IP address databases. The paper also shows that the proposed algorithms deliver comparable performance to other well-known hashing algorithms such as the CRC and RS hashing while requiring much less hardware to implement and a much shorter time to perform.

Efficient location of free spaces in TCAM to improve router performance

A ternary content-addressable memory (TCAM) is a popular hardware device for performing fast IP-address lookup. Because keeping all entries sorted in TCAM, we need move the entries for inserting a new entry. In this paper, we have presented a scheme for minimizing route update overheads in TCAM-based forwarding engines. Our optimizations are based on the hierarchy of prefixes in the routing table. The number of memory movement per update depends on the sequence of the new-inserted prefixes, instead of the initial prefixes in routing table. For the real route update traces, the average number of movements is less than 0.01. Further, when compared to an existing optimization algorithm, in the average case, our algorithm shows a 90% reduction in movement overheads. Copyright © 2005 John Wiley & Sons, Ltd.

A framework for computation-memory algorithmic optimization for signal processing

The heterogeneity of today's computing environment means computation-intensive signal processing algorithms must be optimized for performance in a machine dependent fashion. In this paper, we present a dynamic memory model and associated optimization framework that finds a machine-dependent, near-optimal implementation of an algorithm by exploiting the computation-memory tradeoff. By optimal, we mean an implementation that has the fastest running time given the specification of the machine memory hierarchy. We discuss two instantiations of the framework: fast IP address lookup, and fast nonuniform scalar quantizer and unstructured vector quantizer encoding. Experiments show that both instantiations outperform techniques that ignore this computation-memory tradeoff.

Enabling incremental updates to LC-trie for efficient management of IP forwarding tables

Level-compressed trie (LC-trie) is an efficient data structure for fast IP address lookup. However, the data structure needs to be rebuilt every time the table is updated. Consequently, the LC-trie algorithm is not suitable for application in a dynamic environment where frequent updates to the forwarding table are necessary. It is shown that with appropriate modifications to the data structure, incremental updates can be done efficiently.

High-performance IP routing table lookup

Nowadays, the commonly used table lookup scheme for IP routing is based on the so-called classless interdomain routing (CIDR). With CIDR, routers must find out the best matching prefix (BMP) for IP packets forwarding, which complicates the IP lookup. Currently, this process is mainly done in software and several schemes have been proposed for hardware implementation. Since the IP lookup performance is a major design issue for the new generation routers, in this article we propose a fast IP address lookup scheme, which significantly reduces the forwarding table to fit into SRAM with very low cost. It can also be implemented in hardware using the pipeline technique. By using our proposed method, the required memory space can be 90–170 Kb less than the previous scheme and three memory accesses for a lookup in the worst case. When implemented in hardware pipeline architecture, our mechanism can achieve one routing lookup per memory access.

A fast IP routing lookup scheme

A major issue in router design for the next generation Internet is the fast IP address lookup mechanism. The existing scheme by Huang et al. (see Proc. IEEE INFOCOM'99, New York, NY, 1999) performs the IP address lookup in hardware in which the forwarding table can be compressed to fit into a reasonable-size SRAM, and a lookup can be accomplished in three memory accesses. We claim that with a little extra memory, it is able to further reduce the lookup time to two memory accesses.

Survey and taxonomy of IP address lookup algorithms

Due to the rapid growth of traffic in the Internet, backbone links of several gigabits per second are commonly deployed. To handle gigabit-per-second traffic rates, the backbone routers must be able to forward millions of packets per second on each of their ports. Fast IP address lookup in the routers, which uses the packet's destination address to determine for each packet the next hop, is therefore crucial to achieve the packet forwarding rates required. IP address lookup is difficult because it requires a longest matching prefix search. In the last couple of years, various algorithms for high-performance IP address lookup have been proposed. We present a survey of state-of-the-art IP address lookup algorithms and compare their performance in terms of lookup speed, scalability, and update overhead.