Fast Fourier Transform Stages Research Articles

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

PurposeThis paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle.Design/methodology/approachA new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles.FindingsWith the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations.Originality/valueThis is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers

In this brief, we show how to derive all the optimum multi-path delay commutator (MDC) fast Fourier transform (FFT) hardware architectures in terms of delays and multiplexers and calculate the number of such architectures. The proposed approach is based on analyzing the orders at the FFT stages that lead to optimum number of delays and multiplexers. The results show that there exist a large number of optimum MDC FFTs. This large design space can be explored in the future in order to design efficient MDC architectures that not only optimize the number of delays and multiplexers, but also other figures of merit such as the number of rotators or the input/output data order.

Using Rotator Transformations to Simplify FFT Hardware Architectures

In this paper, we present a new approach to simplify fast Fourier transform (FFT) hardware architectures. The new approach is based on a group of transformations called decimation, reduction, center, move and merge. By combining them it is possible to transform the rotators at different FFT stages, move them to other stages and merge them in such a way that the resulting rotators are simpler than the original ones. The proposed approach can be combined with other existing techniques such coefficient selection and shift-and-add implementation, or rotator allocation in order to obtain low-complexity FFT hardware architectures. To show the effectiveness of the proposed approach, it has been applied to single-path delay feedback (SDF) FFT hardware architectures, where it is observed that the complexity of the rotators is reduced up to 33%.

A 1 Million-Point FFT on a Single FPGA

In this paper, we present the first implementation of a 1 million-point fast Fourier transform (FFT) completely integrated on a single field-programmable gate array (FPGA), without the need for external memory or multiple interconnected FPGAs. The proposed architecture is a pipelined single-delay feedback (SDF) FFT. The architecture includes a specifically designed 1 million-point rotator with high accuracy and a thorough study of the word length at the different FFT stages in order to increase the signal-to-quantization-noise ratio (SQNR) and keep the area low. This also results in low power consumption.

위상 잡음과 직교 불균형이 있는 OFDM 수신 신호의 보상

OFDM(Orthogonal Frequency Division Multiplexing) 시스템에서 직교 불균형 문제는 송수신기의 front-end에서 발생하며, 성상도에 영향을 주게 되어 BER(Bit Error Rate)을 증가시킨다. 또한, 위상 잡음은 송수신시 국부 발진기에서 발생되는 잡음으로 각 부반송파의 직교성을 깨뜨림으로써 시스템 성능을 크게 저하시킨다. 기존 방식인 PNS(Phase Noise Suppression) 알고리즘은 이러한 위상 잡음을 효과적으로 제거하는 방법이지만 직교 불균형 이동시에 적용되면 오히려 성능이 감소된다. 본 논문에서는 OFDM 시스템의 수신기에서 하향 변환 시 발생하는 직교 불균형과 위상 잡음의 영향을 분석하고, 수신기 FFT(Fast Fourier Transform) 후단에서 파일럿 심볼을 사용하여 CPE를 먼저 제거하고 직교 불균형과 위상 잡음의 성분을 검출하여 등화기의 판정 기준으로 사용하여 보상하는 방법을 제시하였다. 또, 다른 기존 방식들은 FFT 후단에서 추정하고 피드백 시키거나 프리엠블과 같은 시퀀스를 사용하는 방식이지만, 본 논문에서는 FFT 후단에서 MMSE 등화기만을 사용하여 제거하므로 기존의 방법보다 복잡도가 줄어든다. 기존의 위상 잡음 제거 방식에 ICI(Inter Carrier Interference) 제거 기능을 추가하고 직교 불균형 성분을 추출하여 MMSE(Minimum Mean Square Error) 과정 중에 적응 forgetting factor를 적용하면 성능 개선과 직교 불균형 성분의 영향이 줄어들며 성능이 개선됨을 보인다. In the OFDM system, IQ imbalance problem happens at the RF front-end of transceiver, which degrades the BER(bit error rate) performance because it affects the constellation in the received signal. Also, phase noise is generated in the local oscillator of transceivers and it destroys the orthogonality between the subcarriers. Conventional PNS algorithm is effective for phase noise suppression, but it is not useful anymore when there are jointly IQ(In-phase and Quadrature) imbalance and phase noise. Therefore, in this paper, we analyze the effect of IQ imbalance and phase noise generated in the down-conversion of the receiver. Then, we estimate and compensate the IQ imbalance and phase noise at the same time. Compared with the conventional method that IQ imbalance after IFFT is estimated and compensated in front of FFT via the feedback, this proposed method extracts and compensates effect of IQ imbalance after FFT stage. In case IQ imbalance and phase noise exist at the same time, we can decrease complexity because it is needless to use elimination of IQ imbalance in time domain and training sequences and preambles. Also, this method shows that it reduces the ICI and CPE component using adaptive forgetting factor of MMSE after FFT.

Low-Power-Adaptive MC-CDMA Receiver Architecture

This paper proposes a novel concept of adjusting the hardware size in a multi-carrier code division multiple access (MC-CDMA) receiver in real time as per the channel parameters such as delay spread, signal-to-noise ratio, transmission rate, and Doppler frequency. The fast Fourier transform (FFT) or inverse FFT (IFFT) size in orthogonal frequency division multiplexing (OFDM)/MC-CDMA transceivers varies from 1024 points to 16 points. Two low-power reconfigurable radix-4 256-point FFT processor architectures are proposed that can also be dynamically configured as 64-point and 16-point as per the channel parameters to prove the concept. By tailoring the clock of the higher FFT stages for longer FFTs and switching to shorter FFTs from longer FFTs, significant power saving is achieved. In addition, two 256 sub-carrier MC-CDMA receiver architectures are proposed which can also be configured for 64 sub-carriers in real time to prove the feasibility of the concept over the whole receiver.

Coefficient memory addressing scheme forhigh performance FFT processors

A novel scheme for coefficient address generation in a fast Fourier transform (FFT) processor is presented. The proposed addressing scheme involves manipulation of the address lines taking into consideration coefficient addresses required at various FFT stages. It is demonstrated that the scheme can be implemented more efficiently with much reduced hardware than approaches published to date, leading to faster, more power and area efficient realisation of FFT processors.

An FFT chart

This letter contains a graph paper summarizing many properties of Fourier transforms and fast Fourier transform (FFT) devices. It shows the interrelationships among data block length, frequency resolution sampling rate, FFT stages, and other related variables. The letter shows the limiting factors in a pipeline FFT and allows its performance to be effectively compared with a random access oriented FFT.