Abstract
In this paper, we present a new approach to simplify fast Fourier transform (FFT) hardware architectures. The new approach is based on a group of transformations called decimation, reduction, center, move and merge. By combining them it is possible to transform the rotators at different FFT stages, move them to other stages and merge them in such a way that the resulting rotators are simpler than the original ones. The proposed approach can be combined with other existing techniques such coefficient selection and shift-and-add implementation, or rotator allocation in order to obtain low-complexity FFT hardware architectures. To show the effectiveness of the proposed approach, it has been applied to single-path delay feedback (SDF) FFT hardware architectures, where it is observed that the complexity of the rotators is reduced up to 33%.
Highlights
I N TODAY’S digital signal processing world, there exists a need for converting signals between time and frequency domains
This paper proposes a new approach to simplify rotators in fast Fourier transform (FFT) hardware architectures based on a set of transformations called decimation, reduction, center, move and merge
In this paper we have presented an approach to simplify FFT hardware architectures that is based on transforming the rotators in the architecture
Summary
I N TODAY’S digital signal processing world, there exists a need for converting signals between time and frequency domains. Color versions of one or more of the figures in this article are available online at https://ieeexplore.ieee.org. An alternative to the CORDIC is to simplify a complex multiplier into shift-and-add operations This approach is useful for rotators that have to rotate among a small number of angles. This paper proposes a new approach to simplify rotators in FFT hardware architectures based on a set of transformations called decimation, reduction, center, move and merge. These techniques take advantage of three main ideas. This means that the same rotator calculates all the rotations at the same stage of the flow graph in Fig. 1 and, the rotator must be configurable to rotate by different angles at different clock cycles
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