Performance Of Fast Fourier Transform Research Articles

Selection of Methods of Surface Texture Characterisation for Reduction of the Frequency-Based Errors in the Measurement and Data Analysis Processes.

Processes of surface texture characterisation can be roughly divided into measurement issues and analysis of the results obtained. Both actions can be fraught with various errors, some of which can be analysed with frequency performance. In this paper, various types of surface topographies were studied, e.g., cylinder liners after the plateau-honing process, plateau-honed liners with additionally burnished dimples of various sizes (width and depth), turned, milled, ground, laser-textured, ceramic, composite and some general isotropic topographies, respectively. They were measured with a stylus or via optical (white light interferometry) methods. They were analysed with frequency-based methods, proposed in often applied measuring equipment, e.g., power spectral density, autocorrelation function and spectral analysis. All of the methods were supported by regular (commonly used) algorithms, or filters with (robust) Gaussian, median, spline or Fast Fourier Transform performance, respectively. The main purpose of the paper was to use regular techniques for the improvement of detection and reduction processes regarding the influence of high-frequency noise on the results of surface texture measurements. It was found that for selected types of surface textures, profile (2D) analysis gave more confidential results than areal (3D) characterisation. It was therefore suggested to detect and remove frequency-defined errors with a multi-threaded performance application. In the end, some guidance on how to use regular methods in the analysis of selected types of surface topographies following the reduction of both measurement (high-frequency noise) and data analysis errors was required.

Customizing FFT with FMA for China Accelerator

Recently, Fast Fourier Transform (FFT) was introduced to study pattern characterization in textiles. Accelerators are a promising platform to accelerate large-scale FFT computation. However, current accelerating FFT only uses the accelerator to compute, but uses a CPU as a mere task controller. Additionally, a specified interface for FFT is built into the China accelerator (CA), which severely restricts FFT parallelization and performance. Hence, we transform four multiplications and six additions into six Fused Multiply Add (FMA) operations, then reduce total float operations by 40%, assisted by FMAs equipped with a Vector Processing Unit (VPE). Moreover, we propose an Interface Adapter (IA) to cater to a specified interface and a Fused Algorithm for Interface Adapter (FAIA) to fully use both the CA and CPU to compute large-scale FFT with coordination. Experimental results validated successful performance.

Data-driven Detection and Early Prediction of Thermoacoustic Instability in a Multi-nozzle Combustor

ABSTRACT Thermoacoustic instability (TAI) is a critical issue in modern lean-burn gas-turbine combustors, which is induced by a strong coupling between the resonant combustor acoustics and fluctuations in the heat release rate. This instability may lead to high-amplitude pressure waves that generate undesirable noise levels as well as fatigue stresses in mechanical structures of the combustor. The intense pressure fluctuations due to TAI may also cause large flow perturbations and possibly flow reversal that may lead to flame oscillations, flame liftoff, and even flame blow-out. Hence, there is a strong need for exercising control actions in a timely fashion to mitigate the TAI phenomena. Anomaly detection is an essential prerequisite to the design of a good controller and such a detector must be able to reliably predict a forthcoming TAI. To detect and predict the onset of a TAI from an ensemble of pressure time series, this paper investigates three data-driven methods: Fast Fourier transform (FFT), symbolic time series analysis (STSA), and hidden Markov modeling (HMM). The main focus of the paper is to make a comparative evaluation of these three anomaly detection methods for classification of the current regime of operation into stable and unstable categories as well as for real-time identification of precursors to impending instabilities with short-length time series of measured variables (e.g., pressure oscillations). The results, generated on experimental data from a multi-nozzle combustor apparatus, have been compared to evaluate the performance of FFT, STSA, and HMM methods for TAI analysis.

Research on the realization and optimization of FFTs in ARMv8 platform

Fast Fourier transform (FFT) is a basic algorithm in digital signal processing and has been widely used in engineering, science and mathematical calculation. With the wide application of ARMv8 processor, it is more and more important to study FFT algorithm to realize high performance on ARMv8 platform. In the current open source FFT library, FFTW packages are mainly suitable for ARMv8 platform, while FFTW and FFTs packages are mainly suitable for ARMv7 platform. This paper implements and optimizes FFTs software package on ARMv8 platform, making it suitable for ARMv8 processor. The experimental results show that the performance of FFTs is improved by about 18% compared with FFTW in ARMv8 platform.

Research on FFT Algorithm Use SMP System

Based on the theoretical research of a series of algorithms of adaptive beamforming and space-time adaptive processing, it is necessary to discuss the implementation of related algorithms on the machine hardware platform. Fast Fourier transform (FFT) is an essential process in this implementation. With the development of array antennas, the number of points to be calculated by the FFT has also increased significantly. Therefore, the ultra-large point FFT has become a key technology for current antenna signal processing. Most of the existing FFT algorithms are researched based on single-core processors, and there is very little literature on the research of super-large-point FFT algorithms suitable for Symmetric Multiprocessor (SMP). In this paper, through analyzing the characteristics of a symmetric multi-processor (SMP) parallel processing system, the very large FFT fast algorithm (VLFFT) is proposed. This algorithm significantly reduces the dependence on memory and improves the FFT's performance using the limited rules of the one-dimensional sequence split, changing the twiddle factor calculation method, and optimizing the data distribution and storage access. And the research's optimized very large FFT algorithms is also summarized in the paper. Experiment results show that the algorithm is suitable for the SMP platform and can effectively solve the problem of the very large FFT, which make single-core processors harder to realize.

High Speed RADIX-2 Butterfly Structure Using Novel Wallace Multiplier

In Signal Processing applications the arithmetic units mainly consists of adders and multipliers. These arithmetic units are used in to enhance the performance of Fast Fourier Transform (FFT) Butterfly structure implementation. This paper discusses the addition and multiplication algorithms for parameters like speed, area and power. The best suited among all adders are Kogge Stone Adder (KSA) while among multipliers are Wallace multiplier(WM) which is used for the implementation of the FFT structure. Verilog coding is used for implementation of circuit and the tool used is Xilinx ISE 14.1 Design suite.

GPU acceleration of time gating based reverse time migration using the pseudospectral time-domain algorithm

We present a Graphics Processing Units (GPU) implementation of time gating based reverse time migration (TG-RTM) which uses the pseudospectral time-domain (PSTD) algorithm to solve the acoustic wave equation. TG-RTM adopts the prior information of surrounding media to strengthen the correlation between the wavefields, thus has advantages in locating the targets over traditional reverse time migration (RTM) methods. The PSTD algorithm adopts fast Fourier transform (FFT) to obtain the spatial derivatives and a perfectly matched layer as an absorbing boundary condition to eliminate the wraparound effect introduced by the FFT periodicity assumption. Under the Nyquist sampling theorem, the spatial sampling density of the PSTD algorithm requires only two points per minimum wavelength. Thus, the PSTD algorithm can solve the time dependent partial differential equations efficiently and save mass computer memory. Compared with traditional RTM based on the finite difference time domain (FDTD) algorithm, the proposed RTM based on the PSTD algorithm can be implemented on a memory-limited GPU and can solve much larger models. To secure a better performance and generality of FFT in GPU, we present a scheme which combines 1D FFT with matrix transpositions instead of using 3D FFT directly. The matrix transpositions use shared memory to improve memory access efficiency. We also apply an efficient FFT scheme which replaces even-sized R2C FFT with a half-sized C2C FFT. For a small amount and balanced memory swapping from computer to GPU, we save the boundaries in lieu of checkpointing scheme when we propagate the source wavefield forward and backward. The proposed RTM has an acceleration ratio of about 80 times by a Tesla K20X GPU card on a desktop computer. The simulation results of 2D and 3D models demonstrate that the proposed RTM is fast and inexpensive.

Performance Optimization of Multithreaded 2D Fast Fourier Transform on Multicore Processors Using Load Imbalancing Parallel Computing Method

Fast Fourier transform (FFT) is a key routine employed in application domains such as molecular dynamics, computational fluid dynamics, signal processing, image processing, and condition monitoring systems. Its performance on modern multicore platforms is therefore of paramount concern to the high-performance computing community. The inherent complexities in these platforms such as severe resource contention and non-uniform memory access, however, pose formidable challenges. We study the performance profiles of multithreaded 2D FFTs provided in three highly optimized packages, FFTW-2.1.5, FFTW-3.3.7, and Intel Math Kernel Library (Intel MKL) FFT, on a modern Intel Haswell multicore processor consisting of 36 cores. We show that all the three routines exhibit drastic performance variations, and hence, their average performances are considerably lower than their peak performances. The ratios of average-to-peak performance for the 2D FFT routines from the three packages are 40%, 30%, and 24%. We conclude that improving the average performance of 2D FFT on modern multicore processors by the removal of performance variations constitutes a tremendous research challenge. To address this challenge, we propose two novel optimization methods, PFFT-FPM and PFFT-FPM-PAD, specifically designed and implemented for 2D FFT. The methods employ model-based parallel computing using a load-imbalancing technique. They take as inputs, the discrete 3D functions of the performance of the processors against problem size, compute 2D DFT of a complex signal matrix of size $N \times N$ using $p$ abstract processors, and output the transformed signal matrix. Based on our experiments on a modern Intel Haswell multicore server consisting of 36 physical cores, the average and maximum speedups observed for PFFT-FPM using FFTW-3.3.7 are $1.9\times $ and $6.8\times $ , and the average and maximum speedups observed using Intel MKL FFT are $1.3\times $ and $2\times $ . The average and maximum speedups observed for PFFT-FPM-PAD using FFTW-3.3.7 are $2\times $ and $9.4\times $ , and the average and maximum speedups observed using Intel MKL FFT are $1.4\times $ and $5.9\times $ .

A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition

Fast Fourier transform (FFT) is the kernel and the most time-consuming algorithm in the domain of digital signal processing, and the FFT sizes of different applications are very different. Therefore, this paper proposes a variable-size FFT hardware accelerator, which fully supports the IEEE-754 single-precision floating-point standard and the FFT calculation with a wide size range from 2 to 220 points. First, a parallel Cooley–Tukey FFT algorithm based on matrix transposition (MT) is proposed, which can efficiently divide a large size FFT into several small size FFTs that can be executed in parallel. Second, guided by this algorithm, the FFT hardware accelerator is designed, and several FFT performance optimization techniques such as hybrid twiddle factor generation, multibank data memory, block MT, and token-based task scheduling are proposed. Third, its VLSI implementation is detailed, showing that it can work at 1 GHz with the area of 2.4 mm2 and the power consumption of 91.3 mW at 25 °C, 0.9 V. Finally, several experiments are carried out to evaluate the proposal’s performance in terms of FFT execution time, resource utilization, and power consumption. Comparative experiments show that our FFT hardware accelerator achieves at most $18.89\times $ speedups in comparison to two software-only solutions and two hardware-dedicated solutions.

High Temperature Quadrature Amplitude Modulation over Orthogonal Frequency Division Multiplexing

As downhole tools advance, they require increasingly higher data rates in communication with the surface. Current data rates over HT single-conductor wireline are limited to approximately 200 kbps. Long cables and harsh environments create a limiting challenge to standard serial bit rates due to high cable impedance and component availability. Keying techniques are often used to improve the robustness and speed of data links over long cables. Frequency shift keying (FSK) is a common implementation where data is encoded by specific frequencies on the data line. Amplitude shift keying (ASK) and phase shift keying (PSK) work on similar principles. In this project we apply quadrature amplitude modulation (QAM), a combination of PSK and ASK, and carry it over multiple frequency channels simultaneously using orthogonal frequency division multiplexing (OFDM). QAM over OFDM is a digital communications technique similar to those used in the telecommunications industry for digital subscriber line (DSL) connections and cellular networks. Using our data link, laboratory tests have demonstrated data rates of up to 3.8 Mbps over a 5000 ft (1524 m) single conductor wireline cable with less than 1e-8 bit error rate. Higher data rates are possible if error mitigation and correction coding is used. Gray encoding is an error mitigation technique where nearby points on the QAM constellation are similar in value so the errors are off only by least significant bits. A prototype point to point link protocol was developed in which the cable bandwidth is assessed empirically to optimize the OFDM by allowing for correction of cable distortion at each frequency independently. The protocol can enable use of the developed data link for a variety of tools with little to no changes by hiding all the complexity from the tool. Future versions of the protocol will automatically detect and correct transmission errors, allow for data buffering/retransmission and provide feedback as to the quality of the link. However, this new approach to the problem requires more complex computation to encode the data and signal generation electronics to produce the required waveform. One of the key challenges to full implementation of this concept on high temperature electronics is that a downhole fast Fourier transform (FFT) is required to decode the QAM information for downlink and an inverse FFT (IFFT) is required to efficiently encode data for uplink. The IFFT allows combination of multiple QAM data streams into a time series which can be converted to analog waveforms. High temperature testing of FFT and IFFT performance on the RelChip RC10001 microcontroller is included here. Also included here are the details of development of a high temperature digital to analog converter (DAC) to create composite signals and a high temperature line driver to boost analog signal transmission. This paper describes the communication architecture, the systems developed for high temperature implementation, and evaluations/implementations on high temperature computation devices.

Enhanced Performance of Fast Fourier Transform (FFT) Based Cardiac System with Modified Compressor using Vedic Algorithm

In Digital Signal Processing, different algorithms are used to perform various functions, out of which Fast Fourier Transform is an important algorithm which is used in linear filtering, spectrum analysis, etc. FFT computation involves (Nlog2N) multiplication and (N/2 log2N) addition operations. So multiplier structure plays an important role in FFT processor configuration. In this paper a high speed FFT processor using Vedic mathematics is proposed in which a novel 4: 2, 5: 2 and 7: 2 compressors are used to perform the partial product addition. It is shown that the proposed compressor based multiplier is faster than the existing multiplier. Also it is shown that the FFT processor using this compressor based multiplier achieves less area complexity and High speed computation.

Improve Diversity with OFDM Technique in V-BLAST Architecture

There are several technologies to transmit any signal in wireless communication. Technologies are: Integration, Differentiation, TDM (Time Division Multiplexing), FDM (Frequency Division Multiplexing), OFDM (Orthogonal Frequency Division Multiplexing). In which OFDM is superior to any other technology. It is widely used in MIMO schemes also where multiple transmission and reception process done with different types of antennas.V-BLAST is the technique where the completion of strongest signal capturing and it gives sturdiest output with the help of different receiver approximation techniques like MMSE (Minimum Mean Square Error), ZF (Zero Forcing) and ML (Maximum Likelihood). In this paper we throw some light on why choose MMSE, ZF and ML to identify overall Throughput, adjustment in pre-coding, performance of FFT (Fast Fourier Transform) and IFFT (Inverse FFT) in OFDM-VBLAST. Also examine which receiver technique is widely and very useful in practical scenario.

Hybrid and 4-D FFT implementations of an open-source parallel FFT package OpenFFT

The fast Fourier transform (FFT) is a fundamental kernel in a wide variety of science and engineering fields from electronic structure calculations to medical imaging. OpenFFT is an open-source package for parallel 3-D FFTs, built on a domain decomposition method with optimal communication for minimizing the volume of communication. However, OpenFFT version 1.1 does not support hybrid calculations for fully utilizing common multi-core machines and parallel 4-D FFTs. In addition, there exist several state-of-the-art open-source packages for parallel FFTs, and performance comparison among them would be interesting and helpful for potential users. In this paper, we (1) extend the functionality of OpenFFT by developing a hybrid MPI/OpenMP version and a parallel 4-D FFT, and (2) conduct performance comparison among the currently available parallel FFT packages. In the former, we first analyze the computational parts of OpenFFT to explore the opportunities for taking advantage of fine-grained parallelization with OpenMP. Based on the analysis, we implement and make comparison to choose between the two most promising hybrid options. We then develop the parallel 4-D FFT by extending the hybrid implementation of the parallel 3-D FFT. The decomposition method for 4-D FFTs preserves its 3-D original features to maximize the localization of data when transposing. In the latter, we evaluate and compare the performance of FFTE, P3DFFT, PFFT, 2DECOMP&FFT, and OpenFFT for both 3-D and 4-D FFTs on a number of different machines with varied computational scales. The evaluation results assert the benefit of the hybrid feature in improving the scalability of OpenFFT, and confirm its minimal volume of communication for 4-D FFTs in practice. Also, although no significant difference is observed in overall performance in general, there are specific cases when some packages have the edge over the others.

Influence of memory access patterns to small-scale FFT performance

Modern GPUs (Graphics Processing Units) offer very high computing power at relative low cost. To take advantage of their computing resources and develop efficient implementations is essential to have certain knowledge about the architecture and memory hierarchy. In this paper, we use the FFT (Fast Fourier Transform) as a benchmark tool to analyze different aspects of GPU architectures, like the influence of the memory access pattern or the impact of the register pressure. The FFT is a good tool for performance analysis because it is used in many digital signal processing applications and has a good balance between computational cost and memory bandwidth requirements.

Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture

The fast Fourier transform (FFT) is a fundamental kernel of many computation-intensive scientific applications. This paper deals with an implementation of the FFT on the accelerator system, a heterogeneous multicore architecture to accelerate computation-intensive parallel computing in scientific and engineering applications. The Engineering and Scientific Computation Accelerator (ESCA) consists of a control unit and a single instruction multiple data (SIMD) processing element (PE) array, in which PEs communicate with each other via a hierarchical two-level network-on-chip (NoC) with high bandwidth and low latency. We exploit the architecture features of ESCA to implement a parallel FFT algorithm efficiently. Experimental results show that both the proposed parallel FFT algorithm and the ESCA architecture are scalable. The 16-bit fixed-point parallel FFT performance of ESCA is compared with a published work to prove the superiority of the mapping algorithm and the hardware architecture. The floating-point parallel FFT performances of ESCA are evaluated and compared with those of the IBM Cell processor and GPU to demonstrate the computing power of the ESCA system for high performance applications.

Gather/scatter hardware support for accelerating Fast Fourier Transform

As we enter the multi-core era, seeking methods to boost the performance of single-threaded applications remains critical. Achieving gains in processor performance by increasing the operating frequency has begun to meet more obstacles. However, significant performance improvements can be achieved by extending the capability of the processor with the addition of hardware support, which makes much more effective use of the available transistors. This paper presents a novel hardware support called, DistTree, to speed up processor performance. The DistTree hardware automates gather and scatter operations for applications with complex but predictable memory access patterns like the Fast Fourier Transform (FFT). With this hardware support integrated with a modern microprocessor (the Alpha architecture in our experiments), the FFT performance can reap a more than twofold increase when compared against the FFTW library, a state-of-the-art implementation. The DistTree hardware support enables the processor to spend the majority of processor cycles on executing the computations of an algorithm by reducing both the arithmetic and address computation overhead. Therefore, the performance of many single-threaded applications can be significantly increased.

Analysis of communications and implementation performance of FFT based carrier synchronization of BPSK/QPSK bursts

Abstract. Carrier synchronization is a vital part of every inner receiver in wireless communications. Frequency offset and phase offset of the received burst must be estimated and the received samples must be corrected according to the estimation. An approximation of the maximum likelihood estimation of frequency offset is given by the Fast Fourier Transform (FFT). The accuracy of the estimation as well as the hardware complexity and throughput depend on the number of FFT points. We demonstrate three techniques to improve the accuracy of the FFT based frequency offset estimation respectively to reduce the number of needed FFT points. These three techniques as well as the reference algorithm without improvements combine phase offset estimation with frequency offset estimation. We present the communications and FPGA implementation performance of these techniques.

Parallel Implementations of 1-D Fast Fourier Transform Without Interprocessor Communication

Computing 1-D Fast Fourier Transform (FFT ) using the conventional 4-step FFT on parallel computers requires intensive all-toall communication, which can adversely affect the performance of FFT. In this paper, we present 2-step-no-communication and 3-step-no-communication algorithms, which are parallel algorithms for 1-D FFT without interprocessor communication. One of the main advantages of these algorithms is the absence of all-to-all communication between processors, albeit at the expense of increased computation compared to the conventional 4-step FFT. If the cost of extra computation required by the 2-step-no-communication and the 3-step-no-communication algorithms is more than offset by the cost of all-to-all communication in the 4-step FFT , then these two no-communication algorithms will outperform the 4-step FFT algorithm. We test the 2-step-no-communication and the 3-step-nocommunication algorithms in two parallel systems (a 32-node Beowulf cluster and 8-node symmetric multiprocessors), with varying costs of all-to-all communication and computation. The experimental results show that the no-communication algorithms perform better than the 4-step FFT in the SMP only for relatively small data sizes, but the no-communication algorithms outperform the 4-step FFT in the Beowulf cluster for all data sizes tested.

TWO PARALLEL 1-D FFT ALGORITHMS WITHOUT ALL-TO-ALL COMMUNICATION

Computing the 1-D Fast Fourier Transform (FFT) using the conventional six-step FFT algorithm on parallel computers requires intensive all-to-all communication due to the necessity of matrix transpose in three steps. This all-to-all communication is a limiting factor in improving the performance of FFT in its parallel implementations. In this paper, we present two parallel algorithms for implementing the 1-D FFT without all-to-all communication between processors, at the expense of increased inner-processor computation as compared to the conventional six-step FFT algorithm. Our analysis reveals the advantage of these two algorithms over the six-step FFT algorithm in parallel systems where the cost of inter-processor communication outweighs the cost of inner-processor computation. As a case study, we choose a 32-node Beowulf cluster with fast processors (running at 2 GHz) but relatively slow inter-processor communication (over a 100 Mbit/s switch). Simulation results on this cluster demonstrate that the proposed no-communication FFT algorithms can achieve a speedup ranging from 1.1 to 1.5 over the six-step FFT algorithm.

Efficient 2D FFT implementation on mediaprocessors

We have developed an efficient implementation to compute the 2D fast Fourier transform (FFT) on a new very long instruction word programmable mediaprocessor. Using instruction-level parallelism and a multimedia instruction set, our radix-4 Cooley–Tukey algorithm optimally maps the FFT computation to the processing resources of the Hitachi/Equator’s MAP mediaprocessor. We have also achieved more efficient data I/O and lower data transfer time compared to traditional implementations by processing several columns in parallel during the column-wise stage of row–column decomposition. We used a programmable direct memory access engine and a double-buffering scheme in the data cache to perform the computation and the data transfer in parallel. Our implementation resulted in 22.4 ms total execution time for a 512 × 512-point 2D complex FFT, which is faster than previous single-chip programmable or dedicated solutions. The implementations on two other mediaprocessors, the TriMedia TM1100 and the BOPS ManArray, illustrate the importance of the instruction set architecture for achieving high performance and the trend of data I/O becoming the limitation on the 2D FFT performance in newer mediaprocessors.