Fast Fourier Transform Operation Research Articles

Efficient simulation of fully nonstationary wind velocity field by an enhanced numerical truncation method

The spectral representation method (SRM) is widely utilized to simulate the fully nonstationary wind velocity field with time-varying coherence. The simulation samples are generated by double summation of harmonic functions. Despite the fast Fourier transform (FFT) technique has been employed to accelerate the summation in the frequency dimension, the computational efficiency is still constrained by the number of simulation points and samples due to the time-consuming summation operation in the spatial dimension. In this study, a numerical truncation method is presented to further quicken the SRM-based simulation of a fully nonstationary wind velocity field. The fundamental idea is that the harmonic functions with tiny amplitude are inconsequential and can be omitted. A novel diagonal decoupling approach is first developed to rearrange the double summation. Further, the frequency truncation scheme is established to simplify the summation in the spatial dimension. Meanwhile, the FFT operations to calculate the summation in the frequency dimension are also considerably reduced. Finally, the superior performance of the proposed method on precision and efficiency is demonstrated by numerical examples.

Strain fields measurement using frequency domain Savitzky–Golay filters in digital image correlation

Savitzky–Golay (SG) filter is an effective and convenient gradient calculation method employed for full-field strain measurement in digital image correlation (DIC). Currently, the strain field can be conveniently obtained by moving smoothing filtering with SG filters. This is a method of spatial filtering, which offers the advantages of easy implementation and high accuracy. This study proposed a strain calculation method based on frequency domain SG (FD-SG) filtering. Prior to performing FD-SG filtering, data extension operations involving outer-boundary padding and zero-padding were performed on the displacement field data. Similarly, the SG filters template was extended with zero-padding and circularly shift operations. Subsequently, FD-SG filters were generated by applying the fast Fourier transform (FFT) to the expanded SG template. Thereafter, FD-SG filtering was implemented through the multiplication of the displacement in the Fourier-domain by an FD-SG filter. Finally, the strain field was obtained via inverse FFT and valid data interception operation. The simulation and practical experiments confirmed the equivalent accuracy exhibited by FD-SG and spatial domain SG filtering. Thus, the proposed FD-SG filtering method has great potential for real-time strain measurement in DIC.

FPGA Implementation of the Chirp-Scaling Algorithm for Real-Time Synthetic Aperture Radar Imaging.

Synthetic aperture radar (SAR), which can generate images of regions or objects, is an important research area of radar. The chirp scaling algorithm (CSA) is a representative SAR imaging algorithm. The CSA has a simple structure comprising phase compensation and fast Fourier transform (FFT) operations by replacing interpolation for range cell migration correction (RCMC) with phase compensation. However, real-time processing still requires many computations and a long execution time. Therefore, it is necessary to develop a hardware accelerator to improve the speed of algorithm processing. In addition, the demand for a small SAR system that can be mounted on a small aircraft or drone and that satisfies the constraints of area and power consumption is increasing. In this study, we proposed a CSA-based SAR processor that supports FFT and phase compensation operations and presents field-programmable gate array (FPGA)-based implementation results. We also proposed a modified CSA flow that simplifies the traditional CSA flow by changing the order in which the transpose operation occurs. Therefore, the proposed CSA-based SAR processor was designed to be suitable for modified CSA flow. We designed the multiplier for FFT to be shared for phase compensation, thereby achieving area efficiency and simplifying the data flow. The proposed CSA-based SAR processor was implemented on a Xilinx UltraScale+ MPSoC FPGA device and designed using Verilog-HDL. After comparing the execution times of the proposed SAR processor and the ARM cortex-A53 microprocessor, we observed a 136.2-fold increase in speed for the 4096 × 4096-pixel image.

An FFT-Based Implementation of the First-Order Small-Slope Approximation for Simulating Microwave Scattering From Sea Surface

This article presents a simple and efficient implementation of the first-order small-slope approximation (SSA-1) to simulate the normalized radar scattering cross section (NRCS) from ocean surface based on fast Fourier transform (FFT) of the equivalent sea surface autocorrelation function. The implementation process only takes a pair of FFT operations between sea wave spectrum and sea surface autocorrelation function. Compared with the reported implementations of SSA-1 model based on the series expansion, the proposed method (called as “FFT-based implementation”) reduces the computation amount of FFT operations greatly. To examine the accuracy and efficiency of the FFT-based implementation relative to the direct integration implementation of SSA-1 (called as “classical implementation”), the monostatic and bistatic NRCSs simulated by using the two implementations with the help of Elfouhaily sea spectrum at various radar frequencies and sea states are compared. The comparison results indicate the FFT-based implementation not only holds almost the same accuracy as the classical implementation but also has a higher efficiency, especially for the simulation scenarios with small Rayleigh parameters. Furthermore, we discuss the influence of sampling range and sampling interval of sea spectrum components on the accuracy and efficiency of the FFT-based implementation and its feasibility on the simplified second-order SSA (SSA-2) model with the mathematic expression similar to SSA-1. The simulation results show that the sampling range and sampling interval of sea spectrum have different effect on the accuracy and efficiency of the FFT-based implementation, and the proposed implementation method is also feasible for the simplified SSA-2 model.

Simulation of Nonseparable Nonstationary Spatially Varying Ground Motions with an Enhanced Interpolation Approximation Approach

An enhanced interpolation approach is developed for simulating nonseparable nonstationary ground motions on the basis of the spectral representation method, which mainly contains two steps of interpolations and an optimization. Firstly, the interpolation technique is utilized to reduce the Cholesky decomposition time of the lagged coherence matrix. The square root of the evolutionary power spectral density is then decoupled into several time and frequency discrete functions using the proper orthogonal decomposition (POD) interpolation technique, which results in the availability of the fast Fourier transform (FFT) technique in the simulation. Compared with existing decoupling schemes, the POD interpolation achieves a significant efficiency improvement with a slight accuracy reduction. Finally, the simulation formula is further optimized to reduce the number of FFT operations. The accuracy and efficiency of this method are verified with the numerical examples of nonstationary ground motions simulation. Results show that the error introduced by two-step interpolations is fairly small and the simulation agrees with the targets very well. Furthermore, the efficiency generating sample function is significantly enhanced.

Multipoint Combined Processing for FMCW LiDAR

This paper proposes a multipoint processing method (MCP) for FMCW LiDAR. The proposed method reduces the number of fast Fourier transform (FFT) calculation compared to the traditional FMCW LiDAR method. This leads to a reduced power consumption. To end this, the proposed method accumulates the multiple beat frequencies in the time domain before the FMCW LiDAR extracts the measured distances from the beat frequencies using the fast Fourier transform (FFT). In order to distinguish the distances that are extracted from the FFT operation, a pulse-width modulation (PWM) counter and an analog comparator were applied. A hysteresis analog comparator was used to increase the immunity from the external noise. When the measured distances are too close to be indistinguishable by the FFT, it may fail to distinguish the measurement order. In order to respond to this situation, the proposed method includes a point-calibration algorithm. The root mean square error (RMSE) and hardware resource usage are utilized in order to assess the performance of the proposed method. The experimental results show that the proposed method achieves power usage time savings compared to the traditional method.

Universal Filtered Multicarrier Receiver Complexity Reduction to Orthogonal Frequency Division Multiplexing Receiver

The Universal Filtered Multicarrier (UFMC) waveform technology is one of the promising waveforms for 5G and beyond 5G networks. Owing 2N-point Fast Fourier Transform (FFT) processor at the UFMC receiver, the computational and implementation complexity is two times more than the conventional Orthogonal Frequency Division Multiplexing (OFDM) receiver system. In this paper, we proposed a simplified UFMC receiver structure to reduce computational complexity as well as hardware requirements. The received UFMC symbol simplified exactly to its equivalent after performing 2N-point FFT and decimation operations. In which, the mathematical model of the frequency-domain UFMC signal is rederived after processing through 2N-point FFT and decimator, and the simplified signal is generated with an N-point FFT. Accordingly, the 2N-point FFT processor and decimator are replaced with a single N-point FFT processor. This approach reduces the 50% computational complexity at the FFT processor level hence the hardware and processing time. The computational complexity of the proposed receiver model is approximately equivalent to the OFDM receiver. Additionally, analyzed the mathematical model for the simplified UFMC receiver and the comparative performance of the UFMC system with the conventional model.

An Efficient mmW Frequency-Domain Imaging Algorithm for Near-Field Scanning 1-D SIMO/MIMO Array

In recent years, millimeter-wave (mmW) 3D imaging technology for scanning 1D single-input multiple-output (SIMO) or multiple-input multiple-output (MIMO) array has been extensively studied due to its unique advantages in near-field applications. However, current imaging algorithms for this kind of scheme are not satisfactory, either of low quality since irrational approximations are introduced, or too slow as the back projection method is employed. In this paper, an efficient frequency-domain imaging algorithm is developed to fetch up these shortages. The precise spectral expression of the echo signal within SIMO data is derived through spherical-wave decomposition and fast Fourier transform (FFT) operations. By properly approximating the nonlinear phase, the wavefront curvature is compensated after employing a 1D Stolt interpolation, and then the reflectivity map of the target can be obtained through several multiplications and inverse FFT operations. Image reconstruction for a MIMO array can be realized by coherently summing up all the SIMO focusing results. Both simulation analysis and experimental results demonstrate the effectiveness of the proposed algorithm in imaging quality and computational efficiency.

Plant leaf classification and retrieval using multi‐scale shape descriptor

Plant leaf classification is a significant and challenging research problem in computer vision area. In this study, an original multi-scale shape descriptor is presented to perform leaf classification and retrieval. Firstly, a novel iterative rule is proposed as scales generation method, which is parameter free. Secondly, leaf contour points are represented by angle information which is calculated using their neighbour points under each scale. The angle information representation is invariant to image rotation, translation and scaling. More importantly, it can describe leaf in a hierarchical way by capturing leaf features from global to local variations. Then Fast Fourier Transform operation is applied to make the representation more compact and independent from starting point. Subsequently, for leaf retrieval the dissimilarity of each pair of leaf under each scale is computed using city block metric. And support vector machine is used as classifier for leaf classification. Finally, experiments and comparisons with multiple state-of-the-art approaches are performed. The classification accuracy was 96.85% and 93.56% respectively on Swedish and Flavia leaf datasets. The mean average precision score was 66.42%, 76.69% and 44.14% respectively on Flavia, Swedish and MEW2012 leaf datasets. The results demonstrate that the proposed method has excellent performance.

Multicarrier Faster-Than-Nyquist Based on Efficient Implementation and Probabilistic Shaping

The conventional multicarrier faster-than-Nyquist (MFTN) achieves the spectral efficiency (SE) gain by deep compression. However, deep compression leads to severe intersymbol interference (ISI) or intercarrier interference (ICI). We propose the MFTN based on efficient implementation and probabilistic amplitude shaping (PAS) to achieve the SE gain with low complexity. We use mild compression instead of conventional deep compression to achieve the compression gain. The MFTN transceiver with the mild compression can be efficiently implemented by fast Fourier transform (FFT)/inverse FFT (IFFT) and filtering operation. The linear pre-equalization (LPE) method eliminates the ISI for mild compression. The MFTN with efficient implementation employs PAS to achieve extra shaping gain. The theoretical results and simulation results show that our method can achieve better performance than the conventional FTN/MFTN with deep compression. The proposed method does not require a complex equalization algorithm and global turbo iteration so that the total complexity is reduced.

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

PurposeThis paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle.Design/methodology/approachA new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles.FindingsWith the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations.Originality/valueThis is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration

The emerging edge intelligence requires low-cost energy-efficient neural network (NN) processors. Supporting various types of edge NN models leads to extra circuit overhead. Designing a unified NN processor with high energy/area efficiency is challenging. This work presents a frequency-domain-accelerated unified NN processor, named STICKER-T. It combines algorithm, architecture, and circuit-level optimization to achieve high energy/area efficiency. By utilizing the block-circulant NN (CirCNN) algorithm, this work supports frequency-domain acceleration and a unified workflow for convolutional, fully connected, and recurrent NN (CNN/FC/RNN). Three key innovations are proposed. First, a block-circulant-accelerated chip architecture is implemented to support unified CNN/FC/RNN workflow. Second, a multi-bit 8-128-point global-parallel local-bit-serial fast Fourier transform (FFT) module is designed for efficient high-throughput FFT/inverse FFT (IFFT) operation. Third, by utilizing a 6T hierarchical-bitline-switching transpose-SRAM (HBST-TRAM), 2-D data reuse is enabled in the proposed multi-bit frequency-domain multiply-accumulate (MAC) array. STICKER-T was fabricated in a 65-nm CMOS technology. It can operate at 0.54-1.15 V and 25-200 MHz with 13.3-339-mW power consumption. The peak energy efficiency achieves 140.3 TOPS/W. It shows 8.1 × area efficiency and 4.2 × energy efficiency at 4-bit precision compared with the state-of-the-art reconfigurable NN processor.

Design optimisation of multiplier‐free parallel pipelined FFT on field programmable gate array

Fast Fourier transform (FFT) is utilised to minimise the complexity of discrete Fourier transform by converting signals from frequency domain to time domain and conversely. Digital signal processing systems like image processing, general filtering, sonar, spread-spectrum communications and convolutions use this FFT operations. Radix-2 decimation in frequency (R2DIF) method is designed to execute an efficient FFT architecture in this study. Each and every state of the FFT stores the input and output the data using the R2DIF method. Also, the complex twiddle factors in FFT are replaced by the proposed uniform Montgomery algorithm. This technique simply performs the shift-add method instead of the multiplication process which also enhances the convergence of the calculation. So, the FFT implementation is done with the help of the proposed method which reduces the usage of chips in the process. Based on this approach, it performs the operation of FFT from 16 points to 1024 points and the performance of this proposed method is compared with existing approaches. Moreover, it does not require expensive dedicated functional blocks and uses only distributed logic resources. The simulation is carried out by the Xilinx platform using Verilog coding. The proposed design outperforms conventional methods in terms of less usage power and high speed.

FFT‐Based Multiband Spectrum Sensing in SIMO In‐band Full‐Duplex Cognitive Radio Networks

AbstractThis paper presents fast Fourier transform (FFT)‐based multiband spectrum sensing over multipath Rayleigh frequency selective fading channels in single input multiple output (SIMO) in‐band full‐duplex (FD) cognitive radio (CR) networks (FDCRNs) under residual self‐interference (RSI). In this work, first, multiband energy detection using Neyman Pearson criterion is proposed in FDCRNs under RSI, where the secondary user is equipped with multiple receive antennas to exploit spatial diversity. Next, a two‐dimensional averaging is done to overcome spectrum leakage problem occurring due to FFT operation in orthogonal frequency division multiplexing (OFDM) system. The closed form expressions for average probability of detection and probability of false alarm are derived for SIMO FDCRNs under RSI. Further, RSI cancelation is performed employing noise robust wavelet decomposition‐based least squares scheme and the corresponding simulation studies indicate that the proposed algorithm further improves the detection performance in SIMO FDCRNs.

PARALLEL PIPELINED MULTI RADIX VARIABLE LENGTH FAST FOURIER TRANSFORM ARCHITECTURE

There is an enormous demand for high speed data communication or high speed internet using Long Term Evolution (LTE) or LTE-Advanced communication methods. To achieve the high speed data rate in the receiver side, it is necessary to achieve high throughput in the Fast Fourier transform (FFT) architecture. Hence there is demand to improve the throughput of the FFT architectures used for high speed data communication. The FFT architecture is designed and optimized for LTE-A applications. However, the high throughput has been achieved by sacrificing hardware resources of the Field Programmable Gate Array (FPGA). Many fixed and variable length FFT processors are proposed by the researchers with improved performance focusing either on algorithmic modifications, novel architectural optimizations or radix selection. Among these FFT processors, the goal and main objectives of this paper are: 1. To design and implement a pipelined FFT architecture to give high throughput for LTE-A MIMO applications 2. To develop an intellectual property (IP) core for FFT computation with variable FFT size 3. To propose a parallel implementation to increase the performance of LTE-A baseband processing system. In an Orthogonal Frequency Division Multiplexing (OFDM) baseband communication system, FFT operation is one of the highest computationally serious tasks which directly influence the communication system performance factor. The baseband hardware has to be capable as well as efficient enough to calculate FFT in specific timing restrictions. Thus, the parallel pipelined multi radix Variable Length FFT architectures for LTE-A Multiple-Input-Multiple-Output (MIMO) applications have been designed. The proposed FFT architecture delivers a throughput of 550 MSPS at the maximum clock rate of 550 MHz. The proposed FFT support the FFT length of 64, 128, 256, 512, 1024 and 2048 for LTE-Advanced MIMO standard. The proposed FFT architecture has been implemented in Xilinx Artix-7 FPGA device and the performance metrics have been analysed. Even though the proposed FFT architecture consumes additional Block-RAMs (BRAM) and quite an amount of Xilinx-Xtreme Digital Signal Processor (DSP)/ DSP48 resources, the Power Delay Product (PDP) of the proposed FFT is excellent compared to the existing FFT architectures. The proposed multi radix mixed 2/3/5 parallel pipelined 2048 point FFT architectures exhibits very less latency of 11.382 µs at 550 MHz clock frequency compared to the existing system with the latency of 56.88 µs at 200 MHz clock frequency. Moreover, the designed FFT architecture utilizes 96 Xilinx Xtreme DSP blocks 25040 clock cycles to complete the FFT operation with an excellent throughput of 2200 MSPS with FFT computation time of 45.528 µs at the clock frequency of 550 MHz for the 4x4 MIMO- OFDM architecture. Therefore, the designed FFT provides high throughput rate in order to meet the modern wireless standard specifications. The proposed FFT architecture outperforms well in terms high throughput, low latency and better PDP with extra hardware as trade-off for both for Single FFT and for MIMO technology.

Coherent Estimation of Three Positioning Measurements for Unknown Frequency-Hopping Signals in Passive Emitter Localization

Due to the superior anti-interception performance and inherent security features, the wide applications of frequency-hopping (FH) signals bring a great challenge to the reconnaissance and monitoring of FH emitters. This paper addresses the problem of positioning measurement estimation for unknown FH signals in passive localization, considering the range migration (RM) and Doppler frequency migration (DFM) of the maneuvering target within the observation time. A coherent range difference (RD), range rate difference (RRD) and acceleration difference (AD) estimation algorithm based on scaled Fourier transform and scaled non-uniform fast Fourier transform is proposed. This method can effectively remove RM and random DFM effects regardless of varied carrier frequency and achieve the coherent estimation of RD, RRD and AD. The whole estimation process can be easily implemented by complex multiplications combined with fast Fourier transform (FFT) and inverse FFT operations without any brute-force searching procedure. Numerical experiments demonstrate that the anti-noise performance of the proposed method is superior to several representative methods and comparable to the optimal maximum likelihood estimator with a much lower computational cost.

Computationally efficient TDOA, FDOA and differential Doppler rate estimation algorithm for passive emitter localization

This paper addresses the joint time difference of arrival (TDOA), frequency difference of arrival (FDOA) and differential Doppler rate estimation problem in passive emitter localization, considering the range and Doppler frequency migrations during the observation time. A computationally efficient estimation algorithm via second-order keystone transform and Lv's distribution is proposed. This method can effectively remove two types of migrations and accomplish the parameter estimation. Cross-terms suppression ability of the proposed method is also analyzed and its characteristic indicates the applicability in the scenario of multi-targets. The whole estimation step can be fast implemented by complex multiplications, fast Fourier transform (FFT) and inverse FFT operations without any searching procedure. Extensive numerical experiments validate that with a much lower computational cost, the proposed method could achieve comparable estimation performance with the maximum likelihood estimator and outperforms the other representative algorithms.

Successive Multipath Interference Cancellation for CP-Free OFDM Systems

Traditional orthogonal frequency-division multiplexing (OFDM) systems mitigate multipath interferences with the help of a cyclic prefix (CP) appended between two adjacent OFDM blocks. The length of the CP must be made longer than channel delay spread to avoid intersymbol interference (ISI). The use of CPs degrades spectrum efficiency significantly, which is a deal price paid in all existing OFDM systems. Motivated to deal with this issue, this paper proposes a CP-free OFDM scheme with successive multipath interference cancellation (SMIC), which does not require CPs and removes ISI before fast Fourier transform (FFT) at a receiver using stored feedback equalization (SFE). The SFE operation leaves a CP gap between adjacent OFDM blocks, and the CP is regenerated with estimated signals. In this way, we convert linearly shifted OFDM blocks induced by multipath propagation back to cyclically shifted OFDM blocks for successful FFT operation. SMIC-OFDM achieves a much higher spectrum efficiency than traditional OFDM owing to the save of CPs in transmission signals. The performance of SMIC-OFDM in terms of the bit error rate, capacity, and computational complexity is compared to that of traditional OFDM to verify the effectiveness of the proposed SMIC-OFDM scheme.

Low power VLSI implementation of real fast Fourier transform with DRAM-VM-CLA

In recent years, Fast Fourier Transform (FFT) plays a vital role in signal processing application for converting time domain to frequency domain. This paper presents Real FFT architecture which is implemented in radix-2 Decimation- in-Frequency (DIF). Instead of using more number of Random Access Memory (RAM), single Dual port RAM (DRAM) is used to store the intermediate data results. In Processing Element (PE), normal multiplier and adder has been used in previous works. In this paper, Vedic Multiplier (VM) and Carry Lookahead Adder (CLA) is used for improving the Real FFT operation and it is implemented in Verilog code. Application Specified Integrated Circuits (ASIC) and Field Programmable Gate Array (FPGA) performances are evaluated for all the architectures. In DRAM-VM-CLA architecture, LUT, flip flop, slices, and frequency are improved in FPGA performance as well as area, power, and delay are improved in ASIC performance. In ASIC 180 nm technology, 81.14% of area, 45.98% of delay, and 89.77% of Area Delay Product (ADP) is minimized in DRAM-VM-CLA as well as 72.64% of area, 5.44% of delay, and 74.10% of ADP is reduced in ASIC 45 nm technology.

Coherent Integration for Radar High-Speed Maneuvering Target Based on Frequency-Domain Second-Order Phase Difference

In recent years, target detection has drawn increasing attention in the field of radar signal processing. In this paper, we address the problem of coherent integration for detecting high-speed maneuvering targets, involving range migration (RM), quadratic RM (QRM), and Doppler frequency migration (DFM) within the coherent processing interval. We propose a novel coherent integration algorithm based on the frequency-domain second-order phase difference (FD-SoPD) approach. First, we use the FD-SoPD operation to reduce the signal from three to two dimensions and simultaneously eliminate the effects of QRM and DFM, which leads to signal-to-noise ratio improvement in the velocity-acceleration domain. Next, we estimate the target motion parameters from the peak position without the need for a search procedure. We show that this algorithm can be easily implemented by using complex multiplications combined with fast Fourier transform (FFT) and inverse FFT (IFFT) operations. We perform comparisons with several representative algorithms and show that the proposed technique can be used to achieve a good trade-off between computational complexity and detection performance. We present both simulated and experimental data to demonstrate the effectiveness of the proposed method.