Fast Fourier Transform Implementation Research Articles

Fast Fourier Transform Implementation for Determining Band Gap Energy from UV–Vis Spectra as a Fresh Methodology

Fast Fourier Transform Implementation for Determining Band Gap Energy from UV–Vis Spectra as a Fresh Methodology

Respiratory Analysis with Electrocardiogram Data: Evaluation of Pan-Tompkins Algorithm and Cubic Curve Interpolation Method

Advancements in bioinstrumentation have facilitated the easier monitoring of biometric signals such as electrocardiogram (ECG) and respiration. This development is particularly crucial for the diagnosis and management of various conditions like stress and sleep disorders. Two commonly used features in heart rate variability (HRV) analysis derived from ECG data are standard deviation and serial correlation coefficients of R-R intervals (the time durations between heartbeats). The former utilizes the fundamental components of QRS complexes, while the latter is designed to extract relationships between respiration and heart rate. In the proposed methodology, R-R wave detection is performed on processed ECG data using the Pan-Tompkins algorithm, and the respiration duration for each R-R interval from respiration data is selected. Additionally, missing respiration data for selected R-R intervals is interpolated based on the interpolation method. The results of this study are compared with the standard interpolation and cubic spline interpolation models to assess the effectiveness of the proposed method and its ability to capture temporal fluctuations. Since standard interpolation fails to accurately detect respiration data from R-R intervals and cannot precisely handle missing R-R intervals in short samples, cubic spline interpolation is recommended as a replacement and its results are presented. The obtained results provide insights into the effectiveness and application of the Pan-Tompkins algorithm, FFT (fast fourier transform) implementation, and cubic spline interpolation in the selection of respiration and R-wave features. According to the findings of the study, in the analysis conducted on 2-second samples with a 1000 Hz sampling frequency created from each participant's respiratory data set, missing respiratory data were successfully reconstructed from the R-R intervals of the EKG data using standard and cubic curve interpolation methods. Upon examination of RMSE (Root mean square error) values, it was observed that for 30% of the participants, as RMSE values increased, completion counts for standard interpolation increased, while completion counts for cubic curve interpolation decreased. Conversely, when RMSE values decreased, 60% of the participants showed a decrease in completion counts for standard interpolation and an increase in completion counts for cubic curve interpolation. A 10% participant group was identified where there was no apparent relationship between RMSE values and interpolation method. This indicates that in 90% of the participants, there is a linear relationship between the study's interpolation method, RMSE values, and completion counts for missing R-R intervals.

Implementation of Fast Fourier Transform and Artificial Neural Network in Series Arc Fault Identification and Protection System on DC Bus Microgrid

A microgrid is a cluster of electrical sources and loads that are interconnected and synchronized. Microgrid operation is typically divided into two modes, isolated or connected to the grid with a single or standalone control system. In this context, it can enhance the reliability and quality of electricity supply for connected customers. When using a microgrid system, it is important to consider the risk of series arc faults. Series arc faults are sudden bursts of flames resulting from ionization of gas between two electrode gaps. These faults can occur due to manufacturing defects, installation Errors, aging, or corrosion on conductor rods, leading to imperfect connections. Detecting series arc faults in DC microgrid system operations can be challenging using standard protective devices. Failure in the protection system can pose risks of fire, electrical shock hazards, and power loss in the DC microgrid.Therefore, a device has been designed to detect series arc faults by utilizing the fast Fourier transform method and artificial neural network, which function to analyze DC signal and make decisions when faults occur by examining the average sum of current frequency values during normal and fault conditions. In this study, the average sum of current frequency values during normal conditions was found to range from 0.35437 to 0.36906 A, while during fault conditions, it ranged from 0.21450 to 0.22793 A, with an average protection identification time of 1087 ms and an ANN output accuracy of 99.98%.

Implementation of FFT in Industrial Induction Motor Monitoring via Mobile Phone

Competition in the industrial world requires companies to always improve efficiency in the production process. The use of communication technology in the monitoring process is one way to reduce effort in monitoring equipment. This study aims to create a mobile phone-based online control and monitoring system for induction motor parameters in the industry without interfering with the motor's electrical network. The monitoring system is carried out by monitoring the vibration and temperature of the induction motor using the GY-521 MPU-6050 sensor connected to the NodeMCU ESP8266 as the control device. For the data computation process to obtain rotational parameters, the Fast Fourier Transform (FFT) function is applied to transform the vibration data from the accelerometer into the frequency domain. In the data collection process, 250 data samples were captured in 1 second which were formed from vibrations of the X, Y and Z direction motors. Manual ON/OFF control of the electric motor and automatic OFF was carried out when a spike in the vibration frequency of the motor was detected. The test was carried out with four variations of rotation conditions. The test results show that the rpm speed of the motor can be obtained based on the difference in the frequency of motor vibration. This data is then sent online to observer technician via the Telegram application installed on the mobile phone device. The system performance as a whole shows quite good performance both in terms of equipment placement, data processing and delivery.

Spatial Filter for the Pseudo-spectral Implementation of Fractional Derivative Wave Equation

The viscoelasticity of the subsurface media varies spatially, and such viscoelasticity can be represented concisely by a wave equation in the form of fractional temporal derivative (FTD). We have developed a strategy for simulating seismic waves propagating through a heterogeneous viscoelastic model. The FTD is transferred to fractional spatial derivatives (FSDs), and the FSDs are implemented through the fast Fourier transform (FFT), for improving the computational efficiency. However, the FFT implementation is not rigorously applicable to the heterogeneous model. In this paper, we have reformulated the FSD wave equation by introducing a spatial-position dependent filter. This spatial filter corrects the errors that are caused by the assumption of non-heterogeneity in the FFT implementation. This formulation appropriately represents the viscoelastic effect in seismic wave propagation, leading to the improvement on the accuracy of numerical simulation.

A novel parallel prefix adder for optimized Radix-2 FFT processor

The Fast Fourier Transform (FFT) is the basic building block for DSP applications where high processing speed is the critical requirement. Resource utilization and the number of computational stages in Radix-2 FFT structure implementation can be minimized by improving the performance of utilized multiplier and adder blocks. This work proposes a hardware design of an efficient Radix-2 FFT architecture using optimized multiplier and novel Parallel prefix (PP) adder. The designed FFT architecture results in low power and area with an increase in operation speed in comparison to the existing architectures. Our proposed Radix 2 FFT implementation results in 18.218 ns (6.030 ns logic delay and 12.118 ns router delay) in comparison with 24.003 ns delay for Wallace multiplier using Kogge Stone PP adder (M1P1), 24.162 ns delay for Wallace multiplier using Brent Kung PP adder (M2P2), 24.889 ns delay for Wallace multiplier using Landner Fischer PP adder (M3P3) and 22.827 ns delay for Wallace multiplier using Han Carlson PP adder (M4P4) algorithm. The proposed adder and hence the FFT processor can be used in different applications where high speed, low power, and less area is required. The novel PP architecture results in a 20.19% improvement in comparison with other state-of-art techniques.

Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications

In this work, we proposed a novel Coordinate Rotation DIgital Computer (CORDIC) rotator algorithm that converges faster by performing radix-2,4 and 16 CORDIC iterations while maintaining the scale factor implicitly constant. A mixed-radix is used to achieve convergence faster to reduce the computational latency of the CORDIC algorithm. The main concern of the higher radix CORDIC algorithm is the compensation of a variable scale factor. To solve this problem, the Taylor series approximation of sine and cosine is proposed for a higher radix CORDIC algorithm to achieve the scaling-free rotation of the two-dimensional vector. The scaling-free rotation of the proposed CORDIC algorithm removes the read-only memory (ROM) needed to store scale factor of higher radix CORDIC algorithm. Further, the proposed CORDIC algorithm is designed in rotation mode and optimized by removing the Z datapath for the digital signal processing (DSP) applications for which the angle of rotation is known in advance. Finally, the multipath delay commutator (MDC) fast Fourier transform (FFT) algorithm is implemented with the proposed CORDIC algorithm based rotator on FPGA. The proposed design is compared with existing designs. In a comparison between the radix-16 CORDIC rotator based FFT implementation and our proposed implementation, it has been found out that implementation proposed in this article has used 17% fewer resources.

Design optimisation of multiplier‐free parallel pipelined FFT on field programmable gate array

Fast Fourier transform (FFT) is utilised to minimise the complexity of discrete Fourier transform by converting signals from frequency domain to time domain and conversely. Digital signal processing systems like image processing, general filtering, sonar, spread-spectrum communications and convolutions use this FFT operations. Radix-2 decimation in frequency (R2DIF) method is designed to execute an efficient FFT architecture in this study. Each and every state of the FFT stores the input and output the data using the R2DIF method. Also, the complex twiddle factors in FFT are replaced by the proposed uniform Montgomery algorithm. This technique simply performs the shift-add method instead of the multiplication process which also enhances the convergence of the calculation. So, the FFT implementation is done with the help of the proposed method which reduces the usage of chips in the process. Based on this approach, it performs the operation of FFT from 16 points to 1024 points and the performance of this proposed method is compared with existing approaches. Moreover, it does not require expensive dedicated functional blocks and uses only distributed logic resources. The simulation is carried out by the Xilinx platform using Verilog coding. The proposed design outperforms conventional methods in terms of less usage power and high speed.

FFT-network for bivariate Lévy option pricing

We propose a two-dimensional fast Fourier transform (FFT) network to retrieve the prices of options that depend on two Levy processes. Applications include, but are not limited to, the valuation of options on two stocks under the Levy processes, and options on a single stock under a random time-change Levy process. The proposed numerical scheme can be applied to different multivariate Levy constructions such as subordination and linear combination provided that the joint characteristic function is available. The proposed FFT-network can be thought of as a lattice approach implemented through the characteristic function. With the prevalent implementation of FFT, the network approach results in significant computational time reduction while maintaining satisfactory accuracy. Furthermore, we investigate option pricing on a single asset where the asset return and its volatility are driven by a pair of dependent Levy processes. Such a model is also called the random time-changed Levy process. Numerical examples are given to demonstrate the efficiency and accuracy of FFT-network applied to exotic and American-style options.

FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm

The fast Fourier transform (FFT) is an algorithm widely used to compute the discrete Fourier transform (DFT) in real-time digital signal processing. High-performance with fewer resources is highly desirable for any real-time application. Our proposed work presents the implementation of the radix-2 decimation-in-frequency (R2DIF) FFT algorithm based on the modified feed-forward double-path delay commutator (DDC) architecture on FPGA device. Need for a complex multiplier to carry out the multiplication of complex twiddle factors and large memory to store the twiddle factors are the main concerns for FFT implementation. Propose work aims to address these issues. In this work, a high-performance radix-16 COordinate Rotational DIgital Computer (CORDIC) algorithm based rotator is proposed to carry out the complex twiddle factor multiplication. Further, CORDIC needs only rotational angles to carry out complex multiplication, which reduces the need for large memory to store the twiddle factors. To compute the total rotation for n-bit precision, our proposed radix-16 CORDIC algorithm takes n/4 iteration as compared to n iteration of the radix-2 CORDIC algorithm. Our proposed architecture of the radix-2 decimation-in-frequency (R2DIF) algorithm is implemented on a Virtex−7 series FPGA. Further, the detailed comparison is presented between our proposed FFT implementation and other recently proposed FFT implementations. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations.

Selecting FFT Word Length for an OFDM Receiver That Supports Undersampling

In this paper, we focus on Orthogonal Frequency Division Multiplexing (OFDM) transceivers where undersampling is employed by the receiver Analog/Digital Converter (ADC) when sparse information is exchanged. Several Fast Fourier Transform (FFT) symmetry properties are exploited to allow the substitution of specific input values by others that have already been sampled by the ADC. Several architectures have been proposed in the literature for efficient FFT implementations in terms of power, speed and hardware resources. The FFT input/output values, twiddle factors, etc., are complex numbers with their real and imaginary parts being represented using fixed point format. A tradeoff has to be made between rounding error and complexity. The optimal minimum FFT word length is investigated by combining the undersampling and the rounding error. A configurable new FFT architecture has been developed in hardware description language to test the error model with various FFT sizes, word lengths and Quadrature Amplitude Modulations (QAM). A system designer can take into account the sparseness of the input data and define the desired rounding and undersampling error relation. Τhe developed error model would then predict the required word length and ADC resolution with average Root Mean Square Error (RMSE) less than 1.

A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture

Fast Fourier transform (FFT) is an essential algorithm in digital signal processing and advanced mobile communications. With the continuous development of modern technology, the area-power efficient hardware implementation of FFT has attracted a lot of attention. In this article, a novel design for FFT implementation is proposed. The number of resource-expensive multiplications in our design is decreased by a twiddle factor merging technique that reduces the hardware area. Subsequently, a common subexpression sharing scheme is applied to reuse the hardware resources to further save the hardware area. In addition, a magnitude-response aware approximation algorithm is proposed for applications where the transformation accuracy can be compromised a little bit for lesser hardware area and power dissipation. Logic synthesis shows that the proposed 16-point FFT architecture can save hardware area and power dissipation on application-specific integrated circuit (ASIC) by up to 65.7% and 53.1% compared with recently published designs. Similarly, the proposed 32-point FFT architecture achieves up to 58.8% reduction on hardware area and 60.0% reduction on power dissipation on ASIC.

FFT Implementation using Modified Booth Multiplier and CLA

In the field of digital signal and image processing the Fast Fourier Transform (FFT) is one of the rudimentary operations. Telecommunication, Automotive, Hearing devices, Voice recognition systems are some of the applications of Fast Fourier Transform. DFT is implemented using FFT which is a type of algorithm that computes DFT in a fast and efficient manner. This project concentrates on the development of the Fast Fourier Transform (FFT), based on Decimation In Time (DIT) domain, Radix2 algorithm, using VHDL as a design entity.The objective of this project is to establish an efficient design that computes FFT in a faster way. In this project FFT is implemented using modified booth multiplier and CLA and simulated on Xilinx ISE. K

Reliability analysis of different RCIED activation signal responsive jamming techniques and their comparison to active jamming

In this paper we compared the time required for the successful jamming of remote controlled improvised explosive devices activation using active and responsive jamming methods. As a representative of active jamming method we analyzed jamming signal generation using frequency sweep. For the analysis of the possible activating signal presence based on responsive jamming procedures we first supposed Fast Fourier Transform (FFT) implementation and compared its analysis rate to the rate of sweep jamming. Taking into account the current technology state, it is proved that the time required to achieve the successful jamming relied on FFT analysis may be less than in the case of active sweep jamming. After that we considered pros and cons for energy detector and matched filter detector implementation in responsive jamming. For these two detector types it is shown how to determine the number of analysis blocks to achieve approximately the same number of collected samples as in the case of FFT implementation, starting from the probabilities of false detection and miss of detection.

Double Precision Floating Point Fft Processor using Vedic Mathematics

There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.

Implementation of FFT Architecture using Various Adders

In 1965 a technique called Fast Fourier Transform (FFT) was invented to find the Fourier Transform. This paper compares three architectures, the basic architecture/ non-reduced architecture of FFT, decomposed FFT architecture without retiming and decomposed FFT architecture with retiming. In each case, the adder used will be Ripple Carry Adder (RCA) and Carry Save Adder (CSA). A fast Fourier transform (FFT) calculates the discrete Fourier transform (DFT) or the inverse (IDFT) of a sequence. Fourier analysis transforms a signal from time to frequency domain or vice versa. One of the most burgeoning use of FFT is in Orthogonal Frequency Division Multiplex (OFDM) used by most cell phones, followed by the use in image processing. The synthesis has been carried out on Xilinx ISE Design Suite 14.7. There is a decrease in delay of 0.824% in Ripple Carry Adder and 6.869% in Carry Save Adder, further the reduced architecture for both the RCA and CSA architectures shows significant area optimization (approximately 20%) from the non-reduced counterparts of the FFT implementation.

A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

This paper presents a high throughput size-configurable floating point (FP) Fast Fourier Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback (MDF) functions suitable for applications in the real-time radar imaging system. With regard to floating-point FFT design, to acquire a high throughput with restricted area and power consumptions poses as a greater challenge due to some higher degrees of complexity involved in realizing of FP operations than those fixed-point counterparts. To address the related issues, a novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2k-point FFT. To this aid, the parallel-processing twiddle factor generator and the dual addition-and-rounding fused FP arithmetic units are optimized to meet the high accuracy demand in computation and the low power budget in implementation. The proposed FP FFT processor has been designed in silicon based on SMIC's 28 nm CMOS technology with the active area of 1.39 mm2. The prototype design delivers a throughput of 4 GSample/s at 500 MHz, at a peak power consumption of 84.2 mW. Thus, the proposed design approach achieves a significant improvement in power efficiency approximately by 14 times on average over some other FP FFT processors previously reported.

Towards design and automation of a scalable split-radix FFT processor for high throughput applications

Fast Fourier Transform (FFT) is a rudimentary operation in signal processing. Modern high speed signal processing and communications standards, such as 4G LTE, 5G, Internet of Things (IoT), etc., necessitate a high throughput implementation of FFT. Moreover the FFT resolution required in aforementioned standards tends to vary with the operation mode. It is, therefore, highly desirable to have a FFT implementation that not only meets the high throughput demand but is also scalable to cater any selectable N-point FFT resolution. In this paper, our contribution is two-fold. First, we have analyzed in details the operational latency and mathematical consistency of our proposed split-radix 4/8 FFT algorithm which is comparable in latency with radix-8 algorithm but is considerably less complex for large-size FFTs. Second, we have developed a JAVA-based automation tool that generates high level implementation details and VHDL descriptions of an adaptive N-point split-radix 4/8 FFT processor. The resulting design can then be rapidly prototyped and synthesized on different hardware platforms like Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). Experimental results show that our proposed auto-generated modular design is comparable in resource usage with the hand-crafted fixed-size designs reported in the literature while providing considerable reduction in design effort and time.

DESIGN OF A HIGH-SPEED HIGH-ACCURACY 2048-POINT FFT USING SINGLE-PRECISION FLOATING-POINT ADAPTIVE CORDIC ON FPGA

In this paper, hardware design of a Fast Fourier Transform (FFT) core using Single-precision Floating-point Adaptive CORDIC is implemented on Altera Stratix IV FPGA. With FFT implementation, CORDIC is utilized for reducing the speed drawback of complex multiplication and the adaptive algorithm is proposed to decrease the iterations of conventional CORDIC. The experimental results of Adaptive CORDIC and 2048-point Radix-2 Multi-path Delay Commutator FFT designs are built and verified based on three kinds of Look-up Table that cost 16, 8 and 4 constant angles. As experimental results, there is a resource equivalence while it has a trade-off between speed performance and accuracy. In comparison, an adaptive CORDIC core based on Look-up Table of 16 constant angles, and 2048-point Radix-2 Multi-path Delay Commutator Fast Fourier Transform based on Adaptive CORDIC using Look-up Table of 16 constant angles are well responding to resource optimization, high-speed performance and high-accuracy of computations.

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of rotary machines. The complexity and cost of the associated hardware limit the use of FFT in real-time applications. In this paper, an efficient hardware architecture for FFT implementation is proposed based on the radix-2 decimation in frequency algorithm (R2DIF) and a feedback pipelined technique (FB) that allows effective sharing of storage between the input and output data at each stage of the FFT process via shift registers. The proposed design uses an optimal hybrid rotation scheme by combining the modified coordinate rotation digital computer (m-CORDIC) algorithm and a binary encoding technique based on canonical signed digit (CSD) for replacing the complex multipliers in FFT. The m-CORDIC algorithm, with an adaptive iterative monitoring process, improves the convergence of computation, whereas the CSD algorithm optimizes the multiplication of constants using a simple shift-add method. Therefore, the proposed design does not require the large memory typically entailed by existing designs to carry out twiddle factor multiplication in large-point FFT implementations, thereby reducing its area on the chip. Moreover, the proposed pipelined FFT processor uses only distributed logic resources and does not require expensive dedicated functional blocks. Experimental results show that the proposed design outperforms existing state-of-the-art approaches in speed by about 49% and in resource utilization by around 51%, while delivering the same accuracy and utilizing less chip area.