Fast Field Programmable Gate Array Research Articles

Silicon spin qubit noise characterization using real-time feedback protocols and wavelet analysis

Recently, several groups have demonstrated two-qubit gate fidelities in semiconductor spin qubit systems above 99%. Achieving this regime of fault-tolerant compatible high fidelities is nontrivial and requires exquisite stability and precise control over the different qubit parameters over an extended period of time. This motivates the search for the efficient calibration of qubit control parameters against different sources of micro- and macroscopic noise and methods for noise analysis. Here, we present several single- and two-qubit parameter feedback protocols, optimized for and implemented in the state-of-the-art fast field-programmable gate array hardware. Furthermore, we present a wavelet-based analysis on feedback data collected over a ∼9 h time frame to gain insight into the different sources of noise in the system. Scalable feedback is an outstanding challenge and the presented implementation and analysis gives insight into the benefits and drawbacks of qubit parameter feedback, as feedback related overhead increases. This work demonstrates a pathway toward robust qubit parameter feedback and systematic noise analysis, crucial for mitigation strategies toward systematic high-fidelity qubit operation compatible with quantum error correction protocols.

Field programmable gate array‐based energy‐efficient and fast epileptic seizure detection using support vector machine and quadratic discriminant analysis classifier

AbstractEpilepsy is a serious neurological disorder that results in seizures. It can be diagnosed by analyzing the brain's electrical activity using an electroencephalogram (EEG). However, the detection of seizures from massive EEG datasets is a challenging task. To address this challenge, researchers have developed several machine‐learning classifiers and feature extraction techniques for detecting seizures. This paper proposes an energy‐efficient and fast field programmable gate array (FPGA) architecture for detecting epileptic seizures using minimal computational resources. The seizure detection system uses the one Hjorth parameter (mobility) and another statistical parameter (nonlinear energy) as features and employs two efficient classifiers, quadratic discriminant analysis and linear support vector machine (LSVM), for classifying signals into seizure and nonseizure categories. The feature extractor block is connected individually to each of these classifiers. Subsequently, the performance of these two proposed models is evaluated in terms of accuracy, sensitivity, power consumption, resource utilization, and other metrics. The results demonstrate that the SVM classifier‐based model achieved the highest accuracy (99.4%) and sensitivity (98.8%) while consuming minimal dynamic power (0.057 mW) and utilizing the minimum FPGA resources. Thus, the proposed hardware system offers a reliable and energy‐efficient solution for detecting seizures in clinical and real‐time applications.

FCRoute: A Fast FPGA Connection Router Using Soft Routing-Space Pruning Algorithm

Routing is one of the most time-consuming stages in the field-programmable gate array (FPGA) design flow. Even if various attempts have been made to reduce route time, the existing work rarely focuses on improving the underlying A*-based FPGA connection router. In this article, we present a fast FPGA connection router called FCRoute based on a novel soft routing-space pruning algorithm. Within FCRoute, a routing resource priority mechanism is applied to classify the routing resource nodes into high-priority nodes and low-priority ones. On the whole, FCRoute is composed of fast maze search and backtracking process. During the fast maze search, we explore only the high-priority nodes in the routing space. In this way, a great deal of unnecessary work can be avoided. When the fast maze search fails to find the target sink, it allows the backtracking process to explore the low-priority nodes promising to be on the best path, after which a new fast maze search is called. By avoiding the exploration of the majority of low-priority nodes, FCRoute maintains runtime efficiency while ensuring global search ability. In addition, we further accelerate FCRoute with an engineering enhancement which simplifies the cost computations of nodes. Runtime and quality of results are compared with the state-of-the-art connection router in VPR 8. Experimental results show that on average FCRoute explores less than half the number of routing resource nodes, and therefore reduces runtime by 38% while enabling the quality of results. When combined with the enhancement, FCRoute achieves an average 45% reduction on runtime without sacrificing the quality of results.

Low-Latency Optical Wireless Data-Center Networks Using Nanoseconds Semiconductor-Based Wavelength Selectors and Arrayed Waveguide Grating Router

In order to meet the massively increasing requirements of big-data applications, data centers (DCs) are key infrastructures to cope with the associated demands, such as high performance, easy scalability, low cabling complexity and low power consumption. Many research efforts have been dedicated to traditional wired data center networks (DCNs). However, DCNs’ static and rigid topology based on optical cables significantly limits their flexibility, scalability, and even reconfigurability. The limitations of this wired connection can be addressed with optical wireless technology, which avoids cable complexity problems while allowing dynamic adaption and fast reconfiguration. Here, we propose and investigate a novel optical wireless data-center network (OW-DCN) architecture based on nanoseconds semiconductor optical amplifier (SOA)-based wavelength selectors and arrayed waveguide grating router (AWGR) controlled by fast field-programmable gate array (FPGA)-based switch schedulers. The full architecture, including the design, packet-switching strategy, contention solving methodology, and reconfiguration capability, is presented and demonstrated. Dynamic switch scheduling with a FPGA-based switch scheduler processing optical label and software-defined network (SDN)-based reconfiguration were experimentally confirmed. The proposed OW-DCN was also achieved with a power penalty of less than 2 dB power penalty at BER < 1 × 10−9 for a 50 Gb/s OOK transmission and packet-switching transmission.

Field‐programmable gate array‐based design for real‐time computation of ensemble empirical mode decomposition

SummaryEmpirical mode decomposition (EMD) is considered as a suitable method when the signal to be analyzed is nonlinear or nonstationary in nature. But, EMD suffers from a problem known as mode mixing. To, reduce this problem, ensemble EMD (EEMD) was proposed. In this paper, we have presented a fast field‐programmable gate array (FPGA)‐based design for EEMD. Where calculation of output can be done in a parallel manner for different realizations. The design has a comparatively less execution time, and the execution time of the proposed EEMD design is even less than some state‐of‐the‐art EMD‐based design, although the architecture of EEMD is more complex, when compared with the EMD design. In this work, we have also performed an FPGA implementation of the EMD algorithm. The root mean square error (RMSE) and the correlation values of the intrinsic mode function (IMFs) obtained from the proposed EMD and EEMD designs are compared. The proposed FPGA‐based architecture of the EEMD algorithm is designed using Verilog‐hardware description language (HDL) and implemented on a Kintex‐7 FPGA. The EEMD architecture consists of cubic Hermite spline interpolation (CHSI) and cubic spline interpolation (CSI) for the envelope generation.

Elevator controller based on implementing a random access memory in FPGA

Previous techniques of elevator controllers suffer from two main challenges: processing time, and software size. In this work these challenges have been overcame by implementing a controller random access memory (RAM) in a fast FPGA for a proto-type of two-floors elevator, as known the RAM and FPGA are fast devices. A look-up-table LUT (which is fast technique) has been proposed for this work, this LUT has represented a proposed relation between 10 and 7 lines, the states of the sensors and switches have been represented by the 10 input lines, and the commands for the motors of slide door and traction machine have been represented by the 7 output lines. The proposed LUT has been schematically realize by a (10×7) bits RAM which has been implemented in field programmable gate arrays (FPGA). The proposed system has been performed using 'ISE Design Suit' software package and FPGA Spartan6 SP-605 evaluation kit, the clock frequency of this FPGA is 200 MHz which is respectively high. The processing time and software size of the proposed controller had reached to 20ns and 3.75 MB, which they are less than that obtained from the results of previous techniques.

Fast Mapping and Updating Algorithms for a Binary CAM on FPGA

Content-addressable memories (CAMs) are used in a variety of applications, such as IP filtering, data compression, and artificial neural networks due to its high-speed lookup. Fast field-programmable gate arrays (FPGAs) are nowadays used to emulate CAMs. These CAM emulations either make use of logical resources or use memory blocks on FPGAs to emulate CAMs. However, such CAM emulation suffers from slower mapping and updating mechanisms, which results in an unacceptable response in real-time applications. The slower response in update mechanism is proportionate to the CAM depth in the schemes. In this article, fast mapping and updating algorithms for a binary CAM (FMU-BiCAM) are presented, which efficiently utilizes lookup tables, slice registers, and block random access memories (RAMs) on Xilinx FPGA to emulate faster mapping and updating CAMs. The advantage of the proposed work lies in directly applying the CAM key as an address, which helps in updating contents in memory units. CAMs in the literature exhaust the entire CAM depth in remapping the CAM words along with the updating word, which leads to higher update latency. The proposed algorithms are implemented on Xilinx Virtex-6 FPGA, and the results show that the proposed method brings latency to only two clock cycles during update.

Efficient Computation Techniques and Hardware Architectures for Unitary Transformations in Support of Quantum Algorithm Emulation

As the development of quantum computers progresses rapidly, continuous research efforts are ongoing for simulation and emulation of quantum algorithms on classical platforms. Software simulations require use of large-scale, costly, and resource-hungry supercomputers, while hardware emulators make use of fast Field-Programmable-Gate-Array (FPGA) accelerators, but are limited in accuracy and scalability. This work presents a cost-effective FPGA-based emulation platform that demonstrates improved scalability, accuracy, and throughput compared to existing FPGA-based emulators. In this work, speed and area trade-offs between different proposed emulation architectures and computation techniques are investigated. For example, stream-based computation is proposed that greatly reduces resource utilization, improves system scalability in terms of the number of emulated quantum bits, and allows for dynamically changing algorithm inputs. The proposed techniques assume that the unitary transformation of the quantum algorithm is known, and the matrix values can be pre-computed or generated dynamically. 32-bit floating-point precision is used for high accuracy and the architectures are fully pipelined to ensure high throughput. As case studies for emulation, the quantum Fourier transform and Grover’s search algorithms are investigated and quantum circuits for multi-pattern Grover’s search are also proposed. Experimental evaluation and analysis of the emulation architectures and computation techniques are provided for the investigated quantum algorithms. The emulation framework is prototyped on a high-performance reconfigurable computing (HPRC) system and the results show quantitative improvement over existing FPGA-based emulators.

Fast Frame Synchronization Design and FPGA Implementation in SF-BOTDA

To address the issues of high time consumption of frame synchronization involved in a scanning-free Brillouin optical time-domain analysis (SF-BOTDA) system, a fast frame synchronization algorithm based on incremental updating was proposed. In comparison to the standard frame synchronization algorithm, the proposed one significantly reduced the processing time required for the BOTDA system frame synchronization by about 98%. In addition, to further accelerate the real-time performance of frame synchronization, a field programmable gate array (FPGA) hardware implementation architecture based on parallel processing and pipelining mechanisms was also proposed. Compared with the software implementation, it further raised the processing speed by 13.41 times. The proposed approach could lay a foundation for the BOTDA system in the field with the associated high real-time requirements.

Real-time control of the deposition location of ECRH in the LHD

A real-time control system for the deposition location of electron cyclotron resonance heating (ECRH) has been newly developed and applied to experiments on the Large Helical Device (LHD). Appropriate settings for a steerable launcher for ECRH were obtained by evaluating the deposition location and the absorption power for various electron density profiles using a ray-tracing code. The real-time deposition location control system adjusts launcher settings to improve the first-pass absorption of the refracted electron cyclotron wave, based on the ray-tracing calculations. The control system was designed to use a fast field programmable gate array (FPGA). The FPGA processes in real time the calculation of characteristic parameters regarding the density profile and the calculation of target positions requested for rotation control of a steering mirror of the launcher. The real-time deposition location control during ECRH discharges on the LHD functioned successfully in maintaining the absorption power higher than that without the control, which resulted from the deposition location maintained in the plasma core region.

Fault location estimation for series-compensated double-circuit transmission line using EWT and weighted RVFLN

In this paper, empirical Wavelet transform (EWT), Hilbert transform (HT) and weighted random vector functional link network (WRVFLN) are integrated for fault detection, classification, and location estimation in a series capacitor compensated double circuit transmission line (SCCDCTL). The full cycle current signals from the point of fault inception are decomposed using EWT to extract three band-limited modes (BLMs). The four efficacious instantaneous features namely energy, Shannon entropy, the standard deviation of the magnitude, and crest factor are computed from the Hilbert transformed array of the BLMs to construct the feature vector. A diagonal matrix W is computed from the zero sequence current of original six current signals as a weighting factor to categorize the ground fault accurately. Numerous faults are generated with a wide variation of the system conditions such as fault resistance, fault inception angle, fault distance, percentage compensation level, source impedance, line parameters, load angle, and inter-circuit fault in MATLAB/Simulink environments. An efficient WRVFLN computational intelligence technique is proposed to recognize and estimate the location of the faults by taking the extracted suitable feature vector with weight factor as an input. The performances of WRVFLN are compared with the recently developed advanced classifiers such as least-square support vector machine (LSSVM) and extreme learning machine (ELM) in the MATLAB interface. The lesser computational complexity, faster learning speed, superior classification accuracy, accurate fault location estimation, and short event detection time prove that the proposed EWTHT–WRVFLN method can be implemented in the real power system for online fault diagnosis. Finally, the developed system architecture is implemented on the reconfigurable digital field programmable gate array (FPGA) in ISE design suite 14.5 environments to verify the cogency of the proposed method in real-time. The feasibility of the proposed method is tested and validated by using the fast FPGA digital circuitry in a loop.

Design of Reconfigurable SDR Platform for Antenna Selection Aided MIMO Communication System

In recent years, antenna selection (AS) has become one of the most popular research topics for massive multiple-input multiple-output (MIMO) system due to its capability of reducing the number of radio frequency chains utilized for MIMO communications, while remaining the MIMO advantages, such as increased bandwidth efficiency and reliability. In this paper, an efficient norm-based AS (NBAS) algorithm is investigated and implemented in the software defined radio (SDR) MIMO communication platform, which consists of field-programmable gate arrays (FPGAs). Owing to the high freedom and fast reconfigurable FPGA hardware, the SDR MIMO communication platform is capable of developing prototype of NBAS-aided MIMO system. More specifically, the implemented NBAS aided SDR MIMO system is capable of achieving uplink communication from users to the base station via time division duplex (TDD). A time-varying fading channel generation model is designed for SDR MIMO platform to enrich our experimental results. Additionally, a novel multiplexer (MUX) circuit module is designed and implemented to enhance the hardware performance of the FPGA in term of delay and resource usage. More specifically, the Results show that by implementing the low-complexity NBAS, the channel capacity performance of the SDR MIMO system may be significantly improved by around 15%. It is also showed that our proposed optimized MUX circuit intellectual property may reduce the critical path delay by about 2:16 ns, and save at lease 3% hardware resources in SDR FPGA.

High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators

System accelerators (ACCs) improve performance and break power and utilization walls. They can be implemented by fixed-function hard macros or reconfigurable logic such as field-programmable gate arrays (FPGAs). For systems running various applications, dynamic reconfigurable ACCs offer a very attractive feature; however, the reconfiguration time is an unavoidable overhead. This paper proposes high-performance architecture with fast dynamic reconfigurable FPGA ACCs (F-RACCs) based on a novel bitstream reprogramming method, which is feasible by using emerging technologies. The architecture includes CPU cores, caches, memories, ACCs, and network-on-chips. A portion of the computing tasks can be offloaded from CPUs to ACCs to improve performance. The ACCs can be reprogrammed rapidly to accommodate various functions required by wide spectrum of applications. The performance is evaluated by platform for ACC-rich architectural design and exploration, a gem5-based cycle-accurate full-system simulation platform. The 11 benchmark applications from different domains are evaluated. Comparing with systems using conventional FPGA ACCs partially configured using fastest configuration speed; this architecture improves system performance on all applications and achieves maximum $1.31\times $ and $2.82\times $ speedup using 1 and 12 ACC instances, respectively. It achieves maximum speedup of $94.93\times $ with one and $565.12\times $ with 12 F-RACCs over CPU software path with no ACCs.

Real-time control of electron cyclotron wave polarization in the LHD

Peripheral plasma with finite electron density gradients and finite magnetic shear is known to affect polarization of electron cyclotron (EC) waves. Calculation of the ratio between the ordinary (O) mode and the extraordinary (X) mode, integrated in the ray-tracing code developed for EC heated plasmas in the Large Helical Device (LHD), enables the search for the optimum EC wave polarization in order to excite the pure O/X mode at the EC resonance layer. The real-time control system of the incident polarization was developed for maximum single-pass absorption of EC waves, based on the dependence of optimum EC wave polarization on peripheral density profiles. The polarization control system is equipped with a fast field programmable gate array, which processes in real time the calculation of the peripheral electron density profile and the optimum EC wave polarization for motion control of the polarization rotator and the elliptical polarizer on the transmission line. The real-time control in LHD experiments functioned properly in maintaining the absorbed power of the EC wave higher than that without the control, demonstrating that the purer heating mode was successfully excited.

Fast FPGA Implementation for Computing the Pixel Purity Index of Hyperspectral Images

The pixel purity index (PPI) algorithm is one of the most popular endmember extraction algorithms employed in hyperspectral image unmixing, which is too time-consuming to obtain real-time analysis in remote sensing applications. The fast field programmable gate array (FPGA) implementation for computing the PPI is proposed in this reported work. The parallel strategy by skewers consumes lower I/O bandwidth and on-chip memory capacity, and the Xilinx Vivado high-level-synthesis (HLS) tool speeds up our architecture design and implementation. The overall design can be simple to implement, and makes the FPGA hardware appealing for on-board hyperspectral unmixing.

Fast FPGA prototyping for real-time image processing with very high-level synthesis

Programming in high abstraction level can facilitate the development of digital signal processing systems. In the recent 20 years, high-level synthesis (HLS) has made significantly progress. This technique greatly benefits the R&D productivity of the Field Programmable Gate Array (FPGA) developments and helps for adding to the maintainability of the products by automating the C-to-RTL (register transfer language) conversion. However, due to the high complexity and computational intensity, image processing algorithms usually necessitate a higher abstraction environment than C-synthesis, and the current HLS tools do not have the ability of this kind. This paper presents a conception of very high-level synthesis method which allows fast prototyping and verifying the FPGA-based image processing designs in the MATLAB environment. We build a heterogeneous development flow by using currently available tool kits for verifying the proposed approach and evaluated it within two real-life applications. Experiment results demonstrate that it can effectively reduce the complexity of the development by automatically synthesizing the algorithm behavior from the user level into the low register transfer level and give play to the advantages of FPGA related to the other devices.

Processing optimization with parallel computing for the J-PET scanner

Abstract The Jagiellonian Positron Emission Tomograph (J-PET) collaboration is developing a prototype time of flight (TOF)-positron emission tomograph (PET) detector based on long polymer scintillators. This novel approach exploits the excellent time properties of the plastic scintillators, which permit very precise time measurements. The very fast field programmable gate array (FPGA)-based front-end electronics and the data acquisition system, as well as low- and high-level reconstruction algorithms were specially developed to be used with the J-PET scanner. The TOF-PET data processing and reconstruction are time and resource demanding operations, especially in the case of a large acceptance detector that works in triggerless data acquisition mode. In this article, we discuss the parallel computing methods applied to optimize the data processing for the J-PET detector. We begin with general concepts of parallel computing and then we discuss several applications of those techniques in the J-PET data processing.

Finite-State-Machine Overlay Architectures for Fast FPGA Compilation and Application Portability

Despite significant advantages, wider usage of field-programmable gate arrays (FPGAs) has been limited by lengthy compilation and a lack of portability. Virtual-architecture overlays have partially addressed these problems, but previous work focuses mainly on heavily pipelined applications with minimal control requirements. We expand previous work by enabling more flexible control via overlay architectures for finite-state machines. Although not appropriate for control-intensive circuits, the presented architectures reduced compilation times of control changes in a convolution case study from 7 hours to less than 1 second, with no performance overhead and an area overhead of 0.2%.

A Development and Testing Instrumentation for GPS Software Defined Radio With Fast FPGA Prototyping Support

The modernization of global positioning systems (GPS) boosts the development of civil and military applications as accuracy and coverage of receivers continually improve. Recently, software defined radio (SDR) approach for GPS receivers (GPS-SDR) gained attention because of its flexibility for multimode operations in different environments. The SDR receiver developers continually advance algorithmic and/or hardware accelerator solutions. However, they need fast prototyping and testing instrumentation to refine and evaluate high performance multimode receivers. This paper presents a feasibility study of fast prototyping of the GPS receiver accelerators using graphical user interface environments. It also describes a testbed with integrated RF front-ends, GPS simulator, receiver, and assistance support. Particularly, a novel host-target codesign solution is demonstrated using a field programmable gate array (FPGA) peripheral and LabVIEW FPGA tool for a case study of a GPS acquisition module. Distributing tasks between the FPGA target and the personal computer host achieves a high performance solution. The fast prototyped solution is compared with a conventional FPGA and state-of-the-art implementations.

Combined Architecture/Algorithm Approach to Fast FPGA Routing

We propose a new field-programmable gate array (FPGA) routing approach, which, when combined with a low-cost architecture change, results in a 40% reduction in router runtime, at the cost of a 6% area overhead and with no increase in critical path delay. Our approach begins with PathFinder-style routing, which we run on a coarsened representation of the routing architecture. This leads to fast generation of a partial routing solution where the signals are assigned to groups of wire segments rather than individual wire segments. A Boolean satisfiability (SAT)-based stage follows, generating a legal routing solution from the partial solution. We explore approximately 165 000 FPGA switch block architectures, showing that the choice of the architecture has a significant impact on the complexity of the SAT formulation, and by extension, on routing runtime. Our approach points to a new research direction, namely, reducing FPGA computer-aided design runtime by exploring FPGA architectures and algorithms together.