Fast Erase Speed Research Articles

Research Progress in Dielectric-Layer Material Systems of Memristors

With the rapid growth of data storage, traditional von Neumann architectures and silicon-based storage computing technologies will reach their limits and fail to meet the storage requirements of ultra-small size, ultra-high density, and memory computing. Memristors have become a strong competitor in next generation memory technology because of their advantages such as simple device structure, fast erase speed, low power consumption, compatibility with CMOS technology, and easy 3D integration. The resistive medium layer is the key to achieving resistive performance; hence, research on memristors mainly focuses on the resistive medium layer. This paper begins by elucidating the fundamental concepts, structures, and resistive-switching mechanisms of memristors, followed by a comprehensive review of how different resistive storage materials impact memristor performance. The categories of memristors, the effects of different resistive materials on memristors, and the issues are described in detail. Finally, a summary of this article is provided, along with future prospects for memristors and the remaining issues in the large-scale industrialization of memristors.

Innovative Structure to Improve Erase Speed in 3-D nand Flash Memory With Cell-on-Peri (COP) Applied

In this article, we propose silicon-nitride-pillar (SNP) and silicon-pillar (SP) structures that can be applied to a COP structure, which is the mainstay of the recent 3-D nand flash structure, by applying the IGZO-nitride-pillar (INP) and IGZO-pillar (IP) structures that showed very good erase performance announced in previous studies and verify them through device simulation. The proposed structure can supply holes through pillars formed by epitaxial growth in the P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> crystal silicon subregion, which is generally used in the existing semiconductor manufacturing process. As a result of simulation, the proposed structure showed a fast erase speed of 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> , and the SNP structure could prevent breakdown by appropriately controlling the thickness of the silicon nitride barrier. In addition, the SP structure with the silicon nitride barrier removed was able to maintain a fast erase speed even when the thickness of the pillar was reduced to 5 nm. Therefore, it was confirmed that the proposed structure can operate more than 100 times faster than the existing GIDL erasing structure if proper structure and operating conditions are secured.

Floating Filler (FF) in an Indium Gallium Zinc Oxide (IGZO) Channel Improves the Erase Performance of Vertical Channel NAND Flash with a Cell-on-Peri (COP) Structure

In this study, we developed a V-NAND with an improved IGZO-P type (IP) floating filler (FF) structure based on an IGZO channel verified in previous studies and demonstrated that it has a very fast erase speed through device simulation. The proposed FF structure can supply holes generated through the Gate-Induced Drain Leakage (GIDL) phenomenon in the upper polysilicon string select line (SSL) channel to the IGZO channel through a P-type filler, and the structure proposed by this operation shows a very fast erase speed of 4 μs. A fast erase speed was achieved because the filler adjacent to the IGZO channel, like IP structures in previous studies, functioned as a path through which electrons emitted from the charge storage layer moved easily, rather than simply supplying holes. This assumption was confirmed by assessing the change in electron density of the channel during the erase operation. Next, we investigated the optimum conditions for leakage current reduction through various condition changes of the lower ground select line (GSL) gate in the proposed structure. We confirmed that the leakage current of the proposed structure can be minimized by changing the number of lower GSL gates, changing the length of the GSL channel, and/or changing the work function of the GSL gate material. We obtained a leakage current of 10−17 A when the GSL channel was 480 nm long with six GSL gates, each with a length of 40 nm. The work function of the gates was 4.96 eV.

Nonvolatile memory based on redox-active ruthenium molecular monolayers

A monolayer of diruthenium molecules was self-assembled onto the silicon oxide surface in a semiconductor capacitor structure with a “click” reaction for nonvolatile memory applications. The attachment of the active molecular monolayer was verified by x-ray photoelectron spectroscopy. The prototypical capacitor memory devices in this work employed a metal/oxide/molecule/oxide/Si structure. With the intrinsic redox-active charge-storage properties of diruthenium molecules, these capacitor memory devices exhibited fast Program and Erase speed, excellent endurance performance with negligible degradation of the memory window after 105 program/erase cycles, and very good 10-year memory retention. These experimental results indicate that the redox-active ruthenium molecular memory is very promising for use in nonvolatile memory applications.

Resistive switching characteristics and resistive switching mechanism of Au/TiO2/FTO memristor

Resistance random access memory is regarded as one of the most promising candidates for the future nonvolatile memory applications due to its good endurance, high storage density, fast erase speed and low power consumption. As one of the most important transition-metal oxides, the anatase TiO2 has received intense attention due to its inexpensive cost, strong optical absorption, favorable band edge positions and superior chemical stability. In the last decade, the nanometer-sized TiO2 has been shown to exhibit a wide range of electrical and optical properties, such as nanoscale electronics and optoelectronics, which rely mainly on the unique size and shape. Recently, various anatase TiO2 based devices such as the anatase TiO2 nanotube based memristor and the anatase TiO2 nano-film based memristor have been intensively studied due to their nonvolatile resistive switching performances. Furthermore, many conduction mechanisms have been used to elucidate the resistive switching behaviors of the anatase TiO2 based devices. However, the direct growth of anatase TiO2 nanowire arrays (NWAs) on the FTO substrate is still a challenge since there exists a large lattice mismatch of about 19% between the anatase TiO2 NWAs and the FTO substrate. Moreover, the Au/TiO2/FTO based device has not been reported and the resistive switching mechanism of the anatase TiO2 NWAs based memristor is still unclear. In this work, the anatase TiO2 NWAs with (101) preferred orientation are successfully grown on the FTO substrate by a facile one-step hydrothermal process. The resistive switching characteristics and resistive switching mechanism of the as-fabricated Au/TiO2/FTO memristor are investigated systemically. The result indicates that the Au/TiO2/FTO memristor exhibits nonvolatile bipolar resistive switching behavior. Meanwhile, the resistance ratio between high resistance state and low resistance state exceeds 20 at 0.1 V, which can be maintained over 103 s without significant degradation. In addition, the conduction mechanism of the low resistance state is governed by the ohmic conduction mechanism, while the trap-controlled space charge limited current conduction mechanism dominates the high resistance state. The resistive switching model of the Au/TiO2/FTO memristor is developed, and the resistive switching mechanism could be attributed to the formation and rupture of the conductive filaments relating to the localized oxygen vacancies. It demonstrates that the Au/TiO2/FTO memristor may be a potential candidate for the future nonvolatile memory applications.

Effects of annealing on CeO2-based flash memories

In this study, CeO2 was used as a trapping layer in metal oxide high-K-oxide-Si (MOHOS)-type memory devices. This trapping layer underwent annealing to enhance memory performance. Multiple material analyses indicate that annealing enables enhanced crystallization and suppresses silicate formation. MOHOS-type flash memory devices incorporating a CeO2 charge trapping layer annealed at 950 °C exhibited a large memory window of 4.7 V, as well as a fast program and erase speed. Our research indicates that MOHOS-type memory devices utilizing CeO2 show great promise for future industrial flash memory applications.

Pillar Type Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory Cells with Modulated Tunneling Oxide

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of <TEX>$N_2$</TEX> ion implantation (<TEX>$N_2$</TEX> I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage (<TEX>$V_{\tau}$</TEX>) of 0.13 V, and a higher <TEX>$g_{m.max}$</TEX> of 18.6 <TEX>${\mu}A/V$</TEX> and mobility of 27.02 <TEX>$cm^2/Vs$</TEX> than the conventional and <TEX>$N_2$</TEX> I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and <TEX>$N_2$</TEX> I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.

Device characteristics of HfON charge-trap layer nonvolatile memory

The authors studied the device characteristics of thin HfON charge-trap layer nonvolatile memory in a TaN/Al2O3/HfON/SiO2/p-Si structure. A large memory window and fast erase speed, as well as good retention time, were achieved by using the NH3 nitridation technique to incorporate nitrogen into the thin HfO2 layer, which causes a high electron-trap density in the HfON layer. The higher dielectric constant of the HfON charge-trap layer induces a higher electric field in the tunneling oxide at the same voltage compared to non-nitrided films and, thus, creates a high Fowler–Nordheim tunneling current to increase the erase and programming speed. The trap level energy in the HfON layer was calculated by using an amphoteric model.

Memory effects based on random networks of single-walled carbon nanotubes

We have fabricated memory devices based on random networks of single-walledcarbon nanotubes (SWNTs) on a glass substrate. The characteristics ofthe nonvolatile memory were investigated as a function of gate voltage,pulse time, and temperature. The program/erase window was greater thanapproximately 3.2 V. The gate voltage sensitivity of the erase speed was greater (∼1.9 times) than that of the program speed. The activation energy was about 0.273 eV. Themechanism could be explained from the polarization of water molecules, and may providean important insight into the program/erase operation of memory devices. We have alsodiscussed a fast erase speed due to a work function difference and oxide trapped charges.

Investigations on the Impact of the Parasitic Bottom Transistor in Gate-All-Around Silicon Nanowire SONOS Memory Cells Fabricated on Bulk Si Substrate

Gate-all-around (GAA) Si nanowire SONOS memory cells (SNWMs) have been fabricated on Si substrate using fully epi-free compatible CMOS technology. A parasitic bottom SONOS memory (PBM) was formed when the SNWM was fabricated on bulk Si substrate. The impact of the PBM on the performance of the SNWM is investigated in this paper. The PBM shows a slower program speed, a faster erase speed, and worse retention characteristics than the SNWM. Therefore, the PBM severely degrades the performance of the SNWM due to its slower program speed and worse retention characteristics, and should be carefully controlled for the SNWM based on bulk Si substrate.

NAND 전하트랩 플래시메모리를 위한 p채널 SONOS 트랜지스터의 특성

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

Reliability and Processing Effects of Bandgap-Engineered SONOS (BE-SONOS) Flash Memory and Study of the Gate-Stack Scaling Capability

In this paper, the reliability properties of bandgap-engineered SONOS (BE-SONOS) devices with various processing methods are extensively studied. BE-SONOS employs a multilayer O1/N1/O2/N2/O3 stack, where O1/N1/O2 serves as a bandgap-engineered tunneling barrier that provides an efficient hole-tunneling erase but eliminates the direct-tunneling leakage. BE-SONOS can overcome the fundamental limitation of the conventional SONOS, for which fast erase speed and good data retention cannot be simultaneously achieved. In this paper, a comprehensive understanding of BE-SONOS reliability is reported, including the processing effects of the critical ONO barrier (O1/N1/O2), the trapping layer (N2), and the top blocking oxide (O3). Moreover, the capability of dielectric scaling is also evaluated. Lower P/E voltages, good P/E cycling endurance, and data retention are maintained when N2 and O3 are further scaled to 60 . The results in this paper provide design and processing guidelines for optimizing the performance and reliability of BE-SONOS flash memory devices.

A novel high-/spl kappa/ SONOS memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si structure for fast speed and long retention operation

A novel high-/spl kappa/ silicon-oxide-nitride-oxide-silicon (SONOS)-type memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si (MATHS) structure is reported for the first time. Such MATHS devices can keep the advantages of our previously reported TaN/HfO/sub 2//Ta/sub 2/O/sub 5//HfO/sub 2//Si device structure to obtain a better tradeoff between long retention and fast programming as compared to traditional SONOS devices. While at the same time by replacing hafnium oxide (HfO/sub 2/) with aluminum oxide (Al/sub 2/O/sub 3/) for the top blocking layer, better blocking efficiency can be achieved due to Al/sub 2/O/sub 3/'s much larger barrier height, resulting in greatly improved memory window and faster programming. The fabricated devices exhibit a fast program and erase speed, excellent ten-year retention and superior endurance up to 10/sup 5/ stress cycles at a tunnel oxide of only 9.5 /spl Aring/ equivalent oxide thickness.

Charge-trapping device structure of SiO2∕SiN∕high-k dielectric Al2O3 for high-density flash memory

We present a device structure of SiO2∕SiN∕Al2O3 (SANOS). The use of a high-k dielectric material, specially Al2O3, in the blocking oxide concentrates the electric fields across the tunnel oxide and SiN, and releases it across the blocking oxide under program and erase mode. This effect leads to lower program and erase voltage as well as faster erase speed than the conventional SiO2∕SiN∕SiO2 (SONOS) device. Moreover, it is shown that the fast erase operation is performed even at a thicker tunnel oxide over 30Å where the hole direct tunneling current through the tunnel oxide is reduced significantly and thus the SANOS device has the excellent bake retention.