Fast Dynamic Voltage Research Articles

Fast dynamic DC-link voltage control strategy for dual three-phase PM-assisted synchronous reluctance starter/generator system

Fast dynamic DC-link voltage control strategy for dual three-phase PM-assisted synchronous reluctance starter/generator system

A Sub-nW 93% Peak Efficiency Buck Converter With Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control

This article presents a highly efficient buck converter with sub-nW quiescent power and wide dynamic range for ultra-low-power (ULP) Internet-of-Things (IoT) systems-on-chip (SoCs). To optimize the SoC power consumption and performance, this buck converter supports fast dynamic voltage and frequency scaling (DVFS) and fast load-transient response (FLTR) using an asynchronous control scheme. To achieve robust and high-efficiency power delivery over process, voltage, and temperature variations, an adaptive deadtime controller (ADTC) is proposed with minimized area and power overhead. The power stage and gate drivers are optimized by a length split technique and a strong-up weak-down (SuWd) scheme to achieve low quiescent power. In addition, the buck converter is fully self-contained with a bias generator (BG), clock, and power-on-reset (PoR) integrated on-chip. Fabricated in 65-nm CMOS, measurement results show that the buck converter achieves 802-pW quiescent power and 93% peak efficiency at 1.5-V input voltage. The measured dynamic range is from 0.5 to 2.75 mW, which is over six orders of magnitude. The measured voltage droop is 56 mV for a 45-nA-to-1-mA load current step and DVFS up- and down-tracking takes 10.57 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$19.81~\mu \text{s}$ </tex-math></inline-formula> for an 88- and 92-mV reference step, respectively. This sub-nW buck converter integrates fast DVFS and FLTR features with a wide dynamic range making it suitable for ULP IoT applications.

System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System

Despite being employed in numerous efforts to improve power delivery efficiency, the integrated voltage regulator (IVR) approach has yet to be evaluated rigorously and quantitatively in a full power delivery system (PDS) setting. To fulfill this need, we present a system-level modeling and design space exploration framework called Ivory for IVR-assisted power delivery systems. Using a novel modeling methodology, it can accurately estimate power delivery efficiency, static performance characteristics, and dynamic transient responses under different load variations and external voltage/frequency scaling conditions. We validate the model over a wide range of IVR topologies with silicon measurement and SPICE simulation. Finally, we present two case studies using architecture-level performance and power simulators. The first case study focuses on optimal PDS design for multi-core systems, which achieves 8.6% power efficiency improvement over conventional off-chip voltage regulator module– (VRM) based PDS. The second case study explores the design tradeoffs for IVR-assisted PDSs in CPU and GPU systems with fast per-core dynamic voltage and frequency scaling (DVFS). We find 2 μs to be the optimal DVFS timescale, which not only reaps energy benefits (12.5% improvement in CPU and 50.0% improvement in GPU) but also avoids costly IVR overheads.

A Modified RC Snubber With Coupled Inductor for Active Voltage Balancing of Series-Connected SiC MOSFETs

Series connection of SiC power MOSFET is an attractive approach to expand the blocking voltage of SiC devices, whereas the dynamic voltage balancing among the series-connected devices is the most critical challenge of the technique. In this article, a simple, fast, and cost-effective dynamic voltage balancing circuit of the series-connected SiC MOSFETs is proposed to suppress the voltage imbalance among the devices. The proposed circuit is composed of a resistor-capacitor (RC) snubber with a coupled inductor to effectively sense the voltage imbalance and add a compensated signal to the gate driving voltage. In the article, the operation principle of the proposed method is described in detail and the parameter selection of the circuit is given. Then the optimized layout of the circuit in a typical half-bridge SiC power module is proposed to reduce the stray parameters introduced by the coupled inductor effectively. The proposed method is verified by experiments under different conditions. Compared with a purely RC snubber balancing strategy, the capacitor can be significantly reduced. Since only passive components are required in the feedback loop, the proposed method demonstrates a reliable and straightforward approach to achieve equal voltage sharing of the series-connected devices.

Fast dynamic voltage security margin estimation: concept and development

This paper develops a machine learning-based method for fast estimation of the dynamic voltage security margin (DVSM). The DVSM can incorporate the dynamic system response following a disturbance and it generally provides a better measure of security than the more commonly used static voltage security margin (VSM). Using the concept of transient P-V curves, the paper first establishes and visualizes the circumstances when the DVSM is to prefer to the static VSM. To overcome the computational difficulties in estimating the DVSM, the paper proposes a method based on training two separate neural networks on a data set composed of combinations of different operating conditions and contingency scenarios generated using time-domain simulations. The trained neural networks are used to improve the search algorithm and significantly increase the computational efficiency in estimating the DVSM. The machine learning-based approach is thus applied to support the estimation of the DVSM, while the actual margin is validated using time-domain simulations. The proposed method was tested on the Nordic32 test system and the number of time-domain simulations was possible to reduce with approximately 70 %, allowing system operators to perform the estimations in near real-time.

A robust FACTS based fuzzy control scheme for dynamic stabilization of generator station

Abstract The paper presents a Flexible Alternating Current Transmission Systems (FACTS) based dynamic stabilization scheme using a modified series–parallel switched filter compensation (MSPFC). The proposed dynamic scheme is controlled by an Incremental Fuzzy Logic controller (MIFLC) to ensure fast response dynamic voltage stabilization and efficient energy utilization. The MIFLC employs a multi loop dynamic error driven time-descaled regulation to ensure the fast response of the dynamic controller. A second Weighted Modified PID controller with fixed gains is assessed with the proposed MIFLC controller. The modified control schemes are validated under normal and fault operating situations to ensure fast dynamic control, ac power quality, feeder loss reduction, efficient energy utilization and dynamic AC voltage stabilization regulation. The performance of the proposed controllers is assessed using statistical studies and qualitative comparison that prove the high ability of the proposed MIFLC compared with modified PID controller.

FOPAC: Flexible On-Chip Power and Clock

A novel flexible on-chip power and clock ( FOPAC ) generation and distribution circuit is proposed to enable fast dynamic voltage and frequency scaling (DVFS). FOPAC utilizes resonant rotary clocks (ReRoCs) along with multi-phase voltage regulators (MPVR) for the clock and power generation and distribution. The locally distributed ReRoCs provide the required clock phases to the MPVR, and the MPVR provides the required voltage levels to the ReRoC, providing spatial and temporal flexibility for fast DVFS. The ReRoC and MPVR share the on-chip fly capacitor of the switched capacitor voltage regulators to achieve greater frequency scaling at run-time while reducing the overhead. The FOPAC architecture is evaluated on industrial designs demonstrating a <2 ns DVFS switching time.

Distributed Pass Gates in Power Delivery Systems With Digital Low-Dropout Regulators

On-chip digital low-dropout (LDO) regulators enable fast dynamic voltage scaling, reducing power consumption. Integrating these regulators into a highly resistive environment has complicated the design of power delivery systems. With the increasing sensitivity of complex integrated systems to power noise, effective approaches to distribute on-chip LDOs are needed due to the limited metal resources. In this article, a methodology is proposed to distribute the pass gates of a system of on-chip digital LDOs. The distribution of the pass gates considers the location of the load currents to reduce voltage variations across the power grid. The proposed pass gate distribution topology reduces the maximum voltage variations across the grid, on average, by two to three times under nonuniform load distributions.

Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators

Low-dropout (LDO) voltage regulators have become prominent elements of on-chip power delivery systems due to the increasing importance of separate voltage domains, fast dynamic voltage scaling, and the need for high-quality power. As the number of LDOs sharing a common power network increases, the stability of the power grid can degrade if the resonance frequency due to the off-chip parasitic impedances is not sufficiently separated from the unity gain frequency of the regulator. In this paper, this source of instability in power delivery networks, consisting of multiple LDO regulators with a balanced load, is described. The effect of the number of LDOs on the resonance frequency of the power delivery network is evaluated to determine the stability of the system when the LDOs operate under similar load conditions.

Dynamic Power Management for Neuromorphic Many-Core Systems

This paper presents a dynamic power management architecture for neuromorphic many-core systems, such as SpiNNaker. A fast dynamic voltage and frequency scaling (DVFS) technique is presented which allows the processing elements (PEs) to change their supply voltage and clock frequency individually and autonomously within less than 100 ns. This is employed by the neuromorphic simulation software flow, which defines the performance level (PL) of the PE based on the actual workload within each simulation cycle. A test chip in 28-nm SLP CMOS technology has been implemented. It includes four PEs which can be scaled from 0.7 to 1.0 V with frequencies from 125 to 500 MHz at three distinct PLs. By measurement of three neuromorphic benchmarks, it is shown that the total PE power consumption can be reduced by 75%, with 80% baseline power reduction and a 50% reduction of energy per neuron and synapse computation, all while maintaining temporary peak system performance to achieve biological real-time operation of the system. A numerical model of this power management model is derived which allows DVFS architecture exploration for neuromorphics. The proposed technique is to be used for the second-generation SpiNNaker neuromorphic many-core system.

A Quasi-V2 Hysteretic Buck Converter With Adaptive COT Control for Fast DVS and Load-Transient Response in RF Applications

This brief proposes a buck converter with adaptive constant on time (ACOT) control, including transient-enhanced technique for fast dynamic voltage scaling (DVS) and load-transient response in RF applications. The proposed ACOT control achieves high performance in DVS tracking response to shorten up-tracking time and down-tracking time. Moreover, the high bandwidth transient-enhanced technique in ACOT control improves load-transient response suffering from low bandwidth compensation loop. In addition, the proposed buck converter operates at 2.5 MHz for high power density and 90.1% peak efficiency. This brief is implemented by TSMC 0.18 $\mu \text{m}$ 1P6M CMOS technology with a chip area 1.81 mm2. Measurement results achieve that the output voltage have both 0.6 $\mu \text{s}$ and 0.6 $\mu \text{s}$ recovery time in 600 mA step-up load and 600 mA step-down load, respectively. For 0.6 V step, the output voltage have both 2 $\mu \text{s}$ in up-tracking time and down-tracking time.

Disturbance-Rejection-Based Model Predictive Control: Flexible-Mode Design With a Modulator for Three-Phase Inverters

This paper aims to investigate a disturbance-rejection-based model predictive control (MPC) with two flexible modes (i.e., unconstrained mode and constrained mode) for three-phase inverters with an $LC$ filter. A disturbance observer (DOB) is designed to both simplify the prediction model and achieve the robustness against uncertain parameters. First, the unconstrained mode is designed with a simple horizon-one MPC control law to precisely regulate the output voltage in the steady state. Next, the constrained mode is designed with long-horizon MPC to quickly drive the system to the unconstrained mode by further optimizing the modulation stage. Also, the proposed MPC ensures the robustness and optimality in all operating modes. Especially, the overall closed-loop stability with DOB dynamics is proven by using Lyapunov function. Unlike other MPC methods, the long-horizon MPC in the constrained mode is specialized by finite switching sequences of the sector-based space vector modulation. Comparative studies with the conventional linear quadratic regulator are conducted on a prototype test bed with a TI TMS320F28335 DSP. Then, the proposed MPC method verifies fast dynamic response and advanced voltage regulation (i.e., small steady-state errors and low total harmonic distortion) under various load conditions and uncertain parameters.

A Multiphase Switched-Capacitor DC–DC Converter Ring With Fast Transient Response and Small Ripple

A fully integrated step-down switched-capacitor dc–dc converter ring with 123 phases has been designed that could achieve fast dynamic voltage scaling for the microprocessor of wearable devices. The symmetrical multiphase converter ring surrounds its load in the square and supplies power to the on-chip power grid that is easily accessible at any point of the chip edges. The frequency of the $V_{\mathrm {DD}}$ -controlled oscillator is adjusted through its supply voltage $V_{\mathrm {DD}}$ , which allows the unity-gain frequency to be designed higher than the switching frequency. The converter ring has been fabricated in a low-leakage 65-nm CMOS process. This converter achieves a response time of 3 ns, a reference tracking speed of 2.5 V/ $\mu \text{s}$ , and a minimum output ripple of 2.2 mV. The peak efficiency is 80% at the power density of 66.6 mW/mm2, and the maximum power density is 180 mW/mm2.

A Three-Level Fuzzy-2 DTC of Induction Motor Drive Using SVPWM

This paper presents proportional integral direct torque control (PIDTC) and fuzzy-2 DTC (F2DTC) of the induction motor (IM) drive using space vector pulse width modulation (SVPWM) for three-level diode-clamped inverter (TDCI). The above control schemes have been implemented in the laboratory using 2 HP IM through a DSPACE DS-1104 controller. The control schemes are capable to balance the dc-link capacitor voltages of TDCI by selecting an optimum voltage vector without using an extra controller. However, the three-level PIDTC of an IM gives poor transient performance during starting, loading, and speed reversal with considerable current and voltage total harmonic distortion (THD). In addition, it takes more time to reach the steady state with large spikes on capacitor voltages during the load or speed variation. This is due to poor performance of the PI controllers (speed and torque). In F2DTC, the conventional PI controllers are replaced by Mamdani-type fuzzy-2 controllers using a centroid method with simple logical rules. The simulated and experimental performance show that F2DTC for the three-level inverter-fed IM drive provides a fast dynamic response, less current and voltage THDs, considerable less distortion in flux and torque, and fewer spikes on capacitor voltages as compared to PIDTC.

Magnetic Inductors and Their Increasing Importance in the Development of on-Chip Power Conversion

Major strides in on-chip power conversion have been made by IBM in case of their POWER8TM processor (1), and by Intel in case of their 4th generation (Haswell) processor (2), although neither company’s new on-chip voltage regulator (VR) uses an integrated inductor. After outlining why on-chip power conversion is so desirable, this talk will highlight the important role of magnetic inductors in power conversion, and will review recent developments in, and prospects for, magnetic materials for inductors, especially those formed by plating methods.Granular DC-DC power delivery, consisting of fast dynamic voltage scaling for each load through use of a dedicated VR, can significantly improve energy efficiency. Traditionally, the large size of the inductor component has impeded efforts to fabricate the VR in one module. The preferred approach to shrinking the inductor is to increase the switching frequency. The downside to higher frequency operation is reduced efficiency and increased heat dissipation. Thus, shrinking the inductor involves a compromise of space vs. performance, and placing the VRM with an integrated inductor on the processor using thin-film fabrication processes is a natural, if challenging, progression.In thin-film ferromagnetic inductors, yoke material and thicknesses (typically 1 - 3 microns) can be tailored to reach desired inductance values (e.g., 10 – 40 nH), while endeavoring to maintain high enough operating frequency (e.g., 50 – 100 MHz). Considerable efforts have gone into developing new magnetic alloys with higher resistivity (> 100 µΩcm) to reduce yoke eddy currents. A notable example produced by sputtering is amorphous Co91.5Zr4Ta4.5 (CZT) [3, 4], which seems to have become the standard against which other materials are compared. This has been used as the yoke material in inductors fabricated on top of 90 nm CMOS structures by Gardner et al. [5], for example.Electroplating has been a standard technique for the deposition of thick metal films due to its high deposition rate, conformal coverage and low cost. It was an enabling technology for the thin-film magnetic recording head, and was thus used for yoke fabrication for our inductors (6, 7). For the latter, Ni45Fe55 was chosen over Ni80Fe20 for its higher magnetic moment (1.6T), high anisotropy field, and higher electrical resistivity (40 µΩcm). Plated Co-based materials are attractive alternatives to Ni-Fe as yoke materials, e.g. due to their higher moment, especially if their resistivity can be made to approach or exceed 100 µΩcm. We are exploring the use of electrolessly-plated, Co-W-P films for inductor applications (8). The electroless Co-W-P films show excellent magnetic properties, with good magnetic anisotropy, and coercivity of less than 0.1 Oe (Fig. 1). The resistivity of the films is about 90-100 µΩcm, which is close to that of most amorphous Co-based alloys. [1] Z. Toprak-Deniz et al., ISSCC Digest, 112 (2014).[2] E. A. Burton, et al., Proc. Applied Power Electronics and Expositions (IEEE-APEC), p. 432-439 (2014)[3] K. Hayashi et al., J. Appl. Phys., 61, 2983 (1987).[4] D. S. Gardner et al., IEEE Trans. Magn. 43, 2615 (2007).[5] D. S. Gardner et al., J. Appl. Phys., 103, 07E927 (2008).[6] N. Wang et al., J. Appl. Phys., 111, 07E732 (2012).[7] N. Sturcken et al., ISSCC, 48, 244 (2013).[8] N. Wang et al., MMM-Intermag, paper HG-11, 2013 Fig. 1. Hysteresis loop (left) and SEM Xsection (right) of an electrolessly-plated Co-W-P films.This work was supported in part by Lawrence Livermore National Laboratory subcontract No. B601996 under prime contract DE-AC52-07NA27344 from the U.S. Government. Inductor fabrication was carried out in the Microelectronics Research Laboratory (MRL) at IBM’s T. J. Watson Research Center.

Fast online dynamic voltage instability prediction and voltage stability classification

In this study, a novel approach is proposed for fast prediction of dynamic voltage instability occurrence (as a short term phenomenon and/or a long term one) and voltage stability stiffness of the system, against load disturbances. The main contribution of this paper is in introducing a procedure for generating novel features to be applied to a pattern classifier, by which dynamic voltage stability status of a power system can be predicted. The proposed feature generation procedure only needs measured pre-disturbance variables and disturbance severity provided by phasor measurement units as inputs whereas a set of output variables are derived from an unconstrained power flow program. Since the proposed method does not need any measured post disturbance data, the prediction task can be performed just after the disturbance. Thus, corrective actions can be executed in a short time after the disturbance to inhibit voltage instability. Moreover as no measured post-disturbance data are needed, the proposed method can also be employed in preventive procedures for voltage stability enhancement and/or decreasing possibility of voltage instability occurrence. Training a decision tree based classifier with the proposed features and testing the method on a modified version of Nordic32 test system, the simulation results have demonstrated that the proposed method effectively predicts the status of dynamic voltage stability in the test system.

Power-Tracking Embedded Buck–Boost Converter With Fast Dynamic Voltage Scaling for the SoC System

A power-tracking embedded buck-boost converter with a fast dynamic voltage scaling (F-DVS) function is proposed to power the system-on-a-chip (SoC) system. To meet the power request of the SoC for different operation functions, fast up/down-tracking is implemented to achieve the F-DVS function. Recycling energy is also derived to minimize power dissipation during the down-tracking period. In addition, the peak current control and valley current control methods are utilized in the buck and boost operations, respectively, to minimize the effect of switching noise in high switching operation for compact solution. Moreover, the self-tuning pulse skipping mechanism extends the effective duty cycle to achieve voltage regulation and improves efficiency when the input voltage is close to that of the output. Through F-DVS, the tracking speed from 3 to 2 V and vice versa are 15 and 20 μs, respectively, with a high switching frequency of 5 MHz.

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops

Built-in resiliency features enable a microprocessor to detect and correct errors due to fast dynamic voltage droop events as well as other types of dynamic variations. Timing errors in the microprocessor core as well as read (RD) and write (WR) errors in the 8T SRAM based cache can be detected. As a result, guardbands added for these variations are reduced or eliminated, improving performance and reducing power consumption. Measurements on a 45 nm research microprocessor core demonstrate 41% improvement in throughput or 22% reduction in energy at 0.8 V. Measurements on the cache demonstrate reduction of the minimum operating Vcc (VMIN) by 9% thereby resulting in a 7.5% reduction of net operating power.