Fast Decoding Research Articles

An Optimized Cyclic Weight Algorithm of (47, 24, 11) QR Code and Hardware Implementation

This paper proposes an optimized cyclic weight (OCW) decoding algorithm based on novelty ideas. The OCW algorithm utilizes the properties of quadratic residue (QR) codes and the advantages of the syndrome-weight algorithm to facilitate fast decoding of the binary systematic (47, 24, 11) QR code. The memory size of the OCW algorithm is reduced to only 0.45% of that in the original cyclic weight algorithm. In addition, it can be carried out in simple and repeatable steps, which is of great importance for hardware implementation. We further propose a hardware architecture in ALTERA STRATIX V FPGA by adopting parallel processing and pipeline techniques. To the best of our knowledge, it is the first hardware architecture to decode (47, 24, 11) QR code. The synthesized results in ALTERA QUARTUS V17.0 show that the proposed hardware architecture operates at high throughput and low latency. The proposed hardware module may be a good candidate in 5G wireless communications.

A complexity-reduced fast successive cancellation list decoder for polar codes

A multi-bit decision for polar codes based on a simplified successive cancellation (SSC) decoding algorithm can improve the throughput of polar decoding. A list algorithm is used to improve the error-correcting performance. However, list decoders are highly complex compared with decoders without a list algorithm. In this paper, a low-complexity list decoder is proposed, where path-splitting operations for a multi-bit decision can be avoided, if the decoding reliability exceeds a threshold. The threshold is determined based on the reliability of subchannels and positions of decoding nodes. Path splitting rules are designed for multi-bit decision processes, and a complexity-reduced list decoder is proposed based on this. Results show that the number of survival paths can be greatly reduced at the cost of negligible deterioration in block error performance. Thus, the computational complexity can be significantly reduced, especially for a high signal-to-noise ratio (SNR) region.

A fast, invariant representation for human action in the visual system.

Humans can effortlessly recognize others' actions in the presence of complex transformations, such as changes in viewpoint. Several studies have located the regions in the brain involved in invariant action recognition; however, the underlying neural computations remain poorly understood. We use magnetoencephalography decoding and a data set of well-controlled, naturalistic videos of five actions (run, walk, jump, eat, drink) performed by different actors at different viewpoints to study the computational steps used to recognize actions across complex transformations. In particular, we ask when the brain discriminates between different actions, and when it does so in a manner that is invariant to changes in 3D viewpoint. We measure the latency difference between invariant and noninvariant action decoding when subjects view full videos as well as form-depleted and motion-depleted stimuli. We were unable to detect a difference in decoding latency or temporal profile between invariant and noninvariant action recognition in full videos. However, when either form or motion information is removed from the stimulus set, we observe a decrease and delay in invariant action decoding. Our results suggest that the brain recognizes actions and builds invariance to complex transformations at the same time and that both form and motion information are crucial for fast, invariant action recognition. NEW & NOTEWORTHY The human brain can quickly recognize actions despite transformations that change their visual appearance. We use neural timing data to uncover the computations underlying this ability. We find that within 200 ms action can be read out of magnetoencephalography data and that this representation is invariant to changes in viewpoint. We find form and motion are needed for this fast action decoding, suggesting that the brain quickly integrates complex spatiotemporal features to form invariant action representations.

Fast Successive-Cancellation Decoding of Polar Codes: Identification and Decoding of New Nodes

The decoding latency of polar codes can be reduced by implementing fast parallel decoders in the last stages of decoding. In this letter, we present five such decoders corresponding to different frozen-bit sequences to improve the decoding speed of polar codes. Implementing them achieves significant latency reduction without tangibly altering the bit-error-rate performance of the code.

A novel physical layer scheme based on superposition codes

The recently proposed superposition codes (SCs) have been mathematically proved to be decoded at any rate below the capacity, for additive white Gaussian noise (AWGN) channels. The main objective of this paper is to study the feasibility of a novel SC approach as an alternative to the traditional way of designing modern physical (PHY) layer schemes. Indeed, currently, PHY solutions are based on the decomposition into two separate problems of modulation shaping and coding over finite alphabets. Since superposition codes are defined over real numbers, modulation and coding can be jointly realized. Moreover, a fast decoding method is developed and tested by comparing the obtained results with both the uncoded system performance and two approximate message passing (AMP) algorithms. Finally, possible perspective to fifth generation (5G) applications exploiting SC solutions are outlined in the paper, and some interesting relations with sparse signal recovery are analyzed for further future research lines.

A Parallel Belief Propagation Decoding Algorithm for Rate Compatible Modulation

This letter proposes a parallel belief propagation algorithm for fast iterative decoding of rate compatible modulation. In this proposed algorithm, the processing at symbol node is partitioned into several low complexity sub-processors. All sub-processors have similar structures and work in parallel without cross connections among them. Numerical and simulation results show that proper partition results in significant reduction of the computational complexity without decoding performance degradation.

Boolean operations-based visual secret sharing for general access structures

Compared to conventional visual secret sharing (VSS), Boolean operations-based VSS solves the problems of the large pixel expansion (pe) and the complex computation involved in the decryption process. However, the existing VSS schemes based on Boolean operations are limited only to (2, n), (n, n) and (k, n). In this paper, we propose a Boolean operations-based VSS scheme for general access structures. The proposed scheme encodes the secret image into several shares such that the secret image can be reconstructed only by any qualified subset of the shares. The proposed scheme has lossless secret reconstruction with an acceptable pixel expansion (0 < pe < 1.5) and fast decoding process. The correctness of the proposed scheme is validated by formal security analysis and the experimental results.

A novel soft reliability-based iterative majority-logic decoding algorithm with uniform quantization

In this paper, a novel soft reliability-based iterative majority-logic decoding algorithm with uniform quantization is proposed for regularly structured low density parity-check (LDPC) codes. A weighted measure is introduced for each check-sum of the parity-check matrix and a scaling factor is used to weaken the overestimation of extrinsic information. Furthermore, the updating process of the reliability measure takes advantage of turbo-like iterative decoding strategy. The main computational complexity of the proposed algorithm only includes logical and integer operations with the bit uniform quantization criterion. Simulation results show that the novel decoding algorithm can achieve excellent error-correction performance and a fast decoding convergence speed.

Fast and Flexible Successive-Cancellation List Decoders for Polar Codes

Polar codes have gained significant amount of attention during the past few years and have been selected as a coding scheme for the next generation of mobile broadband standard. Among decoding schemes, successive-cancellation list (SCL) decoding provides a reasonable trade-off between the error-correction performance and hardware implementation complexity when used to decode polar codes, at the cost of limited throughput. The simplified SCL (SSCL) and its extension SSCL-SPC increase the speed of decoding by removing redundant calculations when encountering particular information and frozen bit patterns (rate one and single parity check codes), while keeping the error-correction performance unaltered. In this paper, we improve SSCL and SSCL-SPC by proving that the list size imposes a specific number of bit estimations required to decode rate one and single parity check codes. Thus, the number of estimations can be limited while guaranteeing exactly the same error-correction performance as if all bits of the code were estimated. We call the new decoding algorithms Fast-SSCL and Fast-SSCL-SPC. Moreover, we show that the number of bit estimations in a practical application can be tuned to achieve desirable speed, while keeping the error-correction performance almost unchanged. Hardware architectures implementing both algorithms are then described and implemented: it is shown that our design can achieve 1.86 Gb/s throughput, higher than the best state-of-the-art decoders.

FPGA design of the fast decoder for burst errors correction

The paper is about FPGA design of the fast single stage decoder for correcting burst errors during data transmission. The decoder allows correcting burst errors with 3 bits for a 15 bit codeword and a 7 bit check unit. The description of a generator polynomial search algorithm for building error-correcting codes was represented. The module structure of the decoder was designed for FPGA implementation. There are modules, such as remainder, check_pattern, decoder2, implemented by asynchronous combinational circuits without memory elements, and they process each codeword shift in parallel. Proposed implementation allows getting high performance about ∼20 ns.

Fast and Parallel AAC Decoder Architecture for a Digital Radio Mondiale 30 Receiver

An embedded real-time indexing engine for live radio stations requires a high-speed parallel advanced audio coding (AAC) decoder architecture to decode hundreds of compressed audio streams broadcast in the digital radio mondiale band. Several AAC hardware core units must be integrated into a single chip and synchronized with a global controller to achieve such high performance. This paper proposes a new parallel AAC decoder architecture to address this challenge. The proposed architecture includes multiple AAC decoder core units, each of which achieves a speed-up by a factor of 2 compared with the existing AAC decoder core units while using optimal logic resources. The proposed architecture overcomes several challenges faced by existing architectures. The Huffman decoder module decodes one word per clock cycle regardless of word length, and a smaller lookup table size is achieved for the inverse quantization module. The inverse modified discrete cosine transform architecture is fully pipelined, and the resource sharing technique is used to reduce the logic area. An initial prototype is implemented on an FPGA platform.

Quasi-cyclic Expansion Algorithm for Protograph LDPC Codes Based on PEG and PH

One of the important code of modern coding theory, the protograph LDPC code technology has been gained more and more attention due to its low encoding complexity, fast decoding speed, low BER, and simple optimization analysis process etc. the quasi-cyclic expansion algorithm of the protograph LDPC codes, named as PQCE algorithms, can complete the extension of protograph and eventually get the protograph LDPC codes. However, the existing PQCE algorithms may be with a low convergence rate, or exist many short cycles in the check matrix. To solve the above problem, a Quasi-cyclic expansion algorithm for protograph LDPC codes based on PEG and PH is proposed in this paper, referred as PEG-PH-PQCE algorithm. In the proposed algorithm, base matrix is acquired by PEG parallel edges elimination expansion algorithm during the first-step expansion of protograph. Then, the second-step expansion is completed, in which the initial index matrix is obtained by PEG quasi-cyclic expansion algorithm, and the check matrix is acquired by using the Hill Climbing algorithm to optimizing the initial index matrix. Simulation results demonstrate the effectiveness the validity of the proposed algorithm, such as, a small number of short cycles and high convergence rate, etc.

Singer product apertures—A coded aperture system with a fast decoding algorithm

A new type of coded aperture configuration that enables fast decoding of the coded aperture shadowgram data is presented. Based on the products of incidence vectors generated from the Singer difference sets, we call these Singer product apertures. For a range of aperture dimensions, we compare experimentally the performance of three decoding methods: standard decoding, induction decoding and direct vector decoding. In all cases the induction and direct vector methods are several orders of magnitude faster than the standard method, with direct vector decoding being significantly faster than induction decoding. For apertures of the same dimensions the increase in speed offered by direct vector decoding over induction decoding is better for lower throughput apertures.

A Fast Polar Code List Decoder Architecture Based on Sphere Decoding

Polar codes are a recently discovered family of capacity-achieving error-correcting codes. Among the proposed decoding algorithms, successive-cancellation list decoding guarantees the best error-correction performance with codes of moderate lengths, but it yields low throughput. Speed-up techniques have been proposed in the past: most of them rely on approximations that degrade the error-correction capability of the algorithm. We propose a speed-up technique for successive-cancellation list decoding of polar codes that is exact for list size of 2, while its approximations bring negligible error-correction performance degradation ( $3.16\times $ , at the cost of 14.2% in area occupation.

Ethnic humour in a multicultural society

AbstractThe coexistence of different cultures in specific pluralistic settings not only has positive but also negative impacts. Besides exchanging cultural contents within a multicultural environment, societies use humour as a form of social interaction, which reinforces cultural interrelationships as well as ethnical differences. However, humour differs from culture to culture and from individual to individual. On the one hand, it develops social cohesion, fosters positive relations and increases the self-identification of the individual in relation to other ethnic groups, but on the other hand, it functions as an acceptable and tolerated form of aggression in a particular society. The bipolar character of humour stems from its status and functions. It serves both as a social unifier and a social separator. The most common paradigms of humour in social discourse are ethnic jokes or cartoons that are often built on fixed ethnic/racial stereotypes leading to social categorization but also to fast and correct decoding of semantic information by an audience. Ethnic jokes are social thermometers, recording and measuring the level of sensitivity towards specific cultural groups. The main aim of this paper is to introduce ethnic humour and its key functions in the context of ongoing cultural interactions and changes.

A Space-Time Code Design for Omnidirectional Transmission in Massive MIMO Systems

Omnidirectional space-time coding has been proposed recently for massive multiple-input multiple-output (MIMO) systems to broadcast common information. In these systems, signals across all transmit antennas have constant power and their discrete Fourier transforms have constant power as well, where the number of discrete frequencies is the number of transmit antennas. When the number of transmit antennas is large, i.e., it is a massive MIMO system, signals received at these discrete angles have constant mean power at any instant time. Furthermore, spatial diversity can be achieved. In this letter, we propose a different design of such a transmission, where the sum of received signal powers in a few consecutive time slots is constant at any angle (not just discrete angles). The other two properties mentioned above, namely, constant transmission power across antennas at any instant time and achieving spatial diversity, are still maintained. Furthermore, it has the fast symbol-wise maximum-likelihood decoding.

Recyclable Counter With Confinement for Real-Time Per-Flow Measurement

With the amount of Internet traffic increasing substantially, measuring per-flow traffic accurately is an important task. Because of the nature of high-speed routers, a measurement algorithm should be fast enough to process every packet going through them, and should be executable with only a limited amount of memory, as well. In this paper, we use two techniques to solve memory/speed constraints: (1) recycling a memory block by resetting it (for memory constraint), and (2) confinement of virtual vectors to one word (for speed constraint). These techniques allow our measurement algorithm, called a recyclable counter with confinement (RCC), to accurately measure all individual flow sizes with a small amount of memory. In terms of encoding speed, it uses about one memory access and one hash computation. Unlike other previously proposed schemes, RCC decodes very quickly, demanding about three memory accesses and two hash calculations. This fast decoding enables real-time detection of a high uploader/downloader. Finally, RCC's data structure includes flow labels for large flows, so it is possible to quickly retrieve a list of large-flow names and sizes.

Fast Decoding ECC for Future Memories

High-performance storage class memories could benefit from a fast decoding error correcting code (ECC), able to correct a few errors in just a few nanoseconds. The class of BCH codes provides excellent candidates to play this role. The low latency requirement prevents adopting iterative or sequential processes in the encoding and decoding phases-as traditionally done for storage application based on Flash NAND technology. Therefore, we propose an architecture for fast decoding of double and triple ECCs. In our architecture, any time-consuming iterative computation is eliminated, and the most complex evaluations are isolated and carried in parallel with the other terms, to avoid bottlenecks in the decoder. In particular, the error locator polynomial is computed by a combinatorial logic, and its roots are searched by testing all the bits simultaneously. Here, we describe a gate-level design of these architectures. We also give an in-depth analysis of hardware-oriented implementations of finite field operations, and of bases for element representation.

A Diversity-Multiplexing Tradeoff Optimal Low Complexity Zero Forcing Method Based on ZP-OFDM

Due to the computational complexity of maximum-likelihood signal decoding, the equalizers with less complexity are considered in the literature. Employing the zero forcing (ZF) equalizer, zero-padded orthogonal frequency-division multiplexing (ZP-OFDM) is capable of benefiting the maximum available multipath diversity with the computational complexity of inverting a matrix of the size of data block length, which incurs an extra implementation cost relative to the fast Fourier transform-based OFDM decoder. In this paper, based on the ZP-OFDM encoding scheme, we propose a two-stage decoder that attains the maximum multipath diversity with lower computational complexity, as compared with the ZF ZP-OFDM and prove analytically that our proposed decoder is diversity-multiplexing tradeoff optimal. It has also been shown that by setting the decoder parameters, it can attain any arbitrary diversity gain smaller than the maximum multipath diversity. Moreover, the more the diversity gain is decreased the more the computational complexity is reduced.

Fast Low-Complexity Decoders for Low-Rate Polar Codes

Polar codes are capacity-achieving error-correcting codes with an explicit construction that can be decoded with low-complexity algorithms. In this work, we show how the state-of-the-art low-complexity decoding algorithm can be improved to better accommodate low-rate codes. More constituent codes are recognized in the updated algorithm and dedicated hardware is added to efficiently decode these new constituent codes. We also alter the polar code construction to further decrease the latency and increase the throughput with little to no noticeable effect on error-correction performance. Rate-flexible decoders for polar codes of length 1024 and 2048 are implemented on FPGA. Over the previous work, they are shown to have from 22 % to 28 % lower latency and 26 % to 34 % greater throughput when decoding low-rate codes. On 65 nm ASIC CMOS technology, the proposed decoder for a (1024, 512) polar code is shown to compare favorably against the state-of-the-art ASIC decoders. With a clock frequency of 400 MHz and a supply voltage of 0.8 V, it has a latency of 0.41 μs and an area efficiency of 1.8 Gbps/mm 2 for an energy efficiency of 77 pJ/info. bit. At 600 MHz with a supply of 1 V, the latency is reduced to 0.27 μs and the area efficiency increased to 2.7 Gbps/mm 2 at 115 pJ/info. bit.