Fast DCT Algorithm Research Articles

A further reduction of multiplications in Wang's fast DCT algorithm

Further reduction of multiplications in fast computatio of several types of DCT is achieved by extraction of a common factor from Wang's algorithm.

Unified forward and inverse discrete cosine transform architecture and proposed VLSI implementation

A unified discrete cosine transform and inverse discrete cosine transform (DCT/IDCT) architecture is used in the design of a proposed single-chip VLSI implementation of this function. An 8-point by 1 organization of the DCT/IDCT is chosen to allow easy implementation of the 8 × 8 format under consideration for recommendation by the International Consultative Committee for Telephone and Telegraph (CCJTT) for 384 K-bit CODECs. Fast DCT and IDCT algorithms are merged into a single hardware architecture that is programmable with a single DCT/IDCT selection switch. To accomplish real-time 10 MHz video data processing, the basic system clock brings data in and sends data out each 100 ns. Eight pixels are loaded for simultaneous processing every 800 ns and the module of each pipeline stage processes these eight elements simultaneously. Algorithm simulations and experimental performance of integrated test sub-circuit prototypes indicate that this proposed new DCT/IDCT chip would be capable of the real-time proces...