Fast Circuit Switching Research Articles

Mars: Near-Optimal Throughput with Shallow Buffers in Reconfigurable Datacenter Networks

The performance of large-scale computing systems often critically depends on high-performance communication networks. Dynamically reconfigurable topologies, e.g., based on optical circuit switches, are emerging as an innovative new technology to deal with the explosive growth of datacenter traffic. Specifically, periodic reconfigurable datacenter networks (RDCNs) such as RotorNet (SIGCOMM 2017), Opera (NSDI 2020) and Sirius (SIGCOMM 2020) have been shown to provide high throughput, by emulating a complete graph through fast periodic circuit switch scheduling. However, to achieve such a high throughput, existing reconfigurable network designs pay a high price: in terms of potentially high delays, but also, as we show as a first contribution in this paper, in terms of the high buffer requirements. In particular, we show that under buffer constraints, emulating the high-throughput complete graph is infeasible at scale, and we uncover a spectrum of unvisited and attractive alternative RDCNs, which emulate regular graphs, but with lower node degree than the complete graph. We present Mars, a periodic reconfigurable topology which emulates a d-regular graph with near-optimal throughput. In particular, we systematically analyze how the degree~d can be optimized for throughput given the available buffer and delay tolerance of the datacenter. We further show empirically that Mars achieves higher throughput compared to existing systems when buffer sizes are bounded.

Mars: Near-Optimal Throughput with Shallow Buffers in Reconfigurable Datacenter Networks

The performance of large-scale computing systems often critically depends on high-performance communication networks. Dynamically reconfigurable topologies, e.g., based on optical circuit switches, are emerging as an innovative new technology to deal with the explosive growth of datacenter traffic. Specifically, periodic reconfigurable datacenter networks (RDCNs) such as RotorNet (SIGCOMM 2017), Opera (NSDI 2020) and Sirius (SIGCOMM 2020) have been shown to provide high throughput, by emulating a complete graph through fast periodic circuit switch scheduling. However, to achieve such a high throughput, existing reconfigurable network designs pay a high price: in terms of potentially high delays, but also, as we show as a first contribution in this paper, in terms of the high buffer requirements. In particular, we show that under buffer constraints, emulating the high-throughput complete graph is infeasible at scale, and we uncover a spectrum of unvisited and attractive alternative RDCNs, which emulate regular graphs, but with lower node degree than the complete graph. We present Mars, a periodic reconfigurable topology which emulates ad-regular graph with near-optimal throughput. In particular, we systematically analyze how the degree d can be optimized for throughput given the available buffer and delay tolerance of the datacenter. We further show empirically that Mars achieves higher throughput compared to existing systems when buffer sizes are bounded.

Novel high-performance QCA Fredkin gate and designing scalable QCA binary to gray and vice versa

In the design of digital logic circuits, QCA technology is an excellent alternative to CMOS technology. Its advantages over CMOS include low power consumption, fast circuit switching, and nanoscale design. Circuits that convert data between different formats are code converters. Code converters have an essential role in high-performance computing and signal processing. In this paper, first, we proposed a novel QCA structure for the quantum reversible Fredkin gate. Second, we proposed 4-bit and 8-bit QCA binary-to-gray converter and vice versa. For the second proposal, both reversible and irreversible structures are suggested. The proposed structures are scalable up to N bits. To change the conversion type from B2G to G2B, we use a 2:1 QCA multiplexer. The proposed QCA Fredkin is applied in the reversible design of QCA code converters as multiplexers. The suggested designs are simulated using the QCADesigner tool. Then we calculated figures of merit, including cell counts, occupied areas, and clock zones. Finally, we compare the proposed structures to existing research. Our proposed approach is the first quantum-dot cellular automata design to perform B2G conversion and G2B in a single QCA circuit. The proposed designs are scalable. Specifications are reported.

Multi-objective Optimization of Retaining Unit of Actuator for Fast Vacuum Circuit Switch Considering Tolerance Uncertainty

Multi-objective Optimization of Retaining Unit of Actuator for Fast Vacuum Circuit Switch Considering Tolerance Uncertainty

Scalable and Fast Optical Circuit Switch Based on Colorless Coherent Detection: Design Principle and Experimental Demonstration

We investigate a large-scale and fast optical circuit switch system that uses digital coherent technologies. The achievable port count is expanded by introducing colorless detection which eliminates channel selecting filters at receivers. Wavelength selection is performed using a shared local oscillator (LO) bank, which is configured by combining a multi-wavelength optical source with Silicon-photonic tunable filters (TFs). Microsecond switching times are realized with the thermo-optic effect available with the Silicon-photonic TF. Design optimization of the proposed system handles complex level of freedom, i.e., available wavelength number, space switch port count, optical amplifier location and gain, and device loss. In addition, colorless coherent detection induces penalties, which further complicates switch scale assessment. In this paper, we develop a simulator to clarify how those parameters affect switch performance; the switch throughput is maximized with consideration of the degradation stemming from colorless detection. The design performance accurately matches results measured in various system scenarios. A dual-carrier 256-Gb/s DP-QPSK experiment successfully demonstrates a 1,856 × 1,856 optical switch system with switching time under 3.52 μs. The resulting total throughput is 441 Tb/s assuming 7%-overhead HD-FEC. To the best of our knowledge, this is the first demonstration of 400-Tbps class large bandwidth optical switches that use TFs as wavelength selective devices for coherent detection.

A Dynamically-Reconfigurable Burst-Mode Link Using a Nanosecond Photonic Switch

Fast optical circuit switching has significant potential to solve scaling issues with traditional packet-switch-based networks and improve bandwidth and power efficiency in datacenter and high-performance computing applications. One difficultly in utilizing a fast optical switch is that the optical signal must be rapidly reacquired after each switching event so as to not significantly impact the overall throughput of the system. Here we present a system-level integration of a nanosecond-scale $2\times 2$ silicon photonic switch with a 25-Gbps burst-mode receiver that can lock in 31 ns. A novel FPGA-based control plane was used to generate test data, control the silicon photonic switch and burst-mode receiver, and measure bit errors at 12.5 and 20 Gbps. Error-free links (BER $ ) with system-level reconfiguration times below 60 ns (at 20 Gbps) and 90 ns (at 12.5 Gbps) including bit- and frame-synchronization are demonstrated.

Realization and Application of Large-Scale Fast Optical Circuit Switch for Data Center Networking

Applying optical switching to data center networks can greatly expand network bandwidth and reduce electrical power consumption, both of which are needed to meet the explosive traffic increase. The optical switch offers large bandwidth switching capability, and so eliminates the multistage switch network architecture needed with electrical switching. Furthermore, the single stage architecture of the optical switch greatly simplifies operating costs, which include cabling, while substantially reducing the number of transponders needed. Data center networks place very different demands on optical systems than communication networks. Grasping the right direction to proceed is of paramount importance. To realize the full potential of optical switches, such as scalability and cost effectiveness, we analyze the role of large-scale optical circuit switches and discuss the realization technologies that combine the two dimensions of space and wavelength. Our recent advances in large port-count optical switches are presented.

Scheduling traffic for maximum switch lifetime in optical data center fabrics

Optical switching is a promising technology to scale the performance of data centers. We address two scenarios: hybrid data centers, in which an optical circuit switching network operates in parallel to an electronic packet switching network that interconnect the servers, and full optical data centers, in which all the traffic is switched in the optical domain. The traffic on the optical network is scheduled proactively by configuring the optical fabric according to a precomputed sequence of configurations. We consider that fast optical circuit switching is implemented through micro-mechanical devices (like MEMS) at each crosspoint, whose lifetime is limited by a maximum number of configuration cycles, due to the experienced mechanical fatigue. We consider the traffic scheduling problem on the optical network and address specifically the problem of minimizing the number of reconfigurations at each crosspoint, in order to maximize the MEMS lifetime, while maximizing the throughput. We propose a family of scheduling algorithms and discuss the achievable tradeoff between lifetime, throughput and computational complexity, throughout a set of extensive simulations and theoretical results.

Electronic and photonic integrated circuits for fast data center optical circuit switches

This article surveys recent work in optical switching technologies and presents a fast optical circuit switch that intimately integrates the control electrics at the chip level using a novel wafer-scale heterogeneous integration technique.

Optical Fast Circuit Switching Networks Employing Dynamic Waveband Tunnel

SUMMARY We propose a novel dynamic hierarchical optical path network architecture that achieves efficient optical fast circuit switching. In order to complete wavelength path setup/teardown efficiently, the proposed network adaptively manages waveband paths and bundles of optical paths, which provide virtual mesh connectivity between node pairs for wavelength paths. Numerical experiments show that operational and facility costs are significantly reduced by employing the adaptive virtual waveband connec

A dynamic and quasi-centralized RWA method for optical fast circuit switching networks employing route pre-prioritization

We propose a new dynamic RWA algorithm for optical fast circuit switching networks, agile optical networks that can accommodate changing broadband demands. The algorithm utilizes pre-computed prioritized route candidates that reflect statistical information such as traffic distribution characteristics to attain better load balancing. The route priority is periodically distributed over a network and RWA for each path connection demand is processed in a distributed manner. Numerical experiments demonstrate that the algorithm matches the performance of a centralized RWA algorithm that uses all the necessary information on a network.

Influence of Matrix Circuit Switching Device Junction Capacitance on Piezoelectric Actuator Drive Performance

Piezoelectric actuators are widely used as fine-motion actuators for positioning devices. Current pulse driving reduces displacement hysteresis, and the drive circuit provides current pulses considered constant charge pulses to the piezoelectric actuator. The circuit for devices with multiple degrees of freedom using multiple piezoelectric actuators should be simple. Matrix circuits are used to drive liquid crystal displays to reduce the number of drive-circuit control signals and components. A group of 2 × 2 piezoelectric actuators was driven alternately using a 4-switch matrix circuit, and two field effect transistors were used as a fast matrix circuit switch. Piezoelectric actuator drive performance was studied in the case of using the current pulse circuit and the matrix circuit. When the matrix circuit drove actuators performing as capacitive loads, switching device junction capacitors adversely affected drive performance.

Analysis of a dynamically wavelength-routed optical burst switched network architecture

The concept of optical burst switching (OBS) aims to allow access to optical bandwidth in dense wavelength division multiplexed (DWDM) networks at fractions of the optical line rate to improve bandwidth utilization efficiency. This paper studies an alternative network architecture combining OBS with dynamic wavelength allocation under fast circuit switching to provide a scalable optical architecture with a guaranteed QoS in the presence of dynamic and bursty traffic loads. In the proposed architecture, all processing and buffering are concentrated at the network edge and bursts are routed over an optical transport core using dynamic wavelength assignment. It is assumed that there are no buffers or wavelength conversion in core nodes and that fast tuneable laser sources are used in the edge routers. This eliminates the forwarding bottleneck of electronic routers in DWDM networks for terabit-per-second throughput and guarantees forwarding with predefined delay at the edge and latency due only to propagation time in the core. The edge burst aggregation mechanisms are evaluated for a range of traffic statistics to identify their impact on the allowable burst lengths, required buffer size and achievable edge delays. Bandwidth utilization and wavelength reuse are introduced as new parameters characterizing the network performance in the case of dynamic wavelength allocation. Based on an analytical model, upper bounds for these parameters are derived to quantify the advantages of wavelength channel reuse, including the influence of the signaling round-trip time required for lightpath reservation. The results allow to quantify the operational gain achievable with fast wavelength switching compared to quasistatic wavelength-routed optical networks and can be applied to the design of future optical network architectures.

A QoS service for IP video applications on demand over DTM

The Differentiated Services model (DiffServ) provides a great flexibility in defining a variety of services through PHBs ( Per Hop Behaviors ) and traffic conditioners. It fits in well with the Integrated Services model (IntServ), jointly offering features such as: QoS signaling; admission control; channel management; assignment of resources (buffer and bandwidth); sorter configuration; and establishment of traffic agreements. With this integration you can have a scalable, flexible, and dynamic QoS environment in networks of the Internet core.This article describes and analyzes the DGF ( DTM Guaranteed Forwarding ) service that guarantees a minimum rate of retransmission of packets, based on RSVP signaling and traffic agreements (SLA), as well as losses close to the error rate of the physical medium, which are ideal features for video applications on demand.When this service is provided, the aforementioned QoS models are integrated with the transport and switching solution called DTM ( Dynamic Synchronous Transfer Mode ), a fast circuit switching technology. DTM is simple, cost-effective, provides QoS features, and is naturally dynamic in supplying bandwidth as well as flexible in fitting in with other IETF QoS models.Thus in the proposed architecture, IPoDQoS ( IP over DTM QoS ), we make use of the dynamism of network protocols and we offer managed VBR traffic in the IP layer (i.e.: DGF service) not originally offered in DTM technology.

Performance study of distributed channel allocation techniques for a fast circuit switched network

Dynamic synchronous transfer mode (DTM) is a next-generation high-speed networking technology. It is based on fast circuit switching and uses distributed channel allocation on shared media. The paper proposes a channel allocation algorithm for DTM, which improves the average call set-up time and call blocking probability characteristics. Another modification is also recommended to the operation, which provides fairness in the case of the examined network model. Many variants of the proposed and known techniques are compared in various network conditions. The performance evaluation of the algorithms is carried out by simulation, and practical conclusions are derived from the results.

Fast circuit switching for the next generation of high performance networks

Dynamic synchronous transfer mode (DTM) is a broadband network architecture based on fast circuit-switching augmented with dynamic reallocation of resources. It provides a service based on multicast, multirate channels with short setup delay and supports applications with real-time requirements on quality of service as well as applications with bursty, asynchronous traffic. The paper describes the DTM architecture and its distributed resource management scheme. Performance analysis results from network simulations are presented. The analysis is performed with respect to throughput and access delay for two network topologies: a dual bus and a grid of dual buses. The effects of varying user requirements, internode distances and transfer size are studied for uniform traffic patterns. The results indicate that the overhead for establishing channels is low (a few hundred microseconds), which gives a high degree of utilization even for short transfers. The analysis also shows that when channels are established very frequently, the signaling capacity limits the performance.

Burst switching-an update

Burst switching research in dispersed control and integrated switching is described. Burst transport is integrated in that voice and data are switched through the same switching fabric and transmission media. Burst switching is compared to and distinguished from fast packet, fast circuit, and ATM (asynchronous transfer mode) switching. Misunderstandings about burst transport that have appeared in the literature are corrected, to wit: burst does not immediately clip in case of channel contention; burst switches voice and data in the same way; and a burst switch interfaces naturally to other types of switches. Round-trip delay performance is calculated to be less than 5 ms. The current status of the burst project is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Circuit switching in multi-hop lightwave networks

Emerging high speed networks are using optical fibers employing time division synchronous communication. In these systems the use of optical switching is strongly advocated due to the bottleneck created by store and forward in electronic components. Switching solutions geared toward optical systems have been proposed so far only for packet switching networks. This paper introduces a new circuit switching approach for the emerging time division controlled fiber optic networks based on the requirement to avoid store and forward at intermediate nodes. The approach, termed Fast Circuit Switching (FCS), is unique in several operational and performance aspects. In terms of the way time slots within each cycle are allocated, a circuit is guaranteed a transmission slot immediately upon arrival at every intermediate node. As a result, the proposed Fast Circuit Switching (FCS) can be implemented by pure optical switches. In terms of performance, FCS guarantees minimum data transmission delays, consisting only of the end to end propagation delay in the network. Lastly due to being based on fixed time allocation at intermediate nodes, the FCS controlled system is purely end to end controlled. These properties make FCS inherently suitable for efficiently implementing circuit switching in wide area fiber optic networks, particularly, for supporting real time communications. The realization of slot assignments, which support the FCS solution, entails a novel graph oriented algorithmic approach. Several new algorithms for allocating circuits according to FCS are presented, dealing with fixed, as well as dynamic, circuit management. It is shown that, while providing unique operational and performance advantages as discussed above, the FCS is also bandwidth efficient, requiring only system bandwidth similar to conventional circuit switching methodologies.

Traffic analysis of a local area network with a star topology

Two forms of fast circuit switching are modeled and studied through mathematical analysis and Monte Carlo simulation. The two examples described use the switching technique in an optical-fiber-based local area network with a star topology. The technique is compatible with time-division multiplexing techniques that are used for a range of traffic classes. Further, the technique trades transmission capacity for processing power, which is the critical limitation of the system. By means of a certain independence assumption, the first form of fast circuit switching is modeled as an M/G/1 queue. The results of the analysis show excellent agreement with simulation. The general result is that there is good system throughput, despite simplicity of processing. The second form, in which rather than first-come first-served the discipline is to search for a message whose destination queue is free, is studied by means of simulation alone. The results indicate an improved performance with a modest increase in processing power.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A fast decoupled approach for optimum TDM assignment in constrained hierarchical switching systems

A three-tiered digital switching hierarchy is considered in which traffic from remote users is grouped, concentrated into time-multiplexed lines, and then transmitted to a central location for interconnection by a central space division switch. While the configuration provides efficient sharing of both transmission and switching resources, the TDM (time-division multiplexing) assignment problem for a conventional time-space-time (T-S-T) switch can become quite formidable due to the various hierarchical constraints. A time-slot assignment strategy is proposed that circumvents this problem by temporarily storing the incoming traffic at the central switch. Unlike the traditional T-S-T approach, the in-bound and out-bound assignments are entirely decoupled, which greatly simplifies the assignment process and produces a fast circuit switching capability. Necessary and sufficient conditions governing the assignability of traffic to the three-tiered switching system are stated and proved, and a block diagram of the proposed switching architecture is presented. >