Far-end Crosstalk Cancellation Research Articles

A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for High-Density Interconnects

This article presents a four-lane single-ended transceiver featuring a crosstalk-canceling coding scheme, Fibonacci coding (FC), which supports high-speed transmission over high-density parallel inter-chip channels. In-depth experiments and analyses are presented to evaluate FC’s performance, and the results suggest that the FC scheme can provide significant near-end and far-end crosstalk cancellation (XTC) while maintaining high channel density for high-speed multi-lane inter-chip links. By simulation, an effective data rate of 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 8.5 Gb/s is enhanced to 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 18 Gb/s by FC for a four-channel link. The transceiver, including an FC codec, a feed-forward equalizer (FFE), and a continuous-time linear equalizer (CTLE), is implemented in 28-nm CMOS. It achieves a data rate density of 0.90 Tb/s/in with an energy efficiency of 1.29 pJ/b and an area of 0.004 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> /lane. The performance of FC is measured on 3.8-mil-spaced four-lane coupled printed circuit board (PCB) microstrips. For the 2-in wires, the peak-to-peak jitter of the received eye is reduced by 45.0% at 10 Gb/s, and the horizontal aperture is broadened to 0.58 UI at a bit error rate (BER) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-12}$</tex-math> </inline-formula> by activating the FC scheme and equalizers. For the 5-in wires, the jitter is reduced by 43.9% and the eye is 0.47-UI-wide at 8.5 Gb/s. And for the 8-in wires, the jitter is reduced by 49.0% and the eye is 0.43-UI-wide at 6 Gb/s.

Far-End Crosstalk Cancellation With MIMO OFDM for &gt;200 Gb/s ADC-Based Serial Links

This brief presents an area- and power-efficient far-end crosstalk (FEXT) cancellation scheme with multi-input multi-output (MIMO) orthogonal frequency-division multiplexing (OFDM) for an analog-to-digital converter (ADC)-based ultra-high-speed serial links. The frequency-domain per-sub-channel equalization nature of OFDM allows a simple FEXT cancellation with MIMO equalizer in its digital signal processor (DSP), unlike time-domain pulse amplitude modulation (PAM) that requires heavy parallel cross-lane filtering for FEXT cancellation. With architectural modeling of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 2$ </tex-math></inline-formula> MIMO OFDM wireline transceiver (TRX), simulation results show that the main and FEXT channels’ frequency responses are properly estimated using pilot symbols. With the estimated channel responses, simulation results also show that the FEXT can be effectively canceled out with per-sub-channel MIMO equalization, achieving an overall symbol error rate (SER) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.4\times 10^{\mathrm {-5}}$ </tex-math></inline-formula> at 224Gb/s/lane for a channel having 23dB loss at 40 GHz, while the SER is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times 10^{\mathrm {-1}}$ </tex-math></inline-formula> without FEXT cancellation.

A 40 nm 16 Gb/s differential transmitter with far-end crosstalk cancellation using injection timing control for high-density flexible flat cables

In some long-reach high-density wires such as flexible flat cables, the crosstalk signal from the aggressor to the victim lanes exhibits the time shift that depends on the cables. This paper proposes a far-end crosstalk (FEXT) cancellation method with controllable injection timing of the crosstalk cancellation (XTC) signals into the victim lanes. The proposed method uses a delay-line-based digital-to-time converter for delay tuning and generates the XTC signals at the transmitter, then inject it to cancel the FEXT effectively on these cables. The proposed XTC circuit is implemented in the differential transmitter so that the XTC signal is generated from the digital data signal from the aggressor. The transmitter circuit with the proposed XTC technique is designed in a 40 nm bulk CMOS process, and its feasibility is verified through the post-layout simulation at a data rate of 16 Gb/s.

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme, which combines analog filters and decision-feedback crosstalk compensation on the receiver (RX) side only, can efficiently remove crosstalk patterns in straight channels as well as boards with reflections due to via stubs. An eight-lane single-ended RX has been manufactured in 32-nm SOI CMOS to validate our findings. A CTLE and eight-tap decision feedback equalizer equalize the channel without transmitter feedforward equalizer. A continuous time crosstalk canceller reduces precursors by nearest neighbors, while the residual postcursors from all aggressors are suppressed by direct feedback $7\times 8$ -tap decision-feedback crosstalk canceller (DFXC). Measurements with flip-chip packaged RX show that the RX macro can equalize both a 30-dB insertion loss single-ended channel with 0-dB signal-to-crosstalk at Nyquist and a channel with 28-dB attenuation with the signal-to-crosstalk ratio of 6 dB combined with reflections due to via stubs. The RX operates up to 7 Gb/s/pin with PRBS11 data at bit error rate (BER) $300\times 350~\mu \text{m}^{\textbf {2}}$ with an energy efficiency of 5.9 mW/Gb/s from 1-V supply.

10 Gb/s adaptive receive-side merged near-end and far-end crosstalk cancellation circuitry in 65 nm CMOS

Crosstalk between neighboring channels can have significant impact on system bit-error rate (BER) as serial I/O data rates scale above 10 Gb/s. This paper presents receive-side circuitry which merges the cancellation of both near-end and far-end crosstalk (NEXT/FEXT) and can automatically adapt to different channel environments and variations in process, voltage, and temperature. NEXT cancellation is realized with a novel 3-tap FIR filter which combines two traditional FIR filter taps and a continuous-time band-pass filter IIR tap for efficient crosstalk cancellation, with all filter tap coefficients automatically determined via an on-die sign---sign least-mean-square (SS-LMS) adaptation engine. FEXT cancellation is realized by coupling the aggressor signal through a differentiator circuit whose gain is automatically adjusted with a power-detection-based adaptation loop. A prototype fabricated in a general purpose 65-nm CMOS process includes the adaptive NEXT and FEXT circuitry, along with a continuous-time linear equalizer (CTLE) to compensate for frequency-dependent channel loss. Enabling the crosstalk cancellation circuitry while operating at 10 Gb/s over coupled 4-in FR4 transmission line channels with NEXT and FEXT aggressors opens a previously closed eye and allows for a 0.2 UI timing margin at a BER = 10ź9. Total power including the NEXT/FEXT crosstalk cancellation circuitry, CTLE, and high-speed output buffer is 34.6 mW, and the core circuit area occupies 0.3 mm2.

4-Gb/s Parallel Receivers With Adaptive FEXT Cancellation by Pulse Width and Amplitude Calibrations

Two 4-Gb/s parallel receivers with adaptive far-end crosstalk (FEXT) cancellation are presented, which requires a calibration mode. A digitally controlled high-pass filter and a variable-gain amplifier are used to generate the crosstalk cancellation (XTC) signal. The pulse width and amplitude of the XTC signal are automatically calibrated to match the FEXT signal for different channel spacing. It is expected to minimize the residual FEXT signal. Two receivers using the proposed adaptive XTC are fabricated in 40-nm CMOS technology and the core area occupies 0.045 mm2. The power consumption from a 0.9-V supply is 19.8 mW. For two 4-Gb/s PRBS of 27 - 1 passing through FR4 PCB traces with 5-in long and 8-mil spacing, the measured peak-to-peak jitter of data is reduced by 27.78 ps by using the proposed adaptive XTC.

A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation

This paper presents an adaptive far-end crosstalk cancellation scheme for a single-ended parallel receiver. The adaptation engine is embedded in a single representative channel CDR, and the receiver efficiently reduces the crosstalk noise with a minimal cost in hardware and power consumption. In addition, the proposed scheme can be applied to any given CDR and equalizing circuits. The receiver is fabricated in 0.13 μm CMOS technology and achieves a reduction of FEXT-induced jitter up to 75%. The receiver consumes 65 mW at 5 Gb/s (4.3 mW/Gb/s/pin) including a PLL for global clock distribution.

4-Gb/s Parallel Receivers With Adaptive Far-End Crosstalk Cancellation

Two 4-Gb/s parallel receivers with adaptive far-end crosstalk (FEXT) cancellation are presented. By using the highpass filter, the crosstalk cancellation (XTC) signal is generated to compensate the FEXT signal. A power detection loop is adopted to achieve automatic tuning of the XTC coefficient for different channel spacing. The receivers with adaptive XTC are fabricated in 40-nm CMOS technology, and the core area occupies 0.0229 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The maximum power consumption from a 1.2-V supply is 15.6 mW. For two 4-Gb/s pseudorandom binary sequences of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> -1 passing through FR4 printed circuit board traces with 5-in length and 8-mil spacing, the measured peak-topeak jitter of the data is reduced by 32.22 ps by using the adaptive XTC. The measured adaptation time of the power detection loop is 63.44 μs.

A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection

A 2.5-7.5-Gb/s transmitter with one-tap feed-forward equalizer (FFE) and adaptive far-end crosstalk (FEXT) cancellation is presented. To cancel the intersymbol interference, the one-tap FFE is also employed. A crosstalk canceller (XTC) is adapted to cancel FEXT by using inverse pulses. To cancel the FEXT due to the coupled microstrip lines with various spacing, the pulse amplitude of the XTC is digitally controlled by using the proposed duty cycle detection. The one-tap FFE and the XTC are merged together to save the power. This adaptive transmitter is fabricated in a 65-nm CMOS technology. The maximum power consumption from a 1.2-V supply is 26.4 mW, and the core area occupies 0.0307 mm2 . For two 5-in FR4 printed-circuit-board traces with the spacing of 8 mil, the measured rms and peak-to-peak jitters of the recovered data are improved by 10.01 and 48.9 ps, respectively, for a 7.5-Gb/s PRBS of 27 -1 . The measured calibration time of the XTC is 1.17 μs.

Arbitrary Partial FEXT Cancellation in Adaptive Precoding for Multichannel Downstream VDSL

In this paper, we present and analyze a simplified, adaptive precoder for arbitrary partial far-end cross talk (FEXT) cancellation in the downstream of multichannel VDSL. The precoder is based on error signal feedback and is computationally efficient. Furthermore, the partial precoding makes it possible to operate the precoder at any desired complexity, and the system's performance increases with any increase in system complexity. Unlike previous works, in which each user experienced either complete FEXT cancellation or no cancellation at all, the presented precoder can mitigate the FEXT from any desired subset of interfering users for each user. We derive sufficient conditions for convergence of the adaptive precoder, for any partial cancellation scheme, and provide closed form steady state error analysis. The precoder's performance and convergence properties are also demonstrated through simulations.

A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation

This paper presents a low-power receiver with two-tap decision feedback equalization (DFE) and novel far-end crosstalk (FEXT) cancellation capability, implemented in a 45-nm SOI CMOS process. The receiver employs a half-rate speculative DFE architecture to allow for the use of low-power front-end circuitry and CMOS clock buffers. In the proposed architecture, a switched-capacitor sample-hold at the front-end is employed to perform DFE tap summation. This technique is generalized to implement n taps of equalization. The receiver compensates the effect of crosstalk without making a decision on the received aggressor signal. Due to the low-power nature of the switched-capacitor front-end, the crosstalk cancellation is possible with only 33 μW/Gbps/lane power overhead. The receiver was tested over channels with different levels of loss and coupling. The signaling rate with BER <; 10-12 was significantly increased with the use of DFE and crosstalk cancellation scheme for highly coupled and lossy PCB traces. The DFE receiver equalizes 15-Gb/s data over a channel with more than 14-dB loss while consuming about 7.5 mW from a 1.2-V supply. At lower data rates it equalizes channels with over 21-dB loss.

A New Design Framework for Sparse FIR MIMO Equalizers

In this paper, we propose a new framework for the design of sparse finite impulse response (FIR) equalizers. We start by formulating greedy and convex-optimization-based solutions for sparse FIR linear equalizer tap vectors given a maximum allowable loss in the decision-point signal-to-noise ratio. Then, we extend our formulation to decision feedback equalizers and multiple-antenna systems. This is followed by further generalization to the channel shortening setup which is important for communication systems operating over broadband channels with long channel impulse responses. We propose a novel approach to design a sparse target impulse response. Finally, as an application of current practical interest, we consider self far-end crosstalk cancellation on vectored very high-speed digital subscriber line systems for cellular backhaul networks.

Adaptive two-stage equalisation and FEXT cancellation architecture for 10GBASE-T system

For 10GBASE-T systems, variation in a multiple-input-multiple-output (MIMO) channel degrades the decision-point signal-to-noise ratio (DP-SNR) owing to imperfect pre-equalisation in the Tomlinson–Harashima precoding (THP) at the transmitter sides and catastrophic error propagation in far-end crosstalk (FEXT) cancellation at the receiver sides. Moreover, by using fixed THP coefficients during data transmission, as specified in the 10GBASE-T standard, and the non-linearity of THP pose challenges in the design of adaptive receivers. The authors propose an adaptive two-stage equalisation and FEXT cancellation (TS-EFC) architecture without updating the THP coefficients to combat channel variation at both the transmitter and receiver sides. In the first stage, we propose a new non-decision-directed FEXT canceller at the transmitter side using a joint training architecture to avoid error propagation. In the second stage, we devise an adaptive MIMO equaliser together with a novel pre-processing unit at the receiver side to combat channel variation. The pre-processing unit can eliminate the non-linearity issue by estimating both effective data sequences and precoded channel inputs. In addition, we develop a block least mean square algorithm that exploits the properties of two-dimensional modulated symbols for updating coefficients of the adaptive MIMO equaliser. Simulation results show that our TS-EFC architecture is robust against channel variation and significantly improves the DP-SNR. It eliminates the error propagation and also achieves faster convergence rates during the adaptation process.

A Low Complexity Linear Precoding Technique for Next Generation VDSL Downstream Transmission Over Copper

In this paper, we study a simplified linear precoding scheme for far-end crosstalk (FEXT) cancellation in very high bit-rate digital subscriber line (VDSL) downstream transmission. We compare the proposed method to zero-forcing (ZF) FEXT cancellation and show that for multipair VDSL systems the method achieves rates that are close to the ZF precoding method. We also derive simple lower bounds on the performance that allows us to predict the performance of the proposed algorithm on each tone. We end up with testing the proposed method on theoretical and empirical channels. This is the first extensive study of VDSL precoding on measured channel data. The proposed method is less complex than ZF precoding and, therefore, alleviates the computational load at the initialization and tracking of precoded VDSL or VDSL2 systems. Finally, we discuss implementation complexity in terms of total Silicon area and show that the method has favorable implementation complexity, since only channel coefficients need to be stored during steady-state transmission.

Monte Carlo FEXT cancellers for DSL channels

Crosstalk coupling is a severe impairment to transmission on twisted-pair copper cables such as digital subscriber telephone loops (DSLs). In this paper, we investigate the problem of far-end crosstalk (FEXT) cancellation for DSL. We propose a new soft interference canceller for coordinated self-FEXT cancellation across multiple twisted-pairs. The proposed receiver treats the FEXT-impaired channel as a multiple-input multiple-output (MIMO) channel; it uses the sequential Monte Carlo (SMC) technique to exploit the sequential structure inherent in iterative cancellation techniques for MIMO decoding. On telephone loops with strong FEXT, the proposed algorithm shows 0.5-dB coding gain with respect to previously proposed techniques. Furthermore, being soft-input-soft-output in nature, the proposed SMC receiver can iteratively exchange extrinsic information with a MAP decoder to successively cancel FEXT, leading to a turbo FEXT canceller.

Vectored transmission for digital subscriber line systems

This paper describes the "vectored" transmission technique for digital subscriber line (DSL) systems, which utilizes user coordination at the central office or optical network unit. This method exploits the colocation of the downstream transmitters and of the upstream receivers, in order to achieve far-end crosstalk (FEXT) cancellation and perform multiuser transmission optimization. The performance improvements are particularly pronounced in environments with strong FEXT such as in very high-speed DSL. Discrete multitone is employed for each user with additional constraints on the cyclic prefix length and with the assumption of block-synchronized transmission and reception for downstream and upstream transmission correspondingly. Within each tone, upstream crosstalk is removed by multiple-input-multiple-output decision feedback at the receiving side, while downstream crosstalk is eliminated by analogous preprocessing at the transmitting side. Additionally, the issue of transmission energy allocation in frequency and among users is addressed. Assuming frequency-division duplexing, the corresponding optimization problem is formulated and solved via convex programming both for a fixed upstream-downstream band plan and for a dynamically programmable band plan. The case of power backoff as a means to reduce the impact of crosstalk on alien systems is also treated. Interestingly, the performance of the proposed methods is shown to be very close to known information theory bounds.